1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (C) 2021 Marvell. */ 3 4 #include <linux/soc/marvell/octeontx2/asm.h> 5 #include "otx2_cptpf.h" 6 #include "otx2_cptvf.h" 7 #include "otx2_cptlf.h" 8 #include "cn10k_cpt.h" 9 10 static struct cpt_hw_ops otx2_hw_ops = { 11 .send_cmd = otx2_cpt_send_cmd, 12 .cpt_get_compcode = otx2_cpt_get_compcode, 13 .cpt_get_uc_compcode = otx2_cpt_get_uc_compcode, 14 }; 15 16 static struct cpt_hw_ops cn10k_hw_ops = { 17 .send_cmd = cn10k_cpt_send_cmd, 18 .cpt_get_compcode = cn10k_cpt_get_compcode, 19 .cpt_get_uc_compcode = cn10k_cpt_get_uc_compcode, 20 }; 21 22 void cn10k_cpt_send_cmd(union otx2_cpt_inst_s *cptinst, u32 insts_num, 23 struct otx2_cptlf_info *lf) 24 { 25 void __iomem *lmtline = lf->lmtline; 26 u64 val = (lf->slot & 0x7FF); 27 u64 tar_addr = 0; 28 29 /* tar_addr<6:4> = Size of first LMTST - 1 in units of 128b. */ 30 tar_addr |= (__force u64)lf->ioreg | 31 (((OTX2_CPT_INST_SIZE/16) - 1) & 0x7) << 4; 32 /* 33 * Make sure memory areas pointed in CPT_INST_S 34 * are flushed before the instruction is sent to CPT 35 */ 36 dma_wmb(); 37 38 /* Copy CPT command to LMTLINE */ 39 memcpy_toio(lmtline, cptinst, insts_num * OTX2_CPT_INST_SIZE); 40 cn10k_lmt_flush(val, tar_addr); 41 } 42 43 int cn10k_cptpf_lmtst_init(struct otx2_cptpf_dev *cptpf) 44 { 45 struct pci_dev *pdev = cptpf->pdev; 46 resource_size_t size; 47 u64 lmt_base; 48 49 if (!test_bit(CN10K_LMTST, &cptpf->cap_flag)) { 50 cptpf->lfs.ops = &otx2_hw_ops; 51 return 0; 52 } 53 54 cptpf->lfs.ops = &cn10k_hw_ops; 55 lmt_base = readq(cptpf->reg_base + RVU_PF_LMTLINE_ADDR); 56 if (!lmt_base) { 57 dev_err(&pdev->dev, "PF LMTLINE address not configured\n"); 58 return -ENOMEM; 59 } 60 size = pci_resource_len(pdev, PCI_MBOX_BAR_NUM); 61 size -= ((1 + cptpf->max_vfs) * MBOX_SIZE); 62 cptpf->lfs.lmt_base = devm_ioremap_wc(&pdev->dev, lmt_base, size); 63 if (!cptpf->lfs.lmt_base) { 64 dev_err(&pdev->dev, 65 "Mapping of PF LMTLINE address failed\n"); 66 return -ENOMEM; 67 } 68 69 return 0; 70 } 71 72 int cn10k_cptvf_lmtst_init(struct otx2_cptvf_dev *cptvf) 73 { 74 struct pci_dev *pdev = cptvf->pdev; 75 resource_size_t offset, size; 76 77 if (!test_bit(CN10K_LMTST, &cptvf->cap_flag)) { 78 cptvf->lfs.ops = &otx2_hw_ops; 79 return 0; 80 } 81 82 cptvf->lfs.ops = &cn10k_hw_ops; 83 offset = pci_resource_start(pdev, PCI_MBOX_BAR_NUM); 84 size = pci_resource_len(pdev, PCI_MBOX_BAR_NUM); 85 /* Map VF LMILINE region */ 86 cptvf->lfs.lmt_base = devm_ioremap_wc(&pdev->dev, offset, size); 87 if (!cptvf->lfs.lmt_base) { 88 dev_err(&pdev->dev, "Unable to map BAR4\n"); 89 return -ENOMEM; 90 } 91 92 return 0; 93 } 94