1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell OcteonTX CPT driver 3 * 4 * Copyright (C) 2019 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/ctype.h> 12 #include <linux/firmware.h> 13 #include "otx_cpt_common.h" 14 #include "otx_cptpf_ucode.h" 15 #include "otx_cptpf.h" 16 17 #define CSR_DELAY 30 18 /* Tar archive defines */ 19 #define TAR_MAGIC "ustar" 20 #define TAR_MAGIC_LEN 6 21 #define TAR_BLOCK_LEN 512 22 #define REGTYPE '0' 23 #define AREGTYPE '\0' 24 25 /* tar header as defined in POSIX 1003.1-1990. */ 26 struct tar_hdr_t { 27 char name[100]; 28 char mode[8]; 29 char uid[8]; 30 char gid[8]; 31 char size[12]; 32 char mtime[12]; 33 char chksum[8]; 34 char typeflag; 35 char linkname[100]; 36 char magic[6]; 37 char version[2]; 38 char uname[32]; 39 char gname[32]; 40 char devmajor[8]; 41 char devminor[8]; 42 char prefix[155]; 43 }; 44 45 struct tar_blk_t { 46 union { 47 struct tar_hdr_t hdr; 48 char block[TAR_BLOCK_LEN]; 49 }; 50 }; 51 52 struct tar_arch_info_t { 53 struct list_head ucodes; 54 const struct firmware *fw; 55 }; 56 57 static struct otx_cpt_bitmap get_cores_bmap(struct device *dev, 58 struct otx_cpt_eng_grp_info *eng_grp) 59 { 60 struct otx_cpt_bitmap bmap = { {0} }; 61 bool found = false; 62 int i; 63 64 if (eng_grp->g->engs_num > OTX_CPT_MAX_ENGINES) { 65 dev_err(dev, "unsupported number of engines %d on octeontx", 66 eng_grp->g->engs_num); 67 return bmap; 68 } 69 70 for (i = 0; i < OTX_CPT_MAX_ETYPES_PER_GRP; i++) { 71 if (eng_grp->engs[i].type) { 72 bitmap_or(bmap.bits, bmap.bits, 73 eng_grp->engs[i].bmap, 74 eng_grp->g->engs_num); 75 bmap.size = eng_grp->g->engs_num; 76 found = true; 77 } 78 } 79 80 if (!found) 81 dev_err(dev, "No engines reserved for engine group %d", 82 eng_grp->idx); 83 return bmap; 84 } 85 86 static int is_eng_type(int val, int eng_type) 87 { 88 return val & (1 << eng_type); 89 } 90 91 static int dev_supports_eng_type(struct otx_cpt_eng_grps *eng_grps, 92 int eng_type) 93 { 94 return is_eng_type(eng_grps->eng_types_supported, eng_type); 95 } 96 97 static void set_ucode_filename(struct otx_cpt_ucode *ucode, 98 const char *filename) 99 { 100 strlcpy(ucode->filename, filename, OTX_CPT_UCODE_NAME_LENGTH); 101 } 102 103 static char *get_eng_type_str(int eng_type) 104 { 105 char *str = "unknown"; 106 107 switch (eng_type) { 108 case OTX_CPT_SE_TYPES: 109 str = "SE"; 110 break; 111 112 case OTX_CPT_AE_TYPES: 113 str = "AE"; 114 break; 115 } 116 return str; 117 } 118 119 static char *get_ucode_type_str(int ucode_type) 120 { 121 char *str = "unknown"; 122 123 switch (ucode_type) { 124 case (1 << OTX_CPT_SE_TYPES): 125 str = "SE"; 126 break; 127 128 case (1 << OTX_CPT_AE_TYPES): 129 str = "AE"; 130 break; 131 } 132 return str; 133 } 134 135 static int get_ucode_type(struct otx_cpt_ucode_hdr *ucode_hdr, int *ucode_type) 136 { 137 char tmp_ver_str[OTX_CPT_UCODE_VER_STR_SZ]; 138 u32 i, val = 0; 139 u8 nn; 140 141 strlcpy(tmp_ver_str, ucode_hdr->ver_str, OTX_CPT_UCODE_VER_STR_SZ); 142 for (i = 0; i < strlen(tmp_ver_str); i++) 143 tmp_ver_str[i] = tolower(tmp_ver_str[i]); 144 145 nn = ucode_hdr->ver_num.nn; 146 if (strnstr(tmp_ver_str, "se-", OTX_CPT_UCODE_VER_STR_SZ) && 147 (nn == OTX_CPT_SE_UC_TYPE1 || nn == OTX_CPT_SE_UC_TYPE2 || 148 nn == OTX_CPT_SE_UC_TYPE3)) 149 val |= 1 << OTX_CPT_SE_TYPES; 150 if (strnstr(tmp_ver_str, "ae", OTX_CPT_UCODE_VER_STR_SZ) && 151 nn == OTX_CPT_AE_UC_TYPE) 152 val |= 1 << OTX_CPT_AE_TYPES; 153 154 *ucode_type = val; 155 156 if (!val) 157 return -EINVAL; 158 if (is_eng_type(val, OTX_CPT_AE_TYPES) && 159 is_eng_type(val, OTX_CPT_SE_TYPES)) 160 return -EINVAL; 161 return 0; 162 } 163 164 static int is_mem_zero(const char *ptr, int size) 165 { 166 int i; 167 168 for (i = 0; i < size; i++) { 169 if (ptr[i]) 170 return 0; 171 } 172 return 1; 173 } 174 175 static int cpt_set_ucode_base(struct otx_cpt_eng_grp_info *eng_grp, void *obj) 176 { 177 struct otx_cpt_device *cpt = (struct otx_cpt_device *) obj; 178 dma_addr_t dma_addr; 179 struct otx_cpt_bitmap bmap; 180 int i; 181 182 bmap = get_cores_bmap(&cpt->pdev->dev, eng_grp); 183 if (!bmap.size) 184 return -EINVAL; 185 186 if (eng_grp->mirror.is_ena) 187 dma_addr = 188 eng_grp->g->grp[eng_grp->mirror.idx].ucode[0].align_dma; 189 else 190 dma_addr = eng_grp->ucode[0].align_dma; 191 192 /* 193 * Set UCODE_BASE only for the cores which are not used, 194 * other cores should have already valid UCODE_BASE set 195 */ 196 for_each_set_bit(i, bmap.bits, bmap.size) 197 if (!eng_grp->g->eng_ref_cnt[i]) 198 writeq((u64) dma_addr, cpt->reg_base + 199 OTX_CPT_PF_ENGX_UCODE_BASE(i)); 200 return 0; 201 } 202 203 static int cpt_detach_and_disable_cores(struct otx_cpt_eng_grp_info *eng_grp, 204 void *obj) 205 { 206 struct otx_cpt_device *cpt = (struct otx_cpt_device *) obj; 207 struct otx_cpt_bitmap bmap = { {0} }; 208 int timeout = 10; 209 int i, busy; 210 u64 reg; 211 212 bmap = get_cores_bmap(&cpt->pdev->dev, eng_grp); 213 if (!bmap.size) 214 return -EINVAL; 215 216 /* Detach the cores from group */ 217 reg = readq(cpt->reg_base + OTX_CPT_PF_GX_EN(eng_grp->idx)); 218 for_each_set_bit(i, bmap.bits, bmap.size) { 219 if (reg & (1ull << i)) { 220 eng_grp->g->eng_ref_cnt[i]--; 221 reg &= ~(1ull << i); 222 } 223 } 224 writeq(reg, cpt->reg_base + OTX_CPT_PF_GX_EN(eng_grp->idx)); 225 226 /* Wait for cores to become idle */ 227 do { 228 busy = 0; 229 usleep_range(10000, 20000); 230 if (timeout-- < 0) 231 return -EBUSY; 232 233 reg = readq(cpt->reg_base + OTX_CPT_PF_EXEC_BUSY); 234 for_each_set_bit(i, bmap.bits, bmap.size) 235 if (reg & (1ull << i)) { 236 busy = 1; 237 break; 238 } 239 } while (busy); 240 241 /* Disable the cores only if they are not used anymore */ 242 reg = readq(cpt->reg_base + OTX_CPT_PF_EXE_CTL); 243 for_each_set_bit(i, bmap.bits, bmap.size) 244 if (!eng_grp->g->eng_ref_cnt[i]) 245 reg &= ~(1ull << i); 246 writeq(reg, cpt->reg_base + OTX_CPT_PF_EXE_CTL); 247 248 return 0; 249 } 250 251 static int cpt_attach_and_enable_cores(struct otx_cpt_eng_grp_info *eng_grp, 252 void *obj) 253 { 254 struct otx_cpt_device *cpt = (struct otx_cpt_device *) obj; 255 struct otx_cpt_bitmap bmap; 256 u64 reg; 257 int i; 258 259 bmap = get_cores_bmap(&cpt->pdev->dev, eng_grp); 260 if (!bmap.size) 261 return -EINVAL; 262 263 /* Attach the cores to the group */ 264 reg = readq(cpt->reg_base + OTX_CPT_PF_GX_EN(eng_grp->idx)); 265 for_each_set_bit(i, bmap.bits, bmap.size) { 266 if (!(reg & (1ull << i))) { 267 eng_grp->g->eng_ref_cnt[i]++; 268 reg |= 1ull << i; 269 } 270 } 271 writeq(reg, cpt->reg_base + OTX_CPT_PF_GX_EN(eng_grp->idx)); 272 273 /* Enable the cores */ 274 reg = readq(cpt->reg_base + OTX_CPT_PF_EXE_CTL); 275 for_each_set_bit(i, bmap.bits, bmap.size) 276 reg |= 1ull << i; 277 writeq(reg, cpt->reg_base + OTX_CPT_PF_EXE_CTL); 278 279 return 0; 280 } 281 282 static int process_tar_file(struct device *dev, 283 struct tar_arch_info_t *tar_arch, char *filename, 284 const u8 *data, u32 size) 285 { 286 struct tar_ucode_info_t *tar_info; 287 struct otx_cpt_ucode_hdr *ucode_hdr; 288 int ucode_type, ucode_size; 289 290 /* 291 * If size is less than microcode header size then don't report 292 * an error because it might not be microcode file, just process 293 * next file from archive 294 */ 295 if (size < sizeof(struct otx_cpt_ucode_hdr)) 296 return 0; 297 298 ucode_hdr = (struct otx_cpt_ucode_hdr *) data; 299 /* 300 * If microcode version can't be found don't report an error 301 * because it might not be microcode file, just process next file 302 */ 303 if (get_ucode_type(ucode_hdr, &ucode_type)) 304 return 0; 305 306 ucode_size = ntohl(ucode_hdr->code_length) * 2; 307 if (!ucode_size || (size < round_up(ucode_size, 16) + 308 sizeof(struct otx_cpt_ucode_hdr) + OTX_CPT_UCODE_SIGN_LEN)) { 309 dev_err(dev, "Ucode %s invalid size", filename); 310 return -EINVAL; 311 } 312 313 tar_info = kzalloc(sizeof(struct tar_ucode_info_t), GFP_KERNEL); 314 if (!tar_info) 315 return -ENOMEM; 316 317 tar_info->ucode_ptr = data; 318 set_ucode_filename(&tar_info->ucode, filename); 319 memcpy(tar_info->ucode.ver_str, ucode_hdr->ver_str, 320 OTX_CPT_UCODE_VER_STR_SZ); 321 tar_info->ucode.ver_num = ucode_hdr->ver_num; 322 tar_info->ucode.type = ucode_type; 323 tar_info->ucode.size = ucode_size; 324 list_add_tail(&tar_info->list, &tar_arch->ucodes); 325 326 return 0; 327 } 328 329 static void release_tar_archive(struct tar_arch_info_t *tar_arch) 330 { 331 struct tar_ucode_info_t *curr, *temp; 332 333 if (!tar_arch) 334 return; 335 336 list_for_each_entry_safe(curr, temp, &tar_arch->ucodes, list) { 337 list_del(&curr->list); 338 kfree(curr); 339 } 340 341 if (tar_arch->fw) 342 release_firmware(tar_arch->fw); 343 kfree(tar_arch); 344 } 345 346 static struct tar_ucode_info_t *get_uc_from_tar_archive( 347 struct tar_arch_info_t *tar_arch, 348 int ucode_type) 349 { 350 struct tar_ucode_info_t *curr, *uc_found = NULL; 351 352 list_for_each_entry(curr, &tar_arch->ucodes, list) { 353 if (!is_eng_type(curr->ucode.type, ucode_type)) 354 continue; 355 356 if (!uc_found) { 357 uc_found = curr; 358 continue; 359 } 360 361 switch (ucode_type) { 362 case OTX_CPT_AE_TYPES: 363 break; 364 365 case OTX_CPT_SE_TYPES: 366 if (uc_found->ucode.ver_num.nn == OTX_CPT_SE_UC_TYPE2 || 367 (uc_found->ucode.ver_num.nn == OTX_CPT_SE_UC_TYPE3 368 && curr->ucode.ver_num.nn == OTX_CPT_SE_UC_TYPE1)) 369 uc_found = curr; 370 break; 371 } 372 } 373 374 return uc_found; 375 } 376 377 static void print_tar_dbg_info(struct tar_arch_info_t *tar_arch, 378 char *tar_filename) 379 { 380 struct tar_ucode_info_t *curr; 381 382 pr_debug("Tar archive filename %s", tar_filename); 383 pr_debug("Tar archive pointer %p, size %ld", tar_arch->fw->data, 384 tar_arch->fw->size); 385 list_for_each_entry(curr, &tar_arch->ucodes, list) { 386 pr_debug("Ucode filename %s", curr->ucode.filename); 387 pr_debug("Ucode version string %s", curr->ucode.ver_str); 388 pr_debug("Ucode version %d.%d.%d.%d", 389 curr->ucode.ver_num.nn, curr->ucode.ver_num.xx, 390 curr->ucode.ver_num.yy, curr->ucode.ver_num.zz); 391 pr_debug("Ucode type (%d) %s", curr->ucode.type, 392 get_ucode_type_str(curr->ucode.type)); 393 pr_debug("Ucode size %d", curr->ucode.size); 394 pr_debug("Ucode ptr %p\n", curr->ucode_ptr); 395 } 396 } 397 398 static struct tar_arch_info_t *load_tar_archive(struct device *dev, 399 char *tar_filename) 400 { 401 struct tar_arch_info_t *tar_arch = NULL; 402 struct tar_blk_t *tar_blk; 403 unsigned int cur_size; 404 size_t tar_offs = 0; 405 size_t tar_size; 406 int ret; 407 408 tar_arch = kzalloc(sizeof(struct tar_arch_info_t), GFP_KERNEL); 409 if (!tar_arch) 410 return NULL; 411 412 INIT_LIST_HEAD(&tar_arch->ucodes); 413 414 /* Load tar archive */ 415 ret = request_firmware(&tar_arch->fw, tar_filename, dev); 416 if (ret) 417 goto release_tar_arch; 418 419 if (tar_arch->fw->size < TAR_BLOCK_LEN) { 420 dev_err(dev, "Invalid tar archive %s ", tar_filename); 421 goto release_tar_arch; 422 } 423 424 tar_size = tar_arch->fw->size; 425 tar_blk = (struct tar_blk_t *) tar_arch->fw->data; 426 if (strncmp(tar_blk->hdr.magic, TAR_MAGIC, TAR_MAGIC_LEN - 1)) { 427 dev_err(dev, "Unsupported format of tar archive %s", 428 tar_filename); 429 goto release_tar_arch; 430 } 431 432 while (1) { 433 /* Read current file size */ 434 ret = kstrtouint(tar_blk->hdr.size, 8, &cur_size); 435 if (ret) 436 goto release_tar_arch; 437 438 if (tar_offs + cur_size > tar_size || 439 tar_offs + 2*TAR_BLOCK_LEN > tar_size) { 440 dev_err(dev, "Invalid tar archive %s ", tar_filename); 441 goto release_tar_arch; 442 } 443 444 tar_offs += TAR_BLOCK_LEN; 445 if (tar_blk->hdr.typeflag == REGTYPE || 446 tar_blk->hdr.typeflag == AREGTYPE) { 447 ret = process_tar_file(dev, tar_arch, 448 tar_blk->hdr.name, 449 &tar_arch->fw->data[tar_offs], 450 cur_size); 451 if (ret) 452 goto release_tar_arch; 453 } 454 455 tar_offs += (cur_size/TAR_BLOCK_LEN) * TAR_BLOCK_LEN; 456 if (cur_size % TAR_BLOCK_LEN) 457 tar_offs += TAR_BLOCK_LEN; 458 459 /* Check for the end of the archive */ 460 if (tar_offs + 2*TAR_BLOCK_LEN > tar_size) { 461 dev_err(dev, "Invalid tar archive %s ", tar_filename); 462 goto release_tar_arch; 463 } 464 465 if (is_mem_zero(&tar_arch->fw->data[tar_offs], 466 2*TAR_BLOCK_LEN)) 467 break; 468 469 /* Read next block from tar archive */ 470 tar_blk = (struct tar_blk_t *) &tar_arch->fw->data[tar_offs]; 471 } 472 473 print_tar_dbg_info(tar_arch, tar_filename); 474 return tar_arch; 475 release_tar_arch: 476 release_tar_archive(tar_arch); 477 return NULL; 478 } 479 480 static struct otx_cpt_engs_rsvd *find_engines_by_type( 481 struct otx_cpt_eng_grp_info *eng_grp, 482 int eng_type) 483 { 484 int i; 485 486 for (i = 0; i < OTX_CPT_MAX_ETYPES_PER_GRP; i++) { 487 if (!eng_grp->engs[i].type) 488 continue; 489 490 if (eng_grp->engs[i].type == eng_type) 491 return &eng_grp->engs[i]; 492 } 493 return NULL; 494 } 495 496 int otx_cpt_uc_supports_eng_type(struct otx_cpt_ucode *ucode, int eng_type) 497 { 498 return is_eng_type(ucode->type, eng_type); 499 } 500 EXPORT_SYMBOL_GPL(otx_cpt_uc_supports_eng_type); 501 502 int otx_cpt_eng_grp_has_eng_type(struct otx_cpt_eng_grp_info *eng_grp, 503 int eng_type) 504 { 505 struct otx_cpt_engs_rsvd *engs; 506 507 engs = find_engines_by_type(eng_grp, eng_type); 508 509 return (engs != NULL ? 1 : 0); 510 } 511 EXPORT_SYMBOL_GPL(otx_cpt_eng_grp_has_eng_type); 512 513 static void print_ucode_info(struct otx_cpt_eng_grp_info *eng_grp, 514 char *buf, int size) 515 { 516 if (eng_grp->mirror.is_ena) { 517 scnprintf(buf, size, "%s (shared with engine_group%d)", 518 eng_grp->g->grp[eng_grp->mirror.idx].ucode[0].ver_str, 519 eng_grp->mirror.idx); 520 } else { 521 scnprintf(buf, size, "%s", eng_grp->ucode[0].ver_str); 522 } 523 } 524 525 static void print_engs_info(struct otx_cpt_eng_grp_info *eng_grp, 526 char *buf, int size, int idx) 527 { 528 struct otx_cpt_engs_rsvd *mirrored_engs = NULL; 529 struct otx_cpt_engs_rsvd *engs; 530 int len, i; 531 532 buf[0] = '\0'; 533 for (i = 0; i < OTX_CPT_MAX_ETYPES_PER_GRP; i++) { 534 engs = &eng_grp->engs[i]; 535 if (!engs->type) 536 continue; 537 if (idx != -1 && idx != i) 538 continue; 539 540 if (eng_grp->mirror.is_ena) 541 mirrored_engs = find_engines_by_type( 542 &eng_grp->g->grp[eng_grp->mirror.idx], 543 engs->type); 544 if (i > 0 && idx == -1) { 545 len = strlen(buf); 546 scnprintf(buf+len, size-len, ", "); 547 } 548 549 len = strlen(buf); 550 scnprintf(buf+len, size-len, "%d %s ", mirrored_engs ? 551 engs->count + mirrored_engs->count : engs->count, 552 get_eng_type_str(engs->type)); 553 if (mirrored_engs) { 554 len = strlen(buf); 555 scnprintf(buf+len, size-len, 556 "(%d shared with engine_group%d) ", 557 engs->count <= 0 ? engs->count + 558 mirrored_engs->count : mirrored_engs->count, 559 eng_grp->mirror.idx); 560 } 561 } 562 } 563 564 static void print_ucode_dbg_info(struct otx_cpt_ucode *ucode) 565 { 566 pr_debug("Ucode info"); 567 pr_debug("Ucode version string %s", ucode->ver_str); 568 pr_debug("Ucode version %d.%d.%d.%d", ucode->ver_num.nn, 569 ucode->ver_num.xx, ucode->ver_num.yy, ucode->ver_num.zz); 570 pr_debug("Ucode type %s", get_ucode_type_str(ucode->type)); 571 pr_debug("Ucode size %d", ucode->size); 572 pr_debug("Ucode virt address %16.16llx", (u64)ucode->align_va); 573 pr_debug("Ucode phys address %16.16llx\n", ucode->align_dma); 574 } 575 576 static void cpt_print_engines_mask(struct otx_cpt_eng_grp_info *eng_grp, 577 struct device *dev, char *buf, int size) 578 { 579 struct otx_cpt_bitmap bmap; 580 u32 mask[2]; 581 582 bmap = get_cores_bmap(dev, eng_grp); 583 if (!bmap.size) { 584 scnprintf(buf, size, "unknown"); 585 return; 586 } 587 bitmap_to_arr32(mask, bmap.bits, bmap.size); 588 scnprintf(buf, size, "%8.8x %8.8x", mask[1], mask[0]); 589 } 590 591 592 static void print_dbg_info(struct device *dev, 593 struct otx_cpt_eng_grps *eng_grps) 594 { 595 char engs_info[2*OTX_CPT_UCODE_NAME_LENGTH]; 596 struct otx_cpt_eng_grp_info *mirrored_grp; 597 char engs_mask[OTX_CPT_UCODE_NAME_LENGTH]; 598 struct otx_cpt_eng_grp_info *grp; 599 struct otx_cpt_engs_rsvd *engs; 600 u32 mask[4]; 601 int i, j; 602 603 pr_debug("Engine groups global info"); 604 pr_debug("max SE %d, max AE %d", 605 eng_grps->avail.max_se_cnt, eng_grps->avail.max_ae_cnt); 606 pr_debug("free SE %d", eng_grps->avail.se_cnt); 607 pr_debug("free AE %d", eng_grps->avail.ae_cnt); 608 609 for (i = 0; i < OTX_CPT_MAX_ENGINE_GROUPS; i++) { 610 grp = &eng_grps->grp[i]; 611 pr_debug("engine_group%d, state %s", i, grp->is_enabled ? 612 "enabled" : "disabled"); 613 if (grp->is_enabled) { 614 mirrored_grp = &eng_grps->grp[grp->mirror.idx]; 615 pr_debug("Ucode0 filename %s, version %s", 616 grp->mirror.is_ena ? 617 mirrored_grp->ucode[0].filename : 618 grp->ucode[0].filename, 619 grp->mirror.is_ena ? 620 mirrored_grp->ucode[0].ver_str : 621 grp->ucode[0].ver_str); 622 } 623 624 for (j = 0; j < OTX_CPT_MAX_ETYPES_PER_GRP; j++) { 625 engs = &grp->engs[j]; 626 if (engs->type) { 627 print_engs_info(grp, engs_info, 628 2*OTX_CPT_UCODE_NAME_LENGTH, j); 629 pr_debug("Slot%d: %s", j, engs_info); 630 bitmap_to_arr32(mask, engs->bmap, 631 eng_grps->engs_num); 632 pr_debug("Mask: %8.8x %8.8x %8.8x %8.8x", 633 mask[3], mask[2], mask[1], mask[0]); 634 } else 635 pr_debug("Slot%d not used", j); 636 } 637 if (grp->is_enabled) { 638 cpt_print_engines_mask(grp, dev, engs_mask, 639 OTX_CPT_UCODE_NAME_LENGTH); 640 pr_debug("Cmask: %s", engs_mask); 641 } 642 } 643 } 644 645 static int update_engines_avail_count(struct device *dev, 646 struct otx_cpt_engs_available *avail, 647 struct otx_cpt_engs_rsvd *engs, int val) 648 { 649 switch (engs->type) { 650 case OTX_CPT_SE_TYPES: 651 avail->se_cnt += val; 652 break; 653 654 case OTX_CPT_AE_TYPES: 655 avail->ae_cnt += val; 656 break; 657 658 default: 659 dev_err(dev, "Invalid engine type %d\n", engs->type); 660 return -EINVAL; 661 } 662 663 return 0; 664 } 665 666 static int update_engines_offset(struct device *dev, 667 struct otx_cpt_engs_available *avail, 668 struct otx_cpt_engs_rsvd *engs) 669 { 670 switch (engs->type) { 671 case OTX_CPT_SE_TYPES: 672 engs->offset = 0; 673 break; 674 675 case OTX_CPT_AE_TYPES: 676 engs->offset = avail->max_se_cnt; 677 break; 678 679 default: 680 dev_err(dev, "Invalid engine type %d\n", engs->type); 681 return -EINVAL; 682 } 683 684 return 0; 685 } 686 687 static int release_engines(struct device *dev, struct otx_cpt_eng_grp_info *grp) 688 { 689 int i, ret = 0; 690 691 for (i = 0; i < OTX_CPT_MAX_ETYPES_PER_GRP; i++) { 692 if (!grp->engs[i].type) 693 continue; 694 695 if (grp->engs[i].count > 0) { 696 ret = update_engines_avail_count(dev, &grp->g->avail, 697 &grp->engs[i], 698 grp->engs[i].count); 699 if (ret) 700 return ret; 701 } 702 703 grp->engs[i].type = 0; 704 grp->engs[i].count = 0; 705 grp->engs[i].offset = 0; 706 grp->engs[i].ucode = NULL; 707 bitmap_zero(grp->engs[i].bmap, grp->g->engs_num); 708 } 709 710 return 0; 711 } 712 713 static int do_reserve_engines(struct device *dev, 714 struct otx_cpt_eng_grp_info *grp, 715 struct otx_cpt_engines *req_engs) 716 { 717 struct otx_cpt_engs_rsvd *engs = NULL; 718 int i, ret; 719 720 for (i = 0; i < OTX_CPT_MAX_ETYPES_PER_GRP; i++) { 721 if (!grp->engs[i].type) { 722 engs = &grp->engs[i]; 723 break; 724 } 725 } 726 727 if (!engs) 728 return -ENOMEM; 729 730 engs->type = req_engs->type; 731 engs->count = req_engs->count; 732 733 ret = update_engines_offset(dev, &grp->g->avail, engs); 734 if (ret) 735 return ret; 736 737 if (engs->count > 0) { 738 ret = update_engines_avail_count(dev, &grp->g->avail, engs, 739 -engs->count); 740 if (ret) 741 return ret; 742 } 743 744 return 0; 745 } 746 747 static int check_engines_availability(struct device *dev, 748 struct otx_cpt_eng_grp_info *grp, 749 struct otx_cpt_engines *req_eng) 750 { 751 int avail_cnt = 0; 752 753 switch (req_eng->type) { 754 case OTX_CPT_SE_TYPES: 755 avail_cnt = grp->g->avail.se_cnt; 756 break; 757 758 case OTX_CPT_AE_TYPES: 759 avail_cnt = grp->g->avail.ae_cnt; 760 break; 761 762 default: 763 dev_err(dev, "Invalid engine type %d\n", req_eng->type); 764 return -EINVAL; 765 } 766 767 if (avail_cnt < req_eng->count) { 768 dev_err(dev, 769 "Error available %s engines %d < than requested %d", 770 get_eng_type_str(req_eng->type), 771 avail_cnt, req_eng->count); 772 return -EBUSY; 773 } 774 775 return 0; 776 } 777 778 static int reserve_engines(struct device *dev, struct otx_cpt_eng_grp_info *grp, 779 struct otx_cpt_engines *req_engs, int req_cnt) 780 { 781 int i, ret; 782 783 /* Validate if a number of requested engines is available */ 784 for (i = 0; i < req_cnt; i++) { 785 ret = check_engines_availability(dev, grp, &req_engs[i]); 786 if (ret) 787 return ret; 788 } 789 790 /* Reserve requested engines for this engine group */ 791 for (i = 0; i < req_cnt; i++) { 792 ret = do_reserve_engines(dev, grp, &req_engs[i]); 793 if (ret) 794 return ret; 795 } 796 return 0; 797 } 798 799 static ssize_t eng_grp_info_show(struct device *dev, 800 struct device_attribute *attr, 801 char *buf) 802 { 803 char ucode_info[2*OTX_CPT_UCODE_NAME_LENGTH]; 804 char engs_info[2*OTX_CPT_UCODE_NAME_LENGTH]; 805 char engs_mask[OTX_CPT_UCODE_NAME_LENGTH]; 806 struct otx_cpt_eng_grp_info *eng_grp; 807 int ret; 808 809 eng_grp = container_of(attr, struct otx_cpt_eng_grp_info, info_attr); 810 mutex_lock(&eng_grp->g->lock); 811 812 print_engs_info(eng_grp, engs_info, 2*OTX_CPT_UCODE_NAME_LENGTH, -1); 813 print_ucode_info(eng_grp, ucode_info, 2*OTX_CPT_UCODE_NAME_LENGTH); 814 cpt_print_engines_mask(eng_grp, dev, engs_mask, 815 OTX_CPT_UCODE_NAME_LENGTH); 816 ret = scnprintf(buf, PAGE_SIZE, 817 "Microcode : %s\nEngines: %s\nEngines mask: %s\n", 818 ucode_info, engs_info, engs_mask); 819 820 mutex_unlock(&eng_grp->g->lock); 821 return ret; 822 } 823 824 static int create_sysfs_eng_grps_info(struct device *dev, 825 struct otx_cpt_eng_grp_info *eng_grp) 826 { 827 int ret; 828 829 eng_grp->info_attr.show = eng_grp_info_show; 830 eng_grp->info_attr.store = NULL; 831 eng_grp->info_attr.attr.name = eng_grp->sysfs_info_name; 832 eng_grp->info_attr.attr.mode = 0440; 833 sysfs_attr_init(&eng_grp->info_attr.attr); 834 ret = device_create_file(dev, &eng_grp->info_attr); 835 if (ret) 836 return ret; 837 838 return 0; 839 } 840 841 static void ucode_unload(struct device *dev, struct otx_cpt_ucode *ucode) 842 { 843 if (ucode->va) { 844 dma_free_coherent(dev, ucode->size + OTX_CPT_UCODE_ALIGNMENT, 845 ucode->va, ucode->dma); 846 ucode->va = NULL; 847 ucode->align_va = NULL; 848 ucode->dma = 0; 849 ucode->align_dma = 0; 850 ucode->size = 0; 851 } 852 853 memset(&ucode->ver_str, 0, OTX_CPT_UCODE_VER_STR_SZ); 854 memset(&ucode->ver_num, 0, sizeof(struct otx_cpt_ucode_ver_num)); 855 set_ucode_filename(ucode, ""); 856 ucode->type = 0; 857 } 858 859 static int copy_ucode_to_dma_mem(struct device *dev, 860 struct otx_cpt_ucode *ucode, 861 const u8 *ucode_data) 862 { 863 u32 i; 864 865 /* Allocate DMAable space */ 866 ucode->va = dma_alloc_coherent(dev, ucode->size + 867 OTX_CPT_UCODE_ALIGNMENT, 868 &ucode->dma, GFP_KERNEL); 869 if (!ucode->va) { 870 dev_err(dev, "Unable to allocate space for microcode"); 871 return -ENOMEM; 872 } 873 ucode->align_va = PTR_ALIGN(ucode->va, OTX_CPT_UCODE_ALIGNMENT); 874 ucode->align_dma = PTR_ALIGN(ucode->dma, OTX_CPT_UCODE_ALIGNMENT); 875 876 memcpy((void *) ucode->align_va, (void *) ucode_data + 877 sizeof(struct otx_cpt_ucode_hdr), ucode->size); 878 879 /* Byte swap 64-bit */ 880 for (i = 0; i < (ucode->size / 8); i++) 881 ((u64 *)ucode->align_va)[i] = 882 cpu_to_be64(((u64 *)ucode->align_va)[i]); 883 /* Ucode needs 16-bit swap */ 884 for (i = 0; i < (ucode->size / 2); i++) 885 ((u16 *)ucode->align_va)[i] = 886 cpu_to_be16(((u16 *)ucode->align_va)[i]); 887 return 0; 888 } 889 890 static int ucode_load(struct device *dev, struct otx_cpt_ucode *ucode, 891 const char *ucode_filename) 892 { 893 struct otx_cpt_ucode_hdr *ucode_hdr; 894 const struct firmware *fw; 895 int ret; 896 897 set_ucode_filename(ucode, ucode_filename); 898 ret = request_firmware(&fw, ucode->filename, dev); 899 if (ret) 900 return ret; 901 902 ucode_hdr = (struct otx_cpt_ucode_hdr *) fw->data; 903 memcpy(ucode->ver_str, ucode_hdr->ver_str, OTX_CPT_UCODE_VER_STR_SZ); 904 ucode->ver_num = ucode_hdr->ver_num; 905 ucode->size = ntohl(ucode_hdr->code_length) * 2; 906 if (!ucode->size || (fw->size < round_up(ucode->size, 16) 907 + sizeof(struct otx_cpt_ucode_hdr) + OTX_CPT_UCODE_SIGN_LEN)) { 908 dev_err(dev, "Ucode %s invalid size", ucode_filename); 909 ret = -EINVAL; 910 goto release_fw; 911 } 912 913 ret = get_ucode_type(ucode_hdr, &ucode->type); 914 if (ret) { 915 dev_err(dev, "Microcode %s unknown type 0x%x", ucode->filename, 916 ucode->type); 917 goto release_fw; 918 } 919 920 ret = copy_ucode_to_dma_mem(dev, ucode, fw->data); 921 if (ret) 922 goto release_fw; 923 924 print_ucode_dbg_info(ucode); 925 release_fw: 926 release_firmware(fw); 927 return ret; 928 } 929 930 static int enable_eng_grp(struct otx_cpt_eng_grp_info *eng_grp, 931 void *obj) 932 { 933 int ret; 934 935 ret = cpt_set_ucode_base(eng_grp, obj); 936 if (ret) 937 return ret; 938 939 ret = cpt_attach_and_enable_cores(eng_grp, obj); 940 return ret; 941 } 942 943 static int disable_eng_grp(struct device *dev, 944 struct otx_cpt_eng_grp_info *eng_grp, 945 void *obj) 946 { 947 int i, ret; 948 949 ret = cpt_detach_and_disable_cores(eng_grp, obj); 950 if (ret) 951 return ret; 952 953 /* Unload ucode used by this engine group */ 954 ucode_unload(dev, &eng_grp->ucode[0]); 955 956 for (i = 0; i < OTX_CPT_MAX_ETYPES_PER_GRP; i++) { 957 if (!eng_grp->engs[i].type) 958 continue; 959 960 eng_grp->engs[i].ucode = &eng_grp->ucode[0]; 961 } 962 963 ret = cpt_set_ucode_base(eng_grp, obj); 964 965 return ret; 966 } 967 968 static void setup_eng_grp_mirroring(struct otx_cpt_eng_grp_info *dst_grp, 969 struct otx_cpt_eng_grp_info *src_grp) 970 { 971 /* Setup fields for engine group which is mirrored */ 972 src_grp->mirror.is_ena = false; 973 src_grp->mirror.idx = 0; 974 src_grp->mirror.ref_count++; 975 976 /* Setup fields for mirroring engine group */ 977 dst_grp->mirror.is_ena = true; 978 dst_grp->mirror.idx = src_grp->idx; 979 dst_grp->mirror.ref_count = 0; 980 } 981 982 static void remove_eng_grp_mirroring(struct otx_cpt_eng_grp_info *dst_grp) 983 { 984 struct otx_cpt_eng_grp_info *src_grp; 985 986 if (!dst_grp->mirror.is_ena) 987 return; 988 989 src_grp = &dst_grp->g->grp[dst_grp->mirror.idx]; 990 991 src_grp->mirror.ref_count--; 992 dst_grp->mirror.is_ena = false; 993 dst_grp->mirror.idx = 0; 994 dst_grp->mirror.ref_count = 0; 995 } 996 997 static void update_requested_engs(struct otx_cpt_eng_grp_info *mirrored_eng_grp, 998 struct otx_cpt_engines *engs, int engs_cnt) 999 { 1000 struct otx_cpt_engs_rsvd *mirrored_engs; 1001 int i; 1002 1003 for (i = 0; i < engs_cnt; i++) { 1004 mirrored_engs = find_engines_by_type(mirrored_eng_grp, 1005 engs[i].type); 1006 if (!mirrored_engs) 1007 continue; 1008 1009 /* 1010 * If mirrored group has this type of engines attached then 1011 * there are 3 scenarios possible: 1012 * 1) mirrored_engs.count == engs[i].count then all engines 1013 * from mirrored engine group will be shared with this engine 1014 * group 1015 * 2) mirrored_engs.count > engs[i].count then only a subset of 1016 * engines from mirrored engine group will be shared with this 1017 * engine group 1018 * 3) mirrored_engs.count < engs[i].count then all engines 1019 * from mirrored engine group will be shared with this group 1020 * and additional engines will be reserved for exclusively use 1021 * by this engine group 1022 */ 1023 engs[i].count -= mirrored_engs->count; 1024 } 1025 } 1026 1027 static struct otx_cpt_eng_grp_info *find_mirrored_eng_grp( 1028 struct otx_cpt_eng_grp_info *grp) 1029 { 1030 struct otx_cpt_eng_grps *eng_grps = grp->g; 1031 int i; 1032 1033 for (i = 0; i < OTX_CPT_MAX_ENGINE_GROUPS; i++) { 1034 if (!eng_grps->grp[i].is_enabled) 1035 continue; 1036 if (eng_grps->grp[i].ucode[0].type) 1037 continue; 1038 if (grp->idx == i) 1039 continue; 1040 if (!strncasecmp(eng_grps->grp[i].ucode[0].ver_str, 1041 grp->ucode[0].ver_str, 1042 OTX_CPT_UCODE_VER_STR_SZ)) 1043 return &eng_grps->grp[i]; 1044 } 1045 1046 return NULL; 1047 } 1048 1049 static struct otx_cpt_eng_grp_info *find_unused_eng_grp( 1050 struct otx_cpt_eng_grps *eng_grps) 1051 { 1052 int i; 1053 1054 for (i = 0; i < OTX_CPT_MAX_ENGINE_GROUPS; i++) { 1055 if (!eng_grps->grp[i].is_enabled) 1056 return &eng_grps->grp[i]; 1057 } 1058 return NULL; 1059 } 1060 1061 static int eng_grp_update_masks(struct device *dev, 1062 struct otx_cpt_eng_grp_info *eng_grp) 1063 { 1064 struct otx_cpt_engs_rsvd *engs, *mirrored_engs; 1065 struct otx_cpt_bitmap tmp_bmap = { {0} }; 1066 int i, j, cnt, max_cnt; 1067 int bit; 1068 1069 for (i = 0; i < OTX_CPT_MAX_ETYPES_PER_GRP; i++) { 1070 engs = &eng_grp->engs[i]; 1071 if (!engs->type) 1072 continue; 1073 if (engs->count <= 0) 1074 continue; 1075 1076 switch (engs->type) { 1077 case OTX_CPT_SE_TYPES: 1078 max_cnt = eng_grp->g->avail.max_se_cnt; 1079 break; 1080 1081 case OTX_CPT_AE_TYPES: 1082 max_cnt = eng_grp->g->avail.max_ae_cnt; 1083 break; 1084 1085 default: 1086 dev_err(dev, "Invalid engine type %d", engs->type); 1087 return -EINVAL; 1088 } 1089 1090 cnt = engs->count; 1091 WARN_ON(engs->offset + max_cnt > OTX_CPT_MAX_ENGINES); 1092 bitmap_zero(tmp_bmap.bits, eng_grp->g->engs_num); 1093 for (j = engs->offset; j < engs->offset + max_cnt; j++) { 1094 if (!eng_grp->g->eng_ref_cnt[j]) { 1095 bitmap_set(tmp_bmap.bits, j, 1); 1096 cnt--; 1097 if (!cnt) 1098 break; 1099 } 1100 } 1101 1102 if (cnt) 1103 return -ENOSPC; 1104 1105 bitmap_copy(engs->bmap, tmp_bmap.bits, eng_grp->g->engs_num); 1106 } 1107 1108 if (!eng_grp->mirror.is_ena) 1109 return 0; 1110 1111 for (i = 0; i < OTX_CPT_MAX_ETYPES_PER_GRP; i++) { 1112 engs = &eng_grp->engs[i]; 1113 if (!engs->type) 1114 continue; 1115 1116 mirrored_engs = find_engines_by_type( 1117 &eng_grp->g->grp[eng_grp->mirror.idx], 1118 engs->type); 1119 WARN_ON(!mirrored_engs && engs->count <= 0); 1120 if (!mirrored_engs) 1121 continue; 1122 1123 bitmap_copy(tmp_bmap.bits, mirrored_engs->bmap, 1124 eng_grp->g->engs_num); 1125 if (engs->count < 0) { 1126 bit = find_first_bit(mirrored_engs->bmap, 1127 eng_grp->g->engs_num); 1128 bitmap_clear(tmp_bmap.bits, bit, -engs->count); 1129 } 1130 bitmap_or(engs->bmap, engs->bmap, tmp_bmap.bits, 1131 eng_grp->g->engs_num); 1132 } 1133 return 0; 1134 } 1135 1136 static int delete_engine_group(struct device *dev, 1137 struct otx_cpt_eng_grp_info *eng_grp) 1138 { 1139 int i, ret; 1140 1141 if (!eng_grp->is_enabled) 1142 return -EINVAL; 1143 1144 if (eng_grp->mirror.ref_count) { 1145 dev_err(dev, "Can't delete engine_group%d as it is used by:", 1146 eng_grp->idx); 1147 for (i = 0; i < OTX_CPT_MAX_ENGINE_GROUPS; i++) { 1148 if (eng_grp->g->grp[i].mirror.is_ena && 1149 eng_grp->g->grp[i].mirror.idx == eng_grp->idx) 1150 dev_err(dev, "engine_group%d", i); 1151 } 1152 return -EINVAL; 1153 } 1154 1155 /* Removing engine group mirroring if enabled */ 1156 remove_eng_grp_mirroring(eng_grp); 1157 1158 /* Disable engine group */ 1159 ret = disable_eng_grp(dev, eng_grp, eng_grp->g->obj); 1160 if (ret) 1161 return ret; 1162 1163 /* Release all engines held by this engine group */ 1164 ret = release_engines(dev, eng_grp); 1165 if (ret) 1166 return ret; 1167 1168 device_remove_file(dev, &eng_grp->info_attr); 1169 eng_grp->is_enabled = false; 1170 1171 return 0; 1172 } 1173 1174 static int validate_1_ucode_scenario(struct device *dev, 1175 struct otx_cpt_eng_grp_info *eng_grp, 1176 struct otx_cpt_engines *engs, int engs_cnt) 1177 { 1178 int i; 1179 1180 /* Verify that ucode loaded supports requested engine types */ 1181 for (i = 0; i < engs_cnt; i++) { 1182 if (!otx_cpt_uc_supports_eng_type(&eng_grp->ucode[0], 1183 engs[i].type)) { 1184 dev_err(dev, 1185 "Microcode %s does not support %s engines", 1186 eng_grp->ucode[0].filename, 1187 get_eng_type_str(engs[i].type)); 1188 return -EINVAL; 1189 } 1190 } 1191 return 0; 1192 } 1193 1194 static void update_ucode_ptrs(struct otx_cpt_eng_grp_info *eng_grp) 1195 { 1196 struct otx_cpt_ucode *ucode; 1197 1198 if (eng_grp->mirror.is_ena) 1199 ucode = &eng_grp->g->grp[eng_grp->mirror.idx].ucode[0]; 1200 else 1201 ucode = &eng_grp->ucode[0]; 1202 WARN_ON(!eng_grp->engs[0].type); 1203 eng_grp->engs[0].ucode = ucode; 1204 } 1205 1206 static int create_engine_group(struct device *dev, 1207 struct otx_cpt_eng_grps *eng_grps, 1208 struct otx_cpt_engines *engs, int engs_cnt, 1209 void *ucode_data[], int ucodes_cnt, 1210 bool use_uc_from_tar_arch) 1211 { 1212 struct otx_cpt_eng_grp_info *mirrored_eng_grp; 1213 struct tar_ucode_info_t *tar_info; 1214 struct otx_cpt_eng_grp_info *eng_grp; 1215 int i, ret = 0; 1216 1217 if (ucodes_cnt > OTX_CPT_MAX_ETYPES_PER_GRP) 1218 return -EINVAL; 1219 1220 /* Validate if requested engine types are supported by this device */ 1221 for (i = 0; i < engs_cnt; i++) 1222 if (!dev_supports_eng_type(eng_grps, engs[i].type)) { 1223 dev_err(dev, "Device does not support %s engines", 1224 get_eng_type_str(engs[i].type)); 1225 return -EPERM; 1226 } 1227 1228 /* Find engine group which is not used */ 1229 eng_grp = find_unused_eng_grp(eng_grps); 1230 if (!eng_grp) { 1231 dev_err(dev, "Error all engine groups are being used"); 1232 return -ENOSPC; 1233 } 1234 1235 /* Load ucode */ 1236 for (i = 0; i < ucodes_cnt; i++) { 1237 if (use_uc_from_tar_arch) { 1238 tar_info = (struct tar_ucode_info_t *) ucode_data[i]; 1239 eng_grp->ucode[i] = tar_info->ucode; 1240 ret = copy_ucode_to_dma_mem(dev, &eng_grp->ucode[i], 1241 tar_info->ucode_ptr); 1242 } else 1243 ret = ucode_load(dev, &eng_grp->ucode[i], 1244 (char *) ucode_data[i]); 1245 if (ret) 1246 goto err_ucode_unload; 1247 } 1248 1249 /* Validate scenario where 1 ucode is used */ 1250 ret = validate_1_ucode_scenario(dev, eng_grp, engs, engs_cnt); 1251 if (ret) 1252 goto err_ucode_unload; 1253 1254 /* Check if this group mirrors another existing engine group */ 1255 mirrored_eng_grp = find_mirrored_eng_grp(eng_grp); 1256 if (mirrored_eng_grp) { 1257 /* Setup mirroring */ 1258 setup_eng_grp_mirroring(eng_grp, mirrored_eng_grp); 1259 1260 /* 1261 * Update count of requested engines because some 1262 * of them might be shared with mirrored group 1263 */ 1264 update_requested_engs(mirrored_eng_grp, engs, engs_cnt); 1265 } 1266 1267 /* Reserve engines */ 1268 ret = reserve_engines(dev, eng_grp, engs, engs_cnt); 1269 if (ret) 1270 goto err_ucode_unload; 1271 1272 /* Update ucode pointers used by engines */ 1273 update_ucode_ptrs(eng_grp); 1274 1275 /* Update engine masks used by this group */ 1276 ret = eng_grp_update_masks(dev, eng_grp); 1277 if (ret) 1278 goto err_release_engs; 1279 1280 /* Create sysfs entry for engine group info */ 1281 ret = create_sysfs_eng_grps_info(dev, eng_grp); 1282 if (ret) 1283 goto err_release_engs; 1284 1285 /* Enable engine group */ 1286 ret = enable_eng_grp(eng_grp, eng_grps->obj); 1287 if (ret) 1288 goto err_release_engs; 1289 1290 /* 1291 * If this engine group mirrors another engine group 1292 * then we need to unload ucode as we will use ucode 1293 * from mirrored engine group 1294 */ 1295 if (eng_grp->mirror.is_ena) 1296 ucode_unload(dev, &eng_grp->ucode[0]); 1297 1298 eng_grp->is_enabled = true; 1299 if (eng_grp->mirror.is_ena) 1300 dev_info(dev, 1301 "Engine_group%d: reuse microcode %s from group %d", 1302 eng_grp->idx, mirrored_eng_grp->ucode[0].ver_str, 1303 mirrored_eng_grp->idx); 1304 else 1305 dev_info(dev, "Engine_group%d: microcode loaded %s", 1306 eng_grp->idx, eng_grp->ucode[0].ver_str); 1307 1308 return 0; 1309 1310 err_release_engs: 1311 release_engines(dev, eng_grp); 1312 err_ucode_unload: 1313 ucode_unload(dev, &eng_grp->ucode[0]); 1314 return ret; 1315 } 1316 1317 static ssize_t ucode_load_store(struct device *dev, 1318 struct device_attribute *attr, 1319 const char *buf, size_t count) 1320 { 1321 struct otx_cpt_engines engs[OTX_CPT_MAX_ETYPES_PER_GRP] = { {0} }; 1322 char *ucode_filename[OTX_CPT_MAX_ETYPES_PER_GRP]; 1323 char tmp_buf[OTX_CPT_UCODE_NAME_LENGTH] = { 0 }; 1324 char *start, *val, *err_msg, *tmp; 1325 struct otx_cpt_eng_grps *eng_grps; 1326 int grp_idx = 0, ret = -EINVAL; 1327 bool has_se, has_ie, has_ae; 1328 int del_grp_idx = -1; 1329 int ucode_idx = 0; 1330 1331 if (strlen(buf) > OTX_CPT_UCODE_NAME_LENGTH) 1332 return -EINVAL; 1333 1334 eng_grps = container_of(attr, struct otx_cpt_eng_grps, ucode_load_attr); 1335 err_msg = "Invalid engine group format"; 1336 strlcpy(tmp_buf, buf, OTX_CPT_UCODE_NAME_LENGTH); 1337 start = tmp_buf; 1338 1339 has_se = has_ie = has_ae = false; 1340 1341 for (;;) { 1342 val = strsep(&start, ";"); 1343 if (!val) 1344 break; 1345 val = strim(val); 1346 if (!*val) 1347 continue; 1348 1349 if (!strncasecmp(val, "engine_group", 12)) { 1350 if (del_grp_idx != -1) 1351 goto err_print; 1352 tmp = strim(strsep(&val, ":")); 1353 if (!val) 1354 goto err_print; 1355 if (strlen(tmp) != 13) 1356 goto err_print; 1357 if (kstrtoint((tmp + 12), 10, &del_grp_idx)) 1358 goto err_print; 1359 val = strim(val); 1360 if (strncasecmp(val, "null", 4)) 1361 goto err_print; 1362 if (strlen(val) != 4) 1363 goto err_print; 1364 } else if (!strncasecmp(val, "se", 2) && strchr(val, ':')) { 1365 if (has_se || ucode_idx) 1366 goto err_print; 1367 tmp = strim(strsep(&val, ":")); 1368 if (!val) 1369 goto err_print; 1370 if (strlen(tmp) != 2) 1371 goto err_print; 1372 if (kstrtoint(strim(val), 10, &engs[grp_idx].count)) 1373 goto err_print; 1374 engs[grp_idx++].type = OTX_CPT_SE_TYPES; 1375 has_se = true; 1376 } else if (!strncasecmp(val, "ae", 2) && strchr(val, ':')) { 1377 if (has_ae || ucode_idx) 1378 goto err_print; 1379 tmp = strim(strsep(&val, ":")); 1380 if (!val) 1381 goto err_print; 1382 if (strlen(tmp) != 2) 1383 goto err_print; 1384 if (kstrtoint(strim(val), 10, &engs[grp_idx].count)) 1385 goto err_print; 1386 engs[grp_idx++].type = OTX_CPT_AE_TYPES; 1387 has_ae = true; 1388 } else { 1389 if (ucode_idx > 1) 1390 goto err_print; 1391 if (!strlen(val)) 1392 goto err_print; 1393 if (strnstr(val, " ", strlen(val))) 1394 goto err_print; 1395 ucode_filename[ucode_idx++] = val; 1396 } 1397 } 1398 1399 /* Validate input parameters */ 1400 if (del_grp_idx == -1) { 1401 if (!(grp_idx && ucode_idx)) 1402 goto err_print; 1403 1404 if (ucode_idx > 1 && grp_idx < 2) 1405 goto err_print; 1406 1407 if (grp_idx > OTX_CPT_MAX_ETYPES_PER_GRP) { 1408 err_msg = "Error max 2 engine types can be attached"; 1409 goto err_print; 1410 } 1411 1412 } else { 1413 if (del_grp_idx < 0 || 1414 del_grp_idx >= OTX_CPT_MAX_ENGINE_GROUPS) { 1415 dev_err(dev, "Invalid engine group index %d", 1416 del_grp_idx); 1417 ret = -EINVAL; 1418 return ret; 1419 } 1420 1421 if (!eng_grps->grp[del_grp_idx].is_enabled) { 1422 dev_err(dev, "Error engine_group%d is not configured", 1423 del_grp_idx); 1424 ret = -EINVAL; 1425 return ret; 1426 } 1427 1428 if (grp_idx || ucode_idx) 1429 goto err_print; 1430 } 1431 1432 mutex_lock(&eng_grps->lock); 1433 1434 if (eng_grps->is_rdonly) { 1435 dev_err(dev, "Disable VFs before modifying engine groups\n"); 1436 ret = -EACCES; 1437 goto err_unlock; 1438 } 1439 1440 if (del_grp_idx == -1) 1441 /* create engine group */ 1442 ret = create_engine_group(dev, eng_grps, engs, grp_idx, 1443 (void **) ucode_filename, 1444 ucode_idx, false); 1445 else 1446 /* delete engine group */ 1447 ret = delete_engine_group(dev, &eng_grps->grp[del_grp_idx]); 1448 if (ret) 1449 goto err_unlock; 1450 1451 print_dbg_info(dev, eng_grps); 1452 err_unlock: 1453 mutex_unlock(&eng_grps->lock); 1454 return ret ? ret : count; 1455 err_print: 1456 dev_err(dev, "%s\n", err_msg); 1457 1458 return ret; 1459 } 1460 1461 int otx_cpt_try_create_default_eng_grps(struct pci_dev *pdev, 1462 struct otx_cpt_eng_grps *eng_grps, 1463 int pf_type) 1464 { 1465 struct tar_ucode_info_t *tar_info[OTX_CPT_MAX_ETYPES_PER_GRP] = { 0 }; 1466 struct otx_cpt_engines engs[OTX_CPT_MAX_ETYPES_PER_GRP] = { {0} }; 1467 struct tar_arch_info_t *tar_arch = NULL; 1468 char *tar_filename; 1469 int i, ret = 0; 1470 1471 mutex_lock(&eng_grps->lock); 1472 1473 /* 1474 * We don't create engine group for kernel crypto if attempt to create 1475 * it was already made (when user enabled VFs for the first time) 1476 */ 1477 if (eng_grps->is_first_try) 1478 goto unlock_mutex; 1479 eng_grps->is_first_try = true; 1480 1481 /* We create group for kcrypto only if no groups are configured */ 1482 for (i = 0; i < OTX_CPT_MAX_ENGINE_GROUPS; i++) 1483 if (eng_grps->grp[i].is_enabled) 1484 goto unlock_mutex; 1485 1486 switch (pf_type) { 1487 case OTX_CPT_AE: 1488 case OTX_CPT_SE: 1489 tar_filename = OTX_CPT_UCODE_TAR_FILE_NAME; 1490 break; 1491 1492 default: 1493 dev_err(&pdev->dev, "Unknown PF type %d\n", pf_type); 1494 ret = -EINVAL; 1495 goto unlock_mutex; 1496 } 1497 1498 tar_arch = load_tar_archive(&pdev->dev, tar_filename); 1499 if (!tar_arch) 1500 goto unlock_mutex; 1501 1502 /* 1503 * If device supports SE engines and there is SE microcode in tar 1504 * archive try to create engine group with SE engines for kernel 1505 * crypto functionality (symmetric crypto) 1506 */ 1507 tar_info[0] = get_uc_from_tar_archive(tar_arch, OTX_CPT_SE_TYPES); 1508 if (tar_info[0] && 1509 dev_supports_eng_type(eng_grps, OTX_CPT_SE_TYPES)) { 1510 1511 engs[0].type = OTX_CPT_SE_TYPES; 1512 engs[0].count = eng_grps->avail.max_se_cnt; 1513 1514 ret = create_engine_group(&pdev->dev, eng_grps, engs, 1, 1515 (void **) tar_info, 1, true); 1516 if (ret) 1517 goto release_tar_arch; 1518 } 1519 /* 1520 * If device supports AE engines and there is AE microcode in tar 1521 * archive try to create engine group with AE engines for asymmetric 1522 * crypto functionality. 1523 */ 1524 tar_info[0] = get_uc_from_tar_archive(tar_arch, OTX_CPT_AE_TYPES); 1525 if (tar_info[0] && 1526 dev_supports_eng_type(eng_grps, OTX_CPT_AE_TYPES)) { 1527 1528 engs[0].type = OTX_CPT_AE_TYPES; 1529 engs[0].count = eng_grps->avail.max_ae_cnt; 1530 1531 ret = create_engine_group(&pdev->dev, eng_grps, engs, 1, 1532 (void **) tar_info, 1, true); 1533 if (ret) 1534 goto release_tar_arch; 1535 } 1536 1537 print_dbg_info(&pdev->dev, eng_grps); 1538 release_tar_arch: 1539 release_tar_archive(tar_arch); 1540 unlock_mutex: 1541 mutex_unlock(&eng_grps->lock); 1542 return ret; 1543 } 1544 1545 void otx_cpt_set_eng_grps_is_rdonly(struct otx_cpt_eng_grps *eng_grps, 1546 bool is_rdonly) 1547 { 1548 mutex_lock(&eng_grps->lock); 1549 1550 eng_grps->is_rdonly = is_rdonly; 1551 1552 mutex_unlock(&eng_grps->lock); 1553 } 1554 1555 void otx_cpt_disable_all_cores(struct otx_cpt_device *cpt) 1556 { 1557 int grp, timeout = 100; 1558 u64 reg; 1559 1560 /* Disengage the cores from groups */ 1561 for (grp = 0; grp < OTX_CPT_MAX_ENGINE_GROUPS; grp++) { 1562 writeq(0, cpt->reg_base + OTX_CPT_PF_GX_EN(grp)); 1563 udelay(CSR_DELAY); 1564 } 1565 1566 reg = readq(cpt->reg_base + OTX_CPT_PF_EXEC_BUSY); 1567 while (reg) { 1568 udelay(CSR_DELAY); 1569 reg = readq(cpt->reg_base + OTX_CPT_PF_EXEC_BUSY); 1570 if (timeout--) { 1571 dev_warn(&cpt->pdev->dev, "Cores still busy"); 1572 break; 1573 } 1574 } 1575 1576 /* Disable the cores */ 1577 writeq(0, cpt->reg_base + OTX_CPT_PF_EXE_CTL); 1578 } 1579 1580 void otx_cpt_cleanup_eng_grps(struct pci_dev *pdev, 1581 struct otx_cpt_eng_grps *eng_grps) 1582 { 1583 struct otx_cpt_eng_grp_info *grp; 1584 int i, j; 1585 1586 mutex_lock(&eng_grps->lock); 1587 if (eng_grps->is_ucode_load_created) { 1588 device_remove_file(&pdev->dev, 1589 &eng_grps->ucode_load_attr); 1590 eng_grps->is_ucode_load_created = false; 1591 } 1592 1593 /* First delete all mirroring engine groups */ 1594 for (i = 0; i < OTX_CPT_MAX_ENGINE_GROUPS; i++) 1595 if (eng_grps->grp[i].mirror.is_ena) 1596 delete_engine_group(&pdev->dev, &eng_grps->grp[i]); 1597 1598 /* Delete remaining engine groups */ 1599 for (i = 0; i < OTX_CPT_MAX_ENGINE_GROUPS; i++) 1600 delete_engine_group(&pdev->dev, &eng_grps->grp[i]); 1601 1602 /* Release memory */ 1603 for (i = 0; i < OTX_CPT_MAX_ENGINE_GROUPS; i++) { 1604 grp = &eng_grps->grp[i]; 1605 for (j = 0; j < OTX_CPT_MAX_ETYPES_PER_GRP; j++) { 1606 kfree(grp->engs[j].bmap); 1607 grp->engs[j].bmap = NULL; 1608 } 1609 } 1610 1611 mutex_unlock(&eng_grps->lock); 1612 } 1613 1614 int otx_cpt_init_eng_grps(struct pci_dev *pdev, 1615 struct otx_cpt_eng_grps *eng_grps, int pf_type) 1616 { 1617 struct otx_cpt_eng_grp_info *grp; 1618 int i, j, ret = 0; 1619 1620 mutex_init(&eng_grps->lock); 1621 eng_grps->obj = pci_get_drvdata(pdev); 1622 eng_grps->avail.se_cnt = eng_grps->avail.max_se_cnt; 1623 eng_grps->avail.ae_cnt = eng_grps->avail.max_ae_cnt; 1624 1625 eng_grps->engs_num = eng_grps->avail.max_se_cnt + 1626 eng_grps->avail.max_ae_cnt; 1627 if (eng_grps->engs_num > OTX_CPT_MAX_ENGINES) { 1628 dev_err(&pdev->dev, 1629 "Number of engines %d > than max supported %d", 1630 eng_grps->engs_num, OTX_CPT_MAX_ENGINES); 1631 ret = -EINVAL; 1632 goto err; 1633 } 1634 1635 for (i = 0; i < OTX_CPT_MAX_ENGINE_GROUPS; i++) { 1636 grp = &eng_grps->grp[i]; 1637 grp->g = eng_grps; 1638 grp->idx = i; 1639 1640 snprintf(grp->sysfs_info_name, OTX_CPT_UCODE_NAME_LENGTH, 1641 "engine_group%d", i); 1642 for (j = 0; j < OTX_CPT_MAX_ETYPES_PER_GRP; j++) { 1643 grp->engs[j].bmap = 1644 kcalloc(BITS_TO_LONGS(eng_grps->engs_num), 1645 sizeof(long), GFP_KERNEL); 1646 if (!grp->engs[j].bmap) { 1647 ret = -ENOMEM; 1648 goto err; 1649 } 1650 } 1651 } 1652 1653 switch (pf_type) { 1654 case OTX_CPT_SE: 1655 /* OcteonTX 83XX SE CPT PF has only SE engines attached */ 1656 eng_grps->eng_types_supported = 1 << OTX_CPT_SE_TYPES; 1657 break; 1658 1659 case OTX_CPT_AE: 1660 /* OcteonTX 83XX AE CPT PF has only AE engines attached */ 1661 eng_grps->eng_types_supported = 1 << OTX_CPT_AE_TYPES; 1662 break; 1663 1664 default: 1665 dev_err(&pdev->dev, "Unknown PF type %d\n", pf_type); 1666 ret = -EINVAL; 1667 goto err; 1668 } 1669 1670 eng_grps->ucode_load_attr.show = NULL; 1671 eng_grps->ucode_load_attr.store = ucode_load_store; 1672 eng_grps->ucode_load_attr.attr.name = "ucode_load"; 1673 eng_grps->ucode_load_attr.attr.mode = 0220; 1674 sysfs_attr_init(&eng_grps->ucode_load_attr.attr); 1675 ret = device_create_file(&pdev->dev, 1676 &eng_grps->ucode_load_attr); 1677 if (ret) 1678 goto err; 1679 eng_grps->is_ucode_load_created = true; 1680 1681 print_dbg_info(&pdev->dev, eng_grps); 1682 return ret; 1683 err: 1684 otx_cpt_cleanup_eng_grps(pdev, eng_grps); 1685 return ret; 1686 } 1687