1655ff1a1SSrujanaChalla /* SPDX-License-Identifier: GPL-2.0 */
2655ff1a1SSrujanaChalla #ifndef __MARVELL_CESA_H__
3655ff1a1SSrujanaChalla #define __MARVELL_CESA_H__
4655ff1a1SSrujanaChalla
5655ff1a1SSrujanaChalla #include <crypto/internal/hash.h>
6655ff1a1SSrujanaChalla #include <crypto/internal/skcipher.h>
7655ff1a1SSrujanaChalla
80c3dc787SHerbert Xu #include <linux/dma-direction.h>
9655ff1a1SSrujanaChalla #include <linux/dmapool.h>
10655ff1a1SSrujanaChalla
11655ff1a1SSrujanaChalla #define CESA_ENGINE_OFF(i) (((i) * 0x2000))
12655ff1a1SSrujanaChalla
13655ff1a1SSrujanaChalla #define CESA_TDMA_BYTE_CNT 0x800
14655ff1a1SSrujanaChalla #define CESA_TDMA_SRC_ADDR 0x810
15655ff1a1SSrujanaChalla #define CESA_TDMA_DST_ADDR 0x820
16655ff1a1SSrujanaChalla #define CESA_TDMA_NEXT_ADDR 0x830
17655ff1a1SSrujanaChalla
18655ff1a1SSrujanaChalla #define CESA_TDMA_CONTROL 0x840
19655ff1a1SSrujanaChalla #define CESA_TDMA_DST_BURST GENMASK(2, 0)
20655ff1a1SSrujanaChalla #define CESA_TDMA_DST_BURST_32B 3
21655ff1a1SSrujanaChalla #define CESA_TDMA_DST_BURST_128B 4
22655ff1a1SSrujanaChalla #define CESA_TDMA_OUT_RD_EN BIT(4)
23655ff1a1SSrujanaChalla #define CESA_TDMA_SRC_BURST GENMASK(8, 6)
24655ff1a1SSrujanaChalla #define CESA_TDMA_SRC_BURST_32B (3 << 6)
25655ff1a1SSrujanaChalla #define CESA_TDMA_SRC_BURST_128B (4 << 6)
26655ff1a1SSrujanaChalla #define CESA_TDMA_CHAIN BIT(9)
27655ff1a1SSrujanaChalla #define CESA_TDMA_BYTE_SWAP BIT(11)
28655ff1a1SSrujanaChalla #define CESA_TDMA_NO_BYTE_SWAP BIT(11)
29655ff1a1SSrujanaChalla #define CESA_TDMA_EN BIT(12)
30655ff1a1SSrujanaChalla #define CESA_TDMA_FETCH_ND BIT(13)
31655ff1a1SSrujanaChalla #define CESA_TDMA_ACT BIT(14)
32655ff1a1SSrujanaChalla
33655ff1a1SSrujanaChalla #define CESA_TDMA_CUR 0x870
34655ff1a1SSrujanaChalla #define CESA_TDMA_ERROR_CAUSE 0x8c8
35655ff1a1SSrujanaChalla #define CESA_TDMA_ERROR_MSK 0x8cc
36655ff1a1SSrujanaChalla
37655ff1a1SSrujanaChalla #define CESA_TDMA_WINDOW_BASE(x) (((x) * 0x8) + 0xa00)
38655ff1a1SSrujanaChalla #define CESA_TDMA_WINDOW_CTRL(x) (((x) * 0x8) + 0xa04)
39655ff1a1SSrujanaChalla
40655ff1a1SSrujanaChalla #define CESA_IVDIG(x) (0xdd00 + ((x) * 4) + \
41655ff1a1SSrujanaChalla (((x) < 5) ? 0 : 0x14))
42655ff1a1SSrujanaChalla
43655ff1a1SSrujanaChalla #define CESA_SA_CMD 0xde00
44655ff1a1SSrujanaChalla #define CESA_SA_CMD_EN_CESA_SA_ACCL0 BIT(0)
45655ff1a1SSrujanaChalla #define CESA_SA_CMD_EN_CESA_SA_ACCL1 BIT(1)
46655ff1a1SSrujanaChalla #define CESA_SA_CMD_DISABLE_SEC BIT(2)
47655ff1a1SSrujanaChalla
48655ff1a1SSrujanaChalla #define CESA_SA_DESC_P0 0xde04
49655ff1a1SSrujanaChalla
50655ff1a1SSrujanaChalla #define CESA_SA_DESC_P1 0xde14
51655ff1a1SSrujanaChalla
52655ff1a1SSrujanaChalla #define CESA_SA_CFG 0xde08
53655ff1a1SSrujanaChalla #define CESA_SA_CFG_STOP_DIG_ERR GENMASK(1, 0)
54655ff1a1SSrujanaChalla #define CESA_SA_CFG_DIG_ERR_CONT 0
55655ff1a1SSrujanaChalla #define CESA_SA_CFG_DIG_ERR_SKIP 1
56655ff1a1SSrujanaChalla #define CESA_SA_CFG_DIG_ERR_STOP 3
57655ff1a1SSrujanaChalla #define CESA_SA_CFG_CH0_W_IDMA BIT(7)
58655ff1a1SSrujanaChalla #define CESA_SA_CFG_CH1_W_IDMA BIT(8)
59655ff1a1SSrujanaChalla #define CESA_SA_CFG_ACT_CH0_IDMA BIT(9)
60655ff1a1SSrujanaChalla #define CESA_SA_CFG_ACT_CH1_IDMA BIT(10)
61655ff1a1SSrujanaChalla #define CESA_SA_CFG_MULTI_PKT BIT(11)
62655ff1a1SSrujanaChalla #define CESA_SA_CFG_PARA_DIS BIT(13)
63655ff1a1SSrujanaChalla
64655ff1a1SSrujanaChalla #define CESA_SA_ACCEL_STATUS 0xde0c
65655ff1a1SSrujanaChalla #define CESA_SA_ST_ACT_0 BIT(0)
66655ff1a1SSrujanaChalla #define CESA_SA_ST_ACT_1 BIT(1)
67655ff1a1SSrujanaChalla
68655ff1a1SSrujanaChalla /*
69*3f52c9aeSTom Rix * CESA_SA_FPGA_INT_STATUS looks like an FPGA leftover and is documented only
70655ff1a1SSrujanaChalla * in Errata 4.12. It looks like that it was part of an IRQ-controller in FPGA
71655ff1a1SSrujanaChalla * and someone forgot to remove it while switching to the core and moving to
72655ff1a1SSrujanaChalla * CESA_SA_INT_STATUS.
73655ff1a1SSrujanaChalla */
74655ff1a1SSrujanaChalla #define CESA_SA_FPGA_INT_STATUS 0xdd68
75655ff1a1SSrujanaChalla #define CESA_SA_INT_STATUS 0xde20
76655ff1a1SSrujanaChalla #define CESA_SA_INT_AUTH_DONE BIT(0)
77655ff1a1SSrujanaChalla #define CESA_SA_INT_DES_E_DONE BIT(1)
78655ff1a1SSrujanaChalla #define CESA_SA_INT_AES_E_DONE BIT(2)
79655ff1a1SSrujanaChalla #define CESA_SA_INT_AES_D_DONE BIT(3)
80655ff1a1SSrujanaChalla #define CESA_SA_INT_ENC_DONE BIT(4)
81655ff1a1SSrujanaChalla #define CESA_SA_INT_ACCEL0_DONE BIT(5)
82655ff1a1SSrujanaChalla #define CESA_SA_INT_ACCEL1_DONE BIT(6)
83655ff1a1SSrujanaChalla #define CESA_SA_INT_ACC0_IDMA_DONE BIT(7)
84655ff1a1SSrujanaChalla #define CESA_SA_INT_ACC1_IDMA_DONE BIT(8)
85655ff1a1SSrujanaChalla #define CESA_SA_INT_IDMA_DONE BIT(9)
86655ff1a1SSrujanaChalla #define CESA_SA_INT_IDMA_OWN_ERR BIT(10)
87655ff1a1SSrujanaChalla
88655ff1a1SSrujanaChalla #define CESA_SA_INT_MSK 0xde24
89655ff1a1SSrujanaChalla
90655ff1a1SSrujanaChalla #define CESA_SA_DESC_CFG_OP_MAC_ONLY 0
91655ff1a1SSrujanaChalla #define CESA_SA_DESC_CFG_OP_CRYPT_ONLY 1
92655ff1a1SSrujanaChalla #define CESA_SA_DESC_CFG_OP_MAC_CRYPT 2
93655ff1a1SSrujanaChalla #define CESA_SA_DESC_CFG_OP_CRYPT_MAC 3
94655ff1a1SSrujanaChalla #define CESA_SA_DESC_CFG_OP_MSK GENMASK(1, 0)
95655ff1a1SSrujanaChalla #define CESA_SA_DESC_CFG_MACM_SHA256 (1 << 4)
96655ff1a1SSrujanaChalla #define CESA_SA_DESC_CFG_MACM_HMAC_SHA256 (3 << 4)
97655ff1a1SSrujanaChalla #define CESA_SA_DESC_CFG_MACM_MD5 (4 << 4)
98655ff1a1SSrujanaChalla #define CESA_SA_DESC_CFG_MACM_SHA1 (5 << 4)
99655ff1a1SSrujanaChalla #define CESA_SA_DESC_CFG_MACM_HMAC_MD5 (6 << 4)
100655ff1a1SSrujanaChalla #define CESA_SA_DESC_CFG_MACM_HMAC_SHA1 (7 << 4)
101655ff1a1SSrujanaChalla #define CESA_SA_DESC_CFG_MACM_MSK GENMASK(6, 4)
102655ff1a1SSrujanaChalla #define CESA_SA_DESC_CFG_CRYPTM_DES (1 << 8)
103655ff1a1SSrujanaChalla #define CESA_SA_DESC_CFG_CRYPTM_3DES (2 << 8)
104655ff1a1SSrujanaChalla #define CESA_SA_DESC_CFG_CRYPTM_AES (3 << 8)
105655ff1a1SSrujanaChalla #define CESA_SA_DESC_CFG_CRYPTM_MSK GENMASK(9, 8)
106655ff1a1SSrujanaChalla #define CESA_SA_DESC_CFG_DIR_ENC (0 << 12)
107655ff1a1SSrujanaChalla #define CESA_SA_DESC_CFG_DIR_DEC (1 << 12)
108655ff1a1SSrujanaChalla #define CESA_SA_DESC_CFG_CRYPTCM_ECB (0 << 16)
109655ff1a1SSrujanaChalla #define CESA_SA_DESC_CFG_CRYPTCM_CBC (1 << 16)
110655ff1a1SSrujanaChalla #define CESA_SA_DESC_CFG_CRYPTCM_MSK BIT(16)
111655ff1a1SSrujanaChalla #define CESA_SA_DESC_CFG_3DES_EEE (0 << 20)
112655ff1a1SSrujanaChalla #define CESA_SA_DESC_CFG_3DES_EDE (1 << 20)
113655ff1a1SSrujanaChalla #define CESA_SA_DESC_CFG_AES_LEN_128 (0 << 24)
114655ff1a1SSrujanaChalla #define CESA_SA_DESC_CFG_AES_LEN_192 (1 << 24)
115655ff1a1SSrujanaChalla #define CESA_SA_DESC_CFG_AES_LEN_256 (2 << 24)
116655ff1a1SSrujanaChalla #define CESA_SA_DESC_CFG_AES_LEN_MSK GENMASK(25, 24)
117655ff1a1SSrujanaChalla #define CESA_SA_DESC_CFG_NOT_FRAG (0 << 30)
118655ff1a1SSrujanaChalla #define CESA_SA_DESC_CFG_FIRST_FRAG (1 << 30)
119655ff1a1SSrujanaChalla #define CESA_SA_DESC_CFG_LAST_FRAG (2 << 30)
120655ff1a1SSrujanaChalla #define CESA_SA_DESC_CFG_MID_FRAG (3 << 30)
121655ff1a1SSrujanaChalla #define CESA_SA_DESC_CFG_FRAG_MSK GENMASK(31, 30)
122655ff1a1SSrujanaChalla
123655ff1a1SSrujanaChalla /*
124655ff1a1SSrujanaChalla * /-----------\ 0
125655ff1a1SSrujanaChalla * | ACCEL CFG | 4 * 8
126655ff1a1SSrujanaChalla * |-----------| 0x20
127655ff1a1SSrujanaChalla * | CRYPT KEY | 8 * 4
128655ff1a1SSrujanaChalla * |-----------| 0x40
129655ff1a1SSrujanaChalla * | IV IN | 4 * 4
130655ff1a1SSrujanaChalla * |-----------| 0x40 (inplace)
131655ff1a1SSrujanaChalla * | IV BUF | 4 * 4
132655ff1a1SSrujanaChalla * |-----------| 0x80
133655ff1a1SSrujanaChalla * | DATA IN | 16 * x (max ->max_req_size)
134655ff1a1SSrujanaChalla * |-----------| 0x80 (inplace operation)
135655ff1a1SSrujanaChalla * | DATA OUT | 16 * x (max ->max_req_size)
136655ff1a1SSrujanaChalla * \-----------/ SRAM size
137655ff1a1SSrujanaChalla */
138655ff1a1SSrujanaChalla
139655ff1a1SSrujanaChalla /*
140655ff1a1SSrujanaChalla * Hashing memory map:
141655ff1a1SSrujanaChalla * /-----------\ 0
142655ff1a1SSrujanaChalla * | ACCEL CFG | 4 * 8
143655ff1a1SSrujanaChalla * |-----------| 0x20
144655ff1a1SSrujanaChalla * | Inner IV | 8 * 4
145655ff1a1SSrujanaChalla * |-----------| 0x40
146655ff1a1SSrujanaChalla * | Outer IV | 8 * 4
147655ff1a1SSrujanaChalla * |-----------| 0x60
148655ff1a1SSrujanaChalla * | Output BUF| 8 * 4
149655ff1a1SSrujanaChalla * |-----------| 0x80
150655ff1a1SSrujanaChalla * | DATA IN | 64 * x (max ->max_req_size)
151655ff1a1SSrujanaChalla * \-----------/ SRAM size
152655ff1a1SSrujanaChalla */
153655ff1a1SSrujanaChalla
154655ff1a1SSrujanaChalla #define CESA_SA_CFG_SRAM_OFFSET 0x00
155655ff1a1SSrujanaChalla #define CESA_SA_DATA_SRAM_OFFSET 0x80
156655ff1a1SSrujanaChalla
157655ff1a1SSrujanaChalla #define CESA_SA_CRYPT_KEY_SRAM_OFFSET 0x20
158655ff1a1SSrujanaChalla #define CESA_SA_CRYPT_IV_SRAM_OFFSET 0x40
159655ff1a1SSrujanaChalla
160655ff1a1SSrujanaChalla #define CESA_SA_MAC_IIV_SRAM_OFFSET 0x20
161655ff1a1SSrujanaChalla #define CESA_SA_MAC_OIV_SRAM_OFFSET 0x40
162655ff1a1SSrujanaChalla #define CESA_SA_MAC_DIG_SRAM_OFFSET 0x60
163655ff1a1SSrujanaChalla
164655ff1a1SSrujanaChalla #define CESA_SA_DESC_CRYPT_DATA(offset) \
165655ff1a1SSrujanaChalla cpu_to_le32((CESA_SA_DATA_SRAM_OFFSET + (offset)) | \
166655ff1a1SSrujanaChalla ((CESA_SA_DATA_SRAM_OFFSET + (offset)) << 16))
167655ff1a1SSrujanaChalla
168655ff1a1SSrujanaChalla #define CESA_SA_DESC_CRYPT_IV(offset) \
169655ff1a1SSrujanaChalla cpu_to_le32((CESA_SA_CRYPT_IV_SRAM_OFFSET + (offset)) | \
170655ff1a1SSrujanaChalla ((CESA_SA_CRYPT_IV_SRAM_OFFSET + (offset)) << 16))
171655ff1a1SSrujanaChalla
172655ff1a1SSrujanaChalla #define CESA_SA_DESC_CRYPT_KEY(offset) \
173655ff1a1SSrujanaChalla cpu_to_le32(CESA_SA_CRYPT_KEY_SRAM_OFFSET + (offset))
174655ff1a1SSrujanaChalla
175655ff1a1SSrujanaChalla #define CESA_SA_DESC_MAC_DATA(offset) \
176655ff1a1SSrujanaChalla cpu_to_le32(CESA_SA_DATA_SRAM_OFFSET + (offset))
177655ff1a1SSrujanaChalla #define CESA_SA_DESC_MAC_DATA_MSK cpu_to_le32(GENMASK(15, 0))
178655ff1a1SSrujanaChalla
179655ff1a1SSrujanaChalla #define CESA_SA_DESC_MAC_TOTAL_LEN(total_len) cpu_to_le32((total_len) << 16)
180655ff1a1SSrujanaChalla #define CESA_SA_DESC_MAC_TOTAL_LEN_MSK cpu_to_le32(GENMASK(31, 16))
181655ff1a1SSrujanaChalla
182655ff1a1SSrujanaChalla #define CESA_SA_DESC_MAC_SRC_TOTAL_LEN_MAX 0xffff
183655ff1a1SSrujanaChalla
184655ff1a1SSrujanaChalla #define CESA_SA_DESC_MAC_DIGEST(offset) \
185655ff1a1SSrujanaChalla cpu_to_le32(CESA_SA_MAC_DIG_SRAM_OFFSET + (offset))
186655ff1a1SSrujanaChalla #define CESA_SA_DESC_MAC_DIGEST_MSK cpu_to_le32(GENMASK(15, 0))
187655ff1a1SSrujanaChalla
188655ff1a1SSrujanaChalla #define CESA_SA_DESC_MAC_FRAG_LEN(frag_len) cpu_to_le32((frag_len) << 16)
189655ff1a1SSrujanaChalla #define CESA_SA_DESC_MAC_FRAG_LEN_MSK cpu_to_le32(GENMASK(31, 16))
190655ff1a1SSrujanaChalla
191655ff1a1SSrujanaChalla #define CESA_SA_DESC_MAC_IV(offset) \
192655ff1a1SSrujanaChalla cpu_to_le32((CESA_SA_MAC_IIV_SRAM_OFFSET + (offset)) | \
193655ff1a1SSrujanaChalla ((CESA_SA_MAC_OIV_SRAM_OFFSET + (offset)) << 16))
194655ff1a1SSrujanaChalla
195655ff1a1SSrujanaChalla #define CESA_SA_SRAM_SIZE 2048
196655ff1a1SSrujanaChalla #define CESA_SA_SRAM_PAYLOAD_SIZE (cesa_dev->sram_size - \
197655ff1a1SSrujanaChalla CESA_SA_DATA_SRAM_OFFSET)
198655ff1a1SSrujanaChalla
199655ff1a1SSrujanaChalla #define CESA_SA_DEFAULT_SRAM_SIZE 2048
200655ff1a1SSrujanaChalla #define CESA_SA_MIN_SRAM_SIZE 1024
201655ff1a1SSrujanaChalla
202655ff1a1SSrujanaChalla #define CESA_SA_SRAM_MSK (2048 - 1)
203655ff1a1SSrujanaChalla
204655ff1a1SSrujanaChalla #define CESA_MAX_HASH_BLOCK_SIZE 64
205655ff1a1SSrujanaChalla #define CESA_HASH_BLOCK_SIZE_MSK (CESA_MAX_HASH_BLOCK_SIZE - 1)
206655ff1a1SSrujanaChalla
207655ff1a1SSrujanaChalla /**
208655ff1a1SSrujanaChalla * struct mv_cesa_sec_accel_desc - security accelerator descriptor
209655ff1a1SSrujanaChalla * @config: engine config
210655ff1a1SSrujanaChalla * @enc_p: input and output data pointers for a cipher operation
211655ff1a1SSrujanaChalla * @enc_len: cipher operation length
212655ff1a1SSrujanaChalla * @enc_key_p: cipher key pointer
213655ff1a1SSrujanaChalla * @enc_iv: cipher IV pointers
214655ff1a1SSrujanaChalla * @mac_src_p: input pointer and total hash length
215655ff1a1SSrujanaChalla * @mac_digest: digest pointer and hash operation length
216655ff1a1SSrujanaChalla * @mac_iv: hmac IV pointers
217655ff1a1SSrujanaChalla *
218655ff1a1SSrujanaChalla * Structure passed to the CESA engine to describe the crypto operation
219655ff1a1SSrujanaChalla * to be executed.
220655ff1a1SSrujanaChalla */
221655ff1a1SSrujanaChalla struct mv_cesa_sec_accel_desc {
222655ff1a1SSrujanaChalla __le32 config;
223655ff1a1SSrujanaChalla __le32 enc_p;
224655ff1a1SSrujanaChalla __le32 enc_len;
225655ff1a1SSrujanaChalla __le32 enc_key_p;
226655ff1a1SSrujanaChalla __le32 enc_iv;
227655ff1a1SSrujanaChalla __le32 mac_src_p;
228655ff1a1SSrujanaChalla __le32 mac_digest;
229655ff1a1SSrujanaChalla __le32 mac_iv;
230655ff1a1SSrujanaChalla };
231655ff1a1SSrujanaChalla
232655ff1a1SSrujanaChalla /**
233655ff1a1SSrujanaChalla * struct mv_cesa_skcipher_op_ctx - cipher operation context
234655ff1a1SSrujanaChalla * @key: cipher key
235655ff1a1SSrujanaChalla * @iv: cipher IV
236655ff1a1SSrujanaChalla *
237655ff1a1SSrujanaChalla * Context associated to a cipher operation.
238655ff1a1SSrujanaChalla */
239655ff1a1SSrujanaChalla struct mv_cesa_skcipher_op_ctx {
240e62291c1SHerbert Xu __le32 key[8];
241655ff1a1SSrujanaChalla u32 iv[4];
242655ff1a1SSrujanaChalla };
243655ff1a1SSrujanaChalla
244655ff1a1SSrujanaChalla /**
245655ff1a1SSrujanaChalla * struct mv_cesa_hash_op_ctx - hash or hmac operation context
246655ff1a1SSrujanaChalla * @key: cipher key
247655ff1a1SSrujanaChalla * @iv: cipher IV
248655ff1a1SSrujanaChalla *
249655ff1a1SSrujanaChalla * Context associated to an hash or hmac operation.
250655ff1a1SSrujanaChalla */
251655ff1a1SSrujanaChalla struct mv_cesa_hash_op_ctx {
252655ff1a1SSrujanaChalla u32 iv[16];
253e62291c1SHerbert Xu __le32 hash[8];
254655ff1a1SSrujanaChalla };
255655ff1a1SSrujanaChalla
256655ff1a1SSrujanaChalla /**
257655ff1a1SSrujanaChalla * struct mv_cesa_op_ctx - crypto operation context
258655ff1a1SSrujanaChalla * @desc: CESA descriptor
259655ff1a1SSrujanaChalla * @ctx: context associated to the crypto operation
260655ff1a1SSrujanaChalla *
261655ff1a1SSrujanaChalla * Context associated to a crypto operation.
262655ff1a1SSrujanaChalla */
263655ff1a1SSrujanaChalla struct mv_cesa_op_ctx {
264655ff1a1SSrujanaChalla struct mv_cesa_sec_accel_desc desc;
265655ff1a1SSrujanaChalla union {
266655ff1a1SSrujanaChalla struct mv_cesa_skcipher_op_ctx skcipher;
267655ff1a1SSrujanaChalla struct mv_cesa_hash_op_ctx hash;
268655ff1a1SSrujanaChalla } ctx;
269655ff1a1SSrujanaChalla };
270655ff1a1SSrujanaChalla
271655ff1a1SSrujanaChalla /* TDMA descriptor flags */
272655ff1a1SSrujanaChalla #define CESA_TDMA_DST_IN_SRAM BIT(31)
273655ff1a1SSrujanaChalla #define CESA_TDMA_SRC_IN_SRAM BIT(30)
274655ff1a1SSrujanaChalla #define CESA_TDMA_END_OF_REQ BIT(29)
275655ff1a1SSrujanaChalla #define CESA_TDMA_BREAK_CHAIN BIT(28)
276655ff1a1SSrujanaChalla #define CESA_TDMA_SET_STATE BIT(27)
277655ff1a1SSrujanaChalla #define CESA_TDMA_TYPE_MSK GENMASK(26, 0)
278655ff1a1SSrujanaChalla #define CESA_TDMA_DUMMY 0
279655ff1a1SSrujanaChalla #define CESA_TDMA_DATA 1
280655ff1a1SSrujanaChalla #define CESA_TDMA_OP 2
281655ff1a1SSrujanaChalla #define CESA_TDMA_RESULT 3
282655ff1a1SSrujanaChalla
283655ff1a1SSrujanaChalla /**
284655ff1a1SSrujanaChalla * struct mv_cesa_tdma_desc - TDMA descriptor
285655ff1a1SSrujanaChalla * @byte_cnt: number of bytes to transfer
286655ff1a1SSrujanaChalla * @src: DMA address of the source
287655ff1a1SSrujanaChalla * @dst: DMA address of the destination
288655ff1a1SSrujanaChalla * @next_dma: DMA address of the next TDMA descriptor
289655ff1a1SSrujanaChalla * @cur_dma: DMA address of this TDMA descriptor
290655ff1a1SSrujanaChalla * @next: pointer to the next TDMA descriptor
291655ff1a1SSrujanaChalla * @op: CESA operation attached to this TDMA descriptor
292655ff1a1SSrujanaChalla * @data: raw data attached to this TDMA descriptor
293655ff1a1SSrujanaChalla * @flags: flags describing the TDMA transfer. See the
294655ff1a1SSrujanaChalla * "TDMA descriptor flags" section above
295655ff1a1SSrujanaChalla *
296655ff1a1SSrujanaChalla * TDMA descriptor used to create a transfer chain describing a crypto
297655ff1a1SSrujanaChalla * operation.
298655ff1a1SSrujanaChalla */
299655ff1a1SSrujanaChalla struct mv_cesa_tdma_desc {
300655ff1a1SSrujanaChalla __le32 byte_cnt;
301e62291c1SHerbert Xu union {
302655ff1a1SSrujanaChalla __le32 src;
3034f6543f2SHerbert Xu u32 src_dma;
304e62291c1SHerbert Xu };
305e62291c1SHerbert Xu union {
306655ff1a1SSrujanaChalla __le32 dst;
3074f6543f2SHerbert Xu u32 dst_dma;
308e62291c1SHerbert Xu };
309655ff1a1SSrujanaChalla __le32 next_dma;
310655ff1a1SSrujanaChalla
311655ff1a1SSrujanaChalla /* Software state */
312655ff1a1SSrujanaChalla dma_addr_t cur_dma;
313655ff1a1SSrujanaChalla struct mv_cesa_tdma_desc *next;
314655ff1a1SSrujanaChalla union {
315655ff1a1SSrujanaChalla struct mv_cesa_op_ctx *op;
316655ff1a1SSrujanaChalla void *data;
317655ff1a1SSrujanaChalla };
318655ff1a1SSrujanaChalla u32 flags;
319655ff1a1SSrujanaChalla };
320655ff1a1SSrujanaChalla
321655ff1a1SSrujanaChalla /**
322655ff1a1SSrujanaChalla * struct mv_cesa_sg_dma_iter - scatter-gather iterator
323655ff1a1SSrujanaChalla * @dir: transfer direction
324655ff1a1SSrujanaChalla * @sg: scatter list
325655ff1a1SSrujanaChalla * @offset: current position in the scatter list
326655ff1a1SSrujanaChalla * @op_offset: current position in the crypto operation
327655ff1a1SSrujanaChalla *
328655ff1a1SSrujanaChalla * Iterator used to iterate over a scatterlist while creating a TDMA chain for
329655ff1a1SSrujanaChalla * a crypto operation.
330655ff1a1SSrujanaChalla */
331655ff1a1SSrujanaChalla struct mv_cesa_sg_dma_iter {
332655ff1a1SSrujanaChalla enum dma_data_direction dir;
333655ff1a1SSrujanaChalla struct scatterlist *sg;
334655ff1a1SSrujanaChalla unsigned int offset;
335655ff1a1SSrujanaChalla unsigned int op_offset;
336655ff1a1SSrujanaChalla };
337655ff1a1SSrujanaChalla
338655ff1a1SSrujanaChalla /**
339655ff1a1SSrujanaChalla * struct mv_cesa_dma_iter - crypto operation iterator
340655ff1a1SSrujanaChalla * @len: the crypto operation length
341655ff1a1SSrujanaChalla * @offset: current position in the crypto operation
342655ff1a1SSrujanaChalla * @op_len: sub-operation length (the crypto engine can only act on 2kb
343655ff1a1SSrujanaChalla * chunks)
344655ff1a1SSrujanaChalla *
345655ff1a1SSrujanaChalla * Iterator used to create a TDMA chain for a given crypto operation.
346655ff1a1SSrujanaChalla */
347655ff1a1SSrujanaChalla struct mv_cesa_dma_iter {
348655ff1a1SSrujanaChalla unsigned int len;
349655ff1a1SSrujanaChalla unsigned int offset;
350655ff1a1SSrujanaChalla unsigned int op_len;
351655ff1a1SSrujanaChalla };
352655ff1a1SSrujanaChalla
353655ff1a1SSrujanaChalla /**
354655ff1a1SSrujanaChalla * struct mv_cesa_tdma_chain - TDMA chain
355655ff1a1SSrujanaChalla * @first: first entry in the TDMA chain
356655ff1a1SSrujanaChalla * @last: last entry in the TDMA chain
357655ff1a1SSrujanaChalla *
358655ff1a1SSrujanaChalla * Stores a TDMA chain for a specific crypto operation.
359655ff1a1SSrujanaChalla */
360655ff1a1SSrujanaChalla struct mv_cesa_tdma_chain {
361655ff1a1SSrujanaChalla struct mv_cesa_tdma_desc *first;
362655ff1a1SSrujanaChalla struct mv_cesa_tdma_desc *last;
363655ff1a1SSrujanaChalla };
364655ff1a1SSrujanaChalla
365655ff1a1SSrujanaChalla struct mv_cesa_engine;
366655ff1a1SSrujanaChalla
367655ff1a1SSrujanaChalla /**
368655ff1a1SSrujanaChalla * struct mv_cesa_caps - CESA device capabilities
369655ff1a1SSrujanaChalla * @engines: number of engines
370655ff1a1SSrujanaChalla * @has_tdma: whether this device has a TDMA block
371655ff1a1SSrujanaChalla * @cipher_algs: supported cipher algorithms
372655ff1a1SSrujanaChalla * @ncipher_algs: number of supported cipher algorithms
373655ff1a1SSrujanaChalla * @ahash_algs: supported hash algorithms
374655ff1a1SSrujanaChalla * @nahash_algs: number of supported hash algorithms
375655ff1a1SSrujanaChalla *
376655ff1a1SSrujanaChalla * Structure used to describe CESA device capabilities.
377655ff1a1SSrujanaChalla */
378655ff1a1SSrujanaChalla struct mv_cesa_caps {
379655ff1a1SSrujanaChalla int nengines;
380655ff1a1SSrujanaChalla bool has_tdma;
381655ff1a1SSrujanaChalla struct skcipher_alg **cipher_algs;
382655ff1a1SSrujanaChalla int ncipher_algs;
383655ff1a1SSrujanaChalla struct ahash_alg **ahash_algs;
384655ff1a1SSrujanaChalla int nahash_algs;
385655ff1a1SSrujanaChalla };
386655ff1a1SSrujanaChalla
387655ff1a1SSrujanaChalla /**
388655ff1a1SSrujanaChalla * struct mv_cesa_dev_dma - DMA pools
389655ff1a1SSrujanaChalla * @tdma_desc_pool: TDMA desc pool
390655ff1a1SSrujanaChalla * @op_pool: crypto operation pool
391655ff1a1SSrujanaChalla * @cache_pool: data cache pool (used by hash implementation when the
392655ff1a1SSrujanaChalla * hash request is smaller than the hash block size)
393655ff1a1SSrujanaChalla * @padding_pool: padding pool (used by hash implementation when hardware
394655ff1a1SSrujanaChalla * padding cannot be used)
395655ff1a1SSrujanaChalla *
396655ff1a1SSrujanaChalla * Structure containing the different DMA pools used by this driver.
397655ff1a1SSrujanaChalla */
398655ff1a1SSrujanaChalla struct mv_cesa_dev_dma {
399655ff1a1SSrujanaChalla struct dma_pool *tdma_desc_pool;
400655ff1a1SSrujanaChalla struct dma_pool *op_pool;
401655ff1a1SSrujanaChalla struct dma_pool *cache_pool;
402655ff1a1SSrujanaChalla struct dma_pool *padding_pool;
403655ff1a1SSrujanaChalla };
404655ff1a1SSrujanaChalla
405655ff1a1SSrujanaChalla /**
406655ff1a1SSrujanaChalla * struct mv_cesa_dev - CESA device
407655ff1a1SSrujanaChalla * @caps: device capabilities
408655ff1a1SSrujanaChalla * @regs: device registers
409655ff1a1SSrujanaChalla * @sram_size: usable SRAM size
410655ff1a1SSrujanaChalla * @lock: device lock
411655ff1a1SSrujanaChalla * @engines: array of engines
412655ff1a1SSrujanaChalla * @dma: dma pools
413655ff1a1SSrujanaChalla *
414655ff1a1SSrujanaChalla * Structure storing CESA device information.
415655ff1a1SSrujanaChalla */
416655ff1a1SSrujanaChalla struct mv_cesa_dev {
417655ff1a1SSrujanaChalla const struct mv_cesa_caps *caps;
418655ff1a1SSrujanaChalla void __iomem *regs;
419655ff1a1SSrujanaChalla struct device *dev;
420655ff1a1SSrujanaChalla unsigned int sram_size;
421655ff1a1SSrujanaChalla spinlock_t lock;
422655ff1a1SSrujanaChalla struct mv_cesa_engine *engines;
423655ff1a1SSrujanaChalla struct mv_cesa_dev_dma *dma;
424655ff1a1SSrujanaChalla };
425655ff1a1SSrujanaChalla
426655ff1a1SSrujanaChalla /**
427655ff1a1SSrujanaChalla * struct mv_cesa_engine - CESA engine
428655ff1a1SSrujanaChalla * @id: engine id
429655ff1a1SSrujanaChalla * @regs: engine registers
430655ff1a1SSrujanaChalla * @sram: SRAM memory region
431c114cf7fSHerbert Xu * @sram_pool: SRAM memory region from pool
432655ff1a1SSrujanaChalla * @sram_dma: DMA address of the SRAM memory region
433655ff1a1SSrujanaChalla * @lock: engine lock
434655ff1a1SSrujanaChalla * @req: current crypto request
435655ff1a1SSrujanaChalla * @clk: engine clk
436655ff1a1SSrujanaChalla * @zclk: engine zclk
437655ff1a1SSrujanaChalla * @max_req_len: maximum chunk length (useful to create the TDMA chain)
438655ff1a1SSrujanaChalla * @int_mask: interrupt mask cache
439655ff1a1SSrujanaChalla * @pool: memory pool pointing to the memory region reserved in
440655ff1a1SSrujanaChalla * SRAM
441655ff1a1SSrujanaChalla * @queue: fifo of the pending crypto requests
442655ff1a1SSrujanaChalla * @load: engine load counter, useful for load balancing
443655ff1a1SSrujanaChalla * @chain: list of the current tdma descriptors being processed
444655ff1a1SSrujanaChalla * by this engine.
445655ff1a1SSrujanaChalla * @complete_queue: fifo of the processed requests by the engine
446655ff1a1SSrujanaChalla *
447655ff1a1SSrujanaChalla * Structure storing CESA engine information.
448655ff1a1SSrujanaChalla */
449655ff1a1SSrujanaChalla struct mv_cesa_engine {
450655ff1a1SSrujanaChalla int id;
451655ff1a1SSrujanaChalla void __iomem *regs;
452c114cf7fSHerbert Xu union {
453655ff1a1SSrujanaChalla void __iomem *sram;
454c114cf7fSHerbert Xu void *sram_pool;
455c114cf7fSHerbert Xu };
456655ff1a1SSrujanaChalla dma_addr_t sram_dma;
457655ff1a1SSrujanaChalla spinlock_t lock;
458655ff1a1SSrujanaChalla struct crypto_async_request *req;
459655ff1a1SSrujanaChalla struct clk *clk;
460655ff1a1SSrujanaChalla struct clk *zclk;
461655ff1a1SSrujanaChalla size_t max_req_len;
462655ff1a1SSrujanaChalla u32 int_mask;
463655ff1a1SSrujanaChalla struct gen_pool *pool;
464655ff1a1SSrujanaChalla struct crypto_queue queue;
465655ff1a1SSrujanaChalla atomic_t load;
466655ff1a1SSrujanaChalla struct mv_cesa_tdma_chain chain;
467655ff1a1SSrujanaChalla struct list_head complete_queue;
46828ee8b09SSven Auhagen int irq;
469655ff1a1SSrujanaChalla };
470655ff1a1SSrujanaChalla
471655ff1a1SSrujanaChalla /**
472655ff1a1SSrujanaChalla * struct mv_cesa_req_ops - CESA request operations
473655ff1a1SSrujanaChalla * @process: process a request chunk result (should return 0 if the
474655ff1a1SSrujanaChalla * operation, -EINPROGRESS if it needs more steps or an error
475655ff1a1SSrujanaChalla * code)
476655ff1a1SSrujanaChalla * @step: launch the crypto operation on the next chunk
477655ff1a1SSrujanaChalla * @cleanup: cleanup the crypto request (release associated data)
478655ff1a1SSrujanaChalla * @complete: complete the request, i.e copy result or context from sram when
479655ff1a1SSrujanaChalla * needed.
480655ff1a1SSrujanaChalla */
481655ff1a1SSrujanaChalla struct mv_cesa_req_ops {
482655ff1a1SSrujanaChalla int (*process)(struct crypto_async_request *req, u32 status);
483655ff1a1SSrujanaChalla void (*step)(struct crypto_async_request *req);
484655ff1a1SSrujanaChalla void (*cleanup)(struct crypto_async_request *req);
485655ff1a1SSrujanaChalla void (*complete)(struct crypto_async_request *req);
486655ff1a1SSrujanaChalla };
487655ff1a1SSrujanaChalla
488655ff1a1SSrujanaChalla /**
489655ff1a1SSrujanaChalla * struct mv_cesa_ctx - CESA operation context
490655ff1a1SSrujanaChalla * @ops: crypto operations
491655ff1a1SSrujanaChalla *
492655ff1a1SSrujanaChalla * Base context structure inherited by operation specific ones.
493655ff1a1SSrujanaChalla */
494655ff1a1SSrujanaChalla struct mv_cesa_ctx {
495655ff1a1SSrujanaChalla const struct mv_cesa_req_ops *ops;
496655ff1a1SSrujanaChalla };
497655ff1a1SSrujanaChalla
498655ff1a1SSrujanaChalla /**
499655ff1a1SSrujanaChalla * struct mv_cesa_hash_ctx - CESA hash operation context
500655ff1a1SSrujanaChalla * @base: base context structure
501655ff1a1SSrujanaChalla *
502655ff1a1SSrujanaChalla * Hash context structure.
503655ff1a1SSrujanaChalla */
504655ff1a1SSrujanaChalla struct mv_cesa_hash_ctx {
505655ff1a1SSrujanaChalla struct mv_cesa_ctx base;
506655ff1a1SSrujanaChalla };
507655ff1a1SSrujanaChalla
508655ff1a1SSrujanaChalla /**
509655ff1a1SSrujanaChalla * struct mv_cesa_hash_ctx - CESA hmac operation context
510655ff1a1SSrujanaChalla * @base: base context structure
511655ff1a1SSrujanaChalla * @iv: initialization vectors
512655ff1a1SSrujanaChalla *
513655ff1a1SSrujanaChalla * HMAC context structure.
514655ff1a1SSrujanaChalla */
515655ff1a1SSrujanaChalla struct mv_cesa_hmac_ctx {
516655ff1a1SSrujanaChalla struct mv_cesa_ctx base;
517e62291c1SHerbert Xu __be32 iv[16];
518655ff1a1SSrujanaChalla };
519655ff1a1SSrujanaChalla
520655ff1a1SSrujanaChalla /**
521655ff1a1SSrujanaChalla * enum mv_cesa_req_type - request type definitions
522655ff1a1SSrujanaChalla * @CESA_STD_REQ: standard request
523655ff1a1SSrujanaChalla * @CESA_DMA_REQ: DMA request
524655ff1a1SSrujanaChalla */
525655ff1a1SSrujanaChalla enum mv_cesa_req_type {
526655ff1a1SSrujanaChalla CESA_STD_REQ,
527655ff1a1SSrujanaChalla CESA_DMA_REQ,
528655ff1a1SSrujanaChalla };
529655ff1a1SSrujanaChalla
530655ff1a1SSrujanaChalla /**
531655ff1a1SSrujanaChalla * struct mv_cesa_req - CESA request
532655ff1a1SSrujanaChalla * @engine: engine associated with this request
533655ff1a1SSrujanaChalla * @chain: list of tdma descriptors associated with this request
534655ff1a1SSrujanaChalla */
535655ff1a1SSrujanaChalla struct mv_cesa_req {
536655ff1a1SSrujanaChalla struct mv_cesa_engine *engine;
537655ff1a1SSrujanaChalla struct mv_cesa_tdma_chain chain;
538655ff1a1SSrujanaChalla };
539655ff1a1SSrujanaChalla
540655ff1a1SSrujanaChalla /**
541655ff1a1SSrujanaChalla * struct mv_cesa_sg_std_iter - CESA scatter-gather iterator for standard
542655ff1a1SSrujanaChalla * requests
543655ff1a1SSrujanaChalla * @iter: sg mapping iterator
544655ff1a1SSrujanaChalla * @offset: current offset in the SG entry mapped in memory
545655ff1a1SSrujanaChalla */
546655ff1a1SSrujanaChalla struct mv_cesa_sg_std_iter {
547655ff1a1SSrujanaChalla struct sg_mapping_iter iter;
548655ff1a1SSrujanaChalla unsigned int offset;
549655ff1a1SSrujanaChalla };
550655ff1a1SSrujanaChalla
551655ff1a1SSrujanaChalla /**
552655ff1a1SSrujanaChalla * struct mv_cesa_skcipher_std_req - cipher standard request
553655ff1a1SSrujanaChalla * @op: operation context
554655ff1a1SSrujanaChalla * @offset: current operation offset
555655ff1a1SSrujanaChalla * @size: size of the crypto operation
556655ff1a1SSrujanaChalla */
557655ff1a1SSrujanaChalla struct mv_cesa_skcipher_std_req {
558655ff1a1SSrujanaChalla struct mv_cesa_op_ctx op;
559655ff1a1SSrujanaChalla unsigned int offset;
560655ff1a1SSrujanaChalla unsigned int size;
561655ff1a1SSrujanaChalla bool skip_ctx;
562655ff1a1SSrujanaChalla };
563655ff1a1SSrujanaChalla
564655ff1a1SSrujanaChalla /**
565655ff1a1SSrujanaChalla * struct mv_cesa_skcipher_req - cipher request
566655ff1a1SSrujanaChalla * @req: type specific request information
567655ff1a1SSrujanaChalla * @src_nents: number of entries in the src sg list
568655ff1a1SSrujanaChalla * @dst_nents: number of entries in the dest sg list
569655ff1a1SSrujanaChalla */
570655ff1a1SSrujanaChalla struct mv_cesa_skcipher_req {
571655ff1a1SSrujanaChalla struct mv_cesa_req base;
572655ff1a1SSrujanaChalla struct mv_cesa_skcipher_std_req std;
573655ff1a1SSrujanaChalla int src_nents;
574655ff1a1SSrujanaChalla int dst_nents;
575655ff1a1SSrujanaChalla };
576655ff1a1SSrujanaChalla
577655ff1a1SSrujanaChalla /**
578655ff1a1SSrujanaChalla * struct mv_cesa_ahash_std_req - standard hash request
579655ff1a1SSrujanaChalla * @offset: current operation offset
580655ff1a1SSrujanaChalla */
581655ff1a1SSrujanaChalla struct mv_cesa_ahash_std_req {
582655ff1a1SSrujanaChalla unsigned int offset;
583655ff1a1SSrujanaChalla };
584655ff1a1SSrujanaChalla
585655ff1a1SSrujanaChalla /**
586655ff1a1SSrujanaChalla * struct mv_cesa_ahash_dma_req - DMA hash request
587655ff1a1SSrujanaChalla * @padding: padding buffer
588655ff1a1SSrujanaChalla * @padding_dma: DMA address of the padding buffer
589655ff1a1SSrujanaChalla * @cache_dma: DMA address of the cache buffer
590655ff1a1SSrujanaChalla */
591655ff1a1SSrujanaChalla struct mv_cesa_ahash_dma_req {
592655ff1a1SSrujanaChalla u8 *padding;
593655ff1a1SSrujanaChalla dma_addr_t padding_dma;
594655ff1a1SSrujanaChalla u8 *cache;
595655ff1a1SSrujanaChalla dma_addr_t cache_dma;
596655ff1a1SSrujanaChalla };
597655ff1a1SSrujanaChalla
598655ff1a1SSrujanaChalla /**
599655ff1a1SSrujanaChalla * struct mv_cesa_ahash_req - hash request
600655ff1a1SSrujanaChalla * @req: type specific request information
601655ff1a1SSrujanaChalla * @cache: cache buffer
602655ff1a1SSrujanaChalla * @cache_ptr: write pointer in the cache buffer
603655ff1a1SSrujanaChalla * @len: hash total length
604655ff1a1SSrujanaChalla * @src_nents: number of entries in the scatterlist
605655ff1a1SSrujanaChalla * @last_req: define whether the current operation is the last one
606655ff1a1SSrujanaChalla * or not
607655ff1a1SSrujanaChalla * @state: hash state
608655ff1a1SSrujanaChalla */
609655ff1a1SSrujanaChalla struct mv_cesa_ahash_req {
610655ff1a1SSrujanaChalla struct mv_cesa_req base;
611655ff1a1SSrujanaChalla union {
612655ff1a1SSrujanaChalla struct mv_cesa_ahash_dma_req dma;
613655ff1a1SSrujanaChalla struct mv_cesa_ahash_std_req std;
614655ff1a1SSrujanaChalla } req;
615655ff1a1SSrujanaChalla struct mv_cesa_op_ctx op_tmpl;
616655ff1a1SSrujanaChalla u8 cache[CESA_MAX_HASH_BLOCK_SIZE];
617655ff1a1SSrujanaChalla unsigned int cache_ptr;
618655ff1a1SSrujanaChalla u64 len;
619655ff1a1SSrujanaChalla int src_nents;
620655ff1a1SSrujanaChalla bool last_req;
621655ff1a1SSrujanaChalla bool algo_le;
622655ff1a1SSrujanaChalla u32 state[8];
623655ff1a1SSrujanaChalla };
624655ff1a1SSrujanaChalla
625655ff1a1SSrujanaChalla /* CESA functions */
626655ff1a1SSrujanaChalla
627655ff1a1SSrujanaChalla extern struct mv_cesa_dev *cesa_dev;
628655ff1a1SSrujanaChalla
629655ff1a1SSrujanaChalla
630655ff1a1SSrujanaChalla static inline void
mv_cesa_engine_enqueue_complete_request(struct mv_cesa_engine * engine,struct crypto_async_request * req)631655ff1a1SSrujanaChalla mv_cesa_engine_enqueue_complete_request(struct mv_cesa_engine *engine,
632655ff1a1SSrujanaChalla struct crypto_async_request *req)
633655ff1a1SSrujanaChalla {
634655ff1a1SSrujanaChalla list_add_tail(&req->list, &engine->complete_queue);
635655ff1a1SSrujanaChalla }
636655ff1a1SSrujanaChalla
637655ff1a1SSrujanaChalla static inline struct crypto_async_request *
mv_cesa_engine_dequeue_complete_request(struct mv_cesa_engine * engine)638655ff1a1SSrujanaChalla mv_cesa_engine_dequeue_complete_request(struct mv_cesa_engine *engine)
639655ff1a1SSrujanaChalla {
640655ff1a1SSrujanaChalla struct crypto_async_request *req;
641655ff1a1SSrujanaChalla
642655ff1a1SSrujanaChalla req = list_first_entry_or_null(&engine->complete_queue,
643655ff1a1SSrujanaChalla struct crypto_async_request,
644655ff1a1SSrujanaChalla list);
645655ff1a1SSrujanaChalla if (req)
646655ff1a1SSrujanaChalla list_del(&req->list);
647655ff1a1SSrujanaChalla
648655ff1a1SSrujanaChalla return req;
649655ff1a1SSrujanaChalla }
650655ff1a1SSrujanaChalla
651655ff1a1SSrujanaChalla
652655ff1a1SSrujanaChalla static inline enum mv_cesa_req_type
mv_cesa_req_get_type(struct mv_cesa_req * req)653655ff1a1SSrujanaChalla mv_cesa_req_get_type(struct mv_cesa_req *req)
654655ff1a1SSrujanaChalla {
655655ff1a1SSrujanaChalla return req->chain.first ? CESA_DMA_REQ : CESA_STD_REQ;
656655ff1a1SSrujanaChalla }
657655ff1a1SSrujanaChalla
mv_cesa_update_op_cfg(struct mv_cesa_op_ctx * op,u32 cfg,u32 mask)658655ff1a1SSrujanaChalla static inline void mv_cesa_update_op_cfg(struct mv_cesa_op_ctx *op,
659655ff1a1SSrujanaChalla u32 cfg, u32 mask)
660655ff1a1SSrujanaChalla {
661655ff1a1SSrujanaChalla op->desc.config &= cpu_to_le32(~mask);
662655ff1a1SSrujanaChalla op->desc.config |= cpu_to_le32(cfg);
663655ff1a1SSrujanaChalla }
664655ff1a1SSrujanaChalla
mv_cesa_get_op_cfg(const struct mv_cesa_op_ctx * op)665655ff1a1SSrujanaChalla static inline u32 mv_cesa_get_op_cfg(const struct mv_cesa_op_ctx *op)
666655ff1a1SSrujanaChalla {
667655ff1a1SSrujanaChalla return le32_to_cpu(op->desc.config);
668655ff1a1SSrujanaChalla }
669655ff1a1SSrujanaChalla
mv_cesa_set_op_cfg(struct mv_cesa_op_ctx * op,u32 cfg)670655ff1a1SSrujanaChalla static inline void mv_cesa_set_op_cfg(struct mv_cesa_op_ctx *op, u32 cfg)
671655ff1a1SSrujanaChalla {
672655ff1a1SSrujanaChalla op->desc.config = cpu_to_le32(cfg);
673655ff1a1SSrujanaChalla }
674655ff1a1SSrujanaChalla
mv_cesa_adjust_op(struct mv_cesa_engine * engine,struct mv_cesa_op_ctx * op)675655ff1a1SSrujanaChalla static inline void mv_cesa_adjust_op(struct mv_cesa_engine *engine,
676655ff1a1SSrujanaChalla struct mv_cesa_op_ctx *op)
677655ff1a1SSrujanaChalla {
678655ff1a1SSrujanaChalla u32 offset = engine->sram_dma & CESA_SA_SRAM_MSK;
679655ff1a1SSrujanaChalla
680655ff1a1SSrujanaChalla op->desc.enc_p = CESA_SA_DESC_CRYPT_DATA(offset);
681655ff1a1SSrujanaChalla op->desc.enc_key_p = CESA_SA_DESC_CRYPT_KEY(offset);
682655ff1a1SSrujanaChalla op->desc.enc_iv = CESA_SA_DESC_CRYPT_IV(offset);
683655ff1a1SSrujanaChalla op->desc.mac_src_p &= ~CESA_SA_DESC_MAC_DATA_MSK;
684655ff1a1SSrujanaChalla op->desc.mac_src_p |= CESA_SA_DESC_MAC_DATA(offset);
685655ff1a1SSrujanaChalla op->desc.mac_digest &= ~CESA_SA_DESC_MAC_DIGEST_MSK;
686655ff1a1SSrujanaChalla op->desc.mac_digest |= CESA_SA_DESC_MAC_DIGEST(offset);
687655ff1a1SSrujanaChalla op->desc.mac_iv = CESA_SA_DESC_MAC_IV(offset);
688655ff1a1SSrujanaChalla }
689655ff1a1SSrujanaChalla
mv_cesa_set_crypt_op_len(struct mv_cesa_op_ctx * op,int len)690655ff1a1SSrujanaChalla static inline void mv_cesa_set_crypt_op_len(struct mv_cesa_op_ctx *op, int len)
691655ff1a1SSrujanaChalla {
692655ff1a1SSrujanaChalla op->desc.enc_len = cpu_to_le32(len);
693655ff1a1SSrujanaChalla }
694655ff1a1SSrujanaChalla
mv_cesa_set_mac_op_total_len(struct mv_cesa_op_ctx * op,int len)695655ff1a1SSrujanaChalla static inline void mv_cesa_set_mac_op_total_len(struct mv_cesa_op_ctx *op,
696655ff1a1SSrujanaChalla int len)
697655ff1a1SSrujanaChalla {
698655ff1a1SSrujanaChalla op->desc.mac_src_p &= ~CESA_SA_DESC_MAC_TOTAL_LEN_MSK;
699655ff1a1SSrujanaChalla op->desc.mac_src_p |= CESA_SA_DESC_MAC_TOTAL_LEN(len);
700655ff1a1SSrujanaChalla }
701655ff1a1SSrujanaChalla
mv_cesa_set_mac_op_frag_len(struct mv_cesa_op_ctx * op,int len)702655ff1a1SSrujanaChalla static inline void mv_cesa_set_mac_op_frag_len(struct mv_cesa_op_ctx *op,
703655ff1a1SSrujanaChalla int len)
704655ff1a1SSrujanaChalla {
705655ff1a1SSrujanaChalla op->desc.mac_digest &= ~CESA_SA_DESC_MAC_FRAG_LEN_MSK;
706655ff1a1SSrujanaChalla op->desc.mac_digest |= CESA_SA_DESC_MAC_FRAG_LEN(len);
707655ff1a1SSrujanaChalla }
708655ff1a1SSrujanaChalla
mv_cesa_set_int_mask(struct mv_cesa_engine * engine,u32 int_mask)709655ff1a1SSrujanaChalla static inline void mv_cesa_set_int_mask(struct mv_cesa_engine *engine,
710655ff1a1SSrujanaChalla u32 int_mask)
711655ff1a1SSrujanaChalla {
712655ff1a1SSrujanaChalla if (int_mask == engine->int_mask)
713655ff1a1SSrujanaChalla return;
714655ff1a1SSrujanaChalla
715655ff1a1SSrujanaChalla writel_relaxed(int_mask, engine->regs + CESA_SA_INT_MSK);
716655ff1a1SSrujanaChalla engine->int_mask = int_mask;
717655ff1a1SSrujanaChalla }
718655ff1a1SSrujanaChalla
mv_cesa_get_int_mask(struct mv_cesa_engine * engine)719655ff1a1SSrujanaChalla static inline u32 mv_cesa_get_int_mask(struct mv_cesa_engine *engine)
720655ff1a1SSrujanaChalla {
721655ff1a1SSrujanaChalla return engine->int_mask;
722655ff1a1SSrujanaChalla }
723655ff1a1SSrujanaChalla
mv_cesa_mac_op_is_first_frag(const struct mv_cesa_op_ctx * op)724655ff1a1SSrujanaChalla static inline bool mv_cesa_mac_op_is_first_frag(const struct mv_cesa_op_ctx *op)
725655ff1a1SSrujanaChalla {
726655ff1a1SSrujanaChalla return (mv_cesa_get_op_cfg(op) & CESA_SA_DESC_CFG_FRAG_MSK) ==
727655ff1a1SSrujanaChalla CESA_SA_DESC_CFG_FIRST_FRAG;
728655ff1a1SSrujanaChalla }
729655ff1a1SSrujanaChalla
730655ff1a1SSrujanaChalla int mv_cesa_queue_req(struct crypto_async_request *req,
731655ff1a1SSrujanaChalla struct mv_cesa_req *creq);
732655ff1a1SSrujanaChalla
733655ff1a1SSrujanaChalla struct crypto_async_request *
734655ff1a1SSrujanaChalla mv_cesa_dequeue_req_locked(struct mv_cesa_engine *engine,
735655ff1a1SSrujanaChalla struct crypto_async_request **backlog);
736655ff1a1SSrujanaChalla
mv_cesa_select_engine(int weight)737655ff1a1SSrujanaChalla static inline struct mv_cesa_engine *mv_cesa_select_engine(int weight)
738655ff1a1SSrujanaChalla {
739655ff1a1SSrujanaChalla int i;
740655ff1a1SSrujanaChalla u32 min_load = U32_MAX;
741655ff1a1SSrujanaChalla struct mv_cesa_engine *selected = NULL;
742655ff1a1SSrujanaChalla
743655ff1a1SSrujanaChalla for (i = 0; i < cesa_dev->caps->nengines; i++) {
744655ff1a1SSrujanaChalla struct mv_cesa_engine *engine = cesa_dev->engines + i;
745655ff1a1SSrujanaChalla u32 load = atomic_read(&engine->load);
746655ff1a1SSrujanaChalla
747655ff1a1SSrujanaChalla if (load < min_load) {
748655ff1a1SSrujanaChalla min_load = load;
749655ff1a1SSrujanaChalla selected = engine;
750655ff1a1SSrujanaChalla }
751655ff1a1SSrujanaChalla }
752655ff1a1SSrujanaChalla
753655ff1a1SSrujanaChalla atomic_add(weight, &selected->load);
754655ff1a1SSrujanaChalla
755655ff1a1SSrujanaChalla return selected;
756655ff1a1SSrujanaChalla }
757655ff1a1SSrujanaChalla
758655ff1a1SSrujanaChalla /*
759655ff1a1SSrujanaChalla * Helper function that indicates whether a crypto request needs to be
760655ff1a1SSrujanaChalla * cleaned up or not after being enqueued using mv_cesa_queue_req().
761655ff1a1SSrujanaChalla */
mv_cesa_req_needs_cleanup(struct crypto_async_request * req,int ret)762655ff1a1SSrujanaChalla static inline int mv_cesa_req_needs_cleanup(struct crypto_async_request *req,
763655ff1a1SSrujanaChalla int ret)
764655ff1a1SSrujanaChalla {
765655ff1a1SSrujanaChalla /*
766655ff1a1SSrujanaChalla * The queue still had some space, the request was queued
767655ff1a1SSrujanaChalla * normally, so there's no need to clean it up.
768655ff1a1SSrujanaChalla */
769655ff1a1SSrujanaChalla if (ret == -EINPROGRESS)
770655ff1a1SSrujanaChalla return false;
771655ff1a1SSrujanaChalla
772655ff1a1SSrujanaChalla /*
773655ff1a1SSrujanaChalla * The queue had not space left, but since the request is
774655ff1a1SSrujanaChalla * flagged with CRYPTO_TFM_REQ_MAY_BACKLOG, it was added to
775655ff1a1SSrujanaChalla * the backlog and will be processed later. There's no need to
776655ff1a1SSrujanaChalla * clean it up.
777655ff1a1SSrujanaChalla */
778655ff1a1SSrujanaChalla if (ret == -EBUSY)
779655ff1a1SSrujanaChalla return false;
780655ff1a1SSrujanaChalla
781655ff1a1SSrujanaChalla /* Request wasn't queued, we need to clean it up */
782655ff1a1SSrujanaChalla return true;
783655ff1a1SSrujanaChalla }
784655ff1a1SSrujanaChalla
785655ff1a1SSrujanaChalla /* TDMA functions */
786655ff1a1SSrujanaChalla
mv_cesa_req_dma_iter_init(struct mv_cesa_dma_iter * iter,unsigned int len)787655ff1a1SSrujanaChalla static inline void mv_cesa_req_dma_iter_init(struct mv_cesa_dma_iter *iter,
788655ff1a1SSrujanaChalla unsigned int len)
789655ff1a1SSrujanaChalla {
790655ff1a1SSrujanaChalla iter->len = len;
791655ff1a1SSrujanaChalla iter->op_len = min(len, CESA_SA_SRAM_PAYLOAD_SIZE);
792655ff1a1SSrujanaChalla iter->offset = 0;
793655ff1a1SSrujanaChalla }
794655ff1a1SSrujanaChalla
mv_cesa_sg_dma_iter_init(struct mv_cesa_sg_dma_iter * iter,struct scatterlist * sg,enum dma_data_direction dir)795655ff1a1SSrujanaChalla static inline void mv_cesa_sg_dma_iter_init(struct mv_cesa_sg_dma_iter *iter,
796655ff1a1SSrujanaChalla struct scatterlist *sg,
797655ff1a1SSrujanaChalla enum dma_data_direction dir)
798655ff1a1SSrujanaChalla {
799655ff1a1SSrujanaChalla iter->op_offset = 0;
800655ff1a1SSrujanaChalla iter->offset = 0;
801655ff1a1SSrujanaChalla iter->sg = sg;
802655ff1a1SSrujanaChalla iter->dir = dir;
803655ff1a1SSrujanaChalla }
804655ff1a1SSrujanaChalla
805655ff1a1SSrujanaChalla static inline unsigned int
mv_cesa_req_dma_iter_transfer_len(struct mv_cesa_dma_iter * iter,struct mv_cesa_sg_dma_iter * sgiter)806655ff1a1SSrujanaChalla mv_cesa_req_dma_iter_transfer_len(struct mv_cesa_dma_iter *iter,
807655ff1a1SSrujanaChalla struct mv_cesa_sg_dma_iter *sgiter)
808655ff1a1SSrujanaChalla {
809655ff1a1SSrujanaChalla return min(iter->op_len - sgiter->op_offset,
810655ff1a1SSrujanaChalla sg_dma_len(sgiter->sg) - sgiter->offset);
811655ff1a1SSrujanaChalla }
812655ff1a1SSrujanaChalla
813655ff1a1SSrujanaChalla bool mv_cesa_req_dma_iter_next_transfer(struct mv_cesa_dma_iter *chain,
814655ff1a1SSrujanaChalla struct mv_cesa_sg_dma_iter *sgiter,
815655ff1a1SSrujanaChalla unsigned int len);
816655ff1a1SSrujanaChalla
mv_cesa_req_dma_iter_next_op(struct mv_cesa_dma_iter * iter)817655ff1a1SSrujanaChalla static inline bool mv_cesa_req_dma_iter_next_op(struct mv_cesa_dma_iter *iter)
818655ff1a1SSrujanaChalla {
819655ff1a1SSrujanaChalla iter->offset += iter->op_len;
820655ff1a1SSrujanaChalla iter->op_len = min(iter->len - iter->offset,
821655ff1a1SSrujanaChalla CESA_SA_SRAM_PAYLOAD_SIZE);
822655ff1a1SSrujanaChalla
823655ff1a1SSrujanaChalla return iter->op_len;
824655ff1a1SSrujanaChalla }
825655ff1a1SSrujanaChalla
826655ff1a1SSrujanaChalla void mv_cesa_dma_step(struct mv_cesa_req *dreq);
827655ff1a1SSrujanaChalla
mv_cesa_dma_process(struct mv_cesa_req * dreq,u32 status)828655ff1a1SSrujanaChalla static inline int mv_cesa_dma_process(struct mv_cesa_req *dreq,
829655ff1a1SSrujanaChalla u32 status)
830655ff1a1SSrujanaChalla {
831655ff1a1SSrujanaChalla if (!(status & CESA_SA_INT_ACC0_IDMA_DONE))
832655ff1a1SSrujanaChalla return -EINPROGRESS;
833655ff1a1SSrujanaChalla
834655ff1a1SSrujanaChalla if (status & CESA_SA_INT_IDMA_OWN_ERR)
835655ff1a1SSrujanaChalla return -EINVAL;
836655ff1a1SSrujanaChalla
837655ff1a1SSrujanaChalla return 0;
838655ff1a1SSrujanaChalla }
839655ff1a1SSrujanaChalla
840655ff1a1SSrujanaChalla void mv_cesa_dma_prepare(struct mv_cesa_req *dreq,
841655ff1a1SSrujanaChalla struct mv_cesa_engine *engine);
842655ff1a1SSrujanaChalla void mv_cesa_dma_cleanup(struct mv_cesa_req *dreq);
843655ff1a1SSrujanaChalla void mv_cesa_tdma_chain(struct mv_cesa_engine *engine,
844655ff1a1SSrujanaChalla struct mv_cesa_req *dreq);
845655ff1a1SSrujanaChalla int mv_cesa_tdma_process(struct mv_cesa_engine *engine, u32 status);
846655ff1a1SSrujanaChalla
847655ff1a1SSrujanaChalla
848655ff1a1SSrujanaChalla static inline void
mv_cesa_tdma_desc_iter_init(struct mv_cesa_tdma_chain * chain)849655ff1a1SSrujanaChalla mv_cesa_tdma_desc_iter_init(struct mv_cesa_tdma_chain *chain)
850655ff1a1SSrujanaChalla {
851655ff1a1SSrujanaChalla memset(chain, 0, sizeof(*chain));
852655ff1a1SSrujanaChalla }
853655ff1a1SSrujanaChalla
854655ff1a1SSrujanaChalla int mv_cesa_dma_add_result_op(struct mv_cesa_tdma_chain *chain, dma_addr_t src,
855655ff1a1SSrujanaChalla u32 size, u32 flags, gfp_t gfp_flags);
856655ff1a1SSrujanaChalla
857655ff1a1SSrujanaChalla struct mv_cesa_op_ctx *mv_cesa_dma_add_op(struct mv_cesa_tdma_chain *chain,
858655ff1a1SSrujanaChalla const struct mv_cesa_op_ctx *op_templ,
859655ff1a1SSrujanaChalla bool skip_ctx,
860655ff1a1SSrujanaChalla gfp_t flags);
861655ff1a1SSrujanaChalla
862655ff1a1SSrujanaChalla int mv_cesa_dma_add_data_transfer(struct mv_cesa_tdma_chain *chain,
863655ff1a1SSrujanaChalla dma_addr_t dst, dma_addr_t src, u32 size,
864655ff1a1SSrujanaChalla u32 flags, gfp_t gfp_flags);
865655ff1a1SSrujanaChalla
866655ff1a1SSrujanaChalla int mv_cesa_dma_add_dummy_launch(struct mv_cesa_tdma_chain *chain, gfp_t flags);
867655ff1a1SSrujanaChalla int mv_cesa_dma_add_dummy_end(struct mv_cesa_tdma_chain *chain, gfp_t flags);
868655ff1a1SSrujanaChalla
869655ff1a1SSrujanaChalla int mv_cesa_dma_add_op_transfers(struct mv_cesa_tdma_chain *chain,
870655ff1a1SSrujanaChalla struct mv_cesa_dma_iter *dma_iter,
871655ff1a1SSrujanaChalla struct mv_cesa_sg_dma_iter *sgiter,
872655ff1a1SSrujanaChalla gfp_t gfp_flags);
873655ff1a1SSrujanaChalla
874c114cf7fSHerbert Xu size_t mv_cesa_sg_copy(struct mv_cesa_engine *engine,
875c114cf7fSHerbert Xu struct scatterlist *sgl, unsigned int nents,
876c114cf7fSHerbert Xu unsigned int sram_off, size_t buflen, off_t skip,
877c114cf7fSHerbert Xu bool to_sram);
878c114cf7fSHerbert Xu
mv_cesa_sg_copy_to_sram(struct mv_cesa_engine * engine,struct scatterlist * sgl,unsigned int nents,unsigned int sram_off,size_t buflen,off_t skip)879c114cf7fSHerbert Xu static inline size_t mv_cesa_sg_copy_to_sram(struct mv_cesa_engine *engine,
880c114cf7fSHerbert Xu struct scatterlist *sgl,
881c114cf7fSHerbert Xu unsigned int nents,
882c114cf7fSHerbert Xu unsigned int sram_off,
883c114cf7fSHerbert Xu size_t buflen, off_t skip)
884c114cf7fSHerbert Xu {
885c114cf7fSHerbert Xu return mv_cesa_sg_copy(engine, sgl, nents, sram_off, buflen, skip,
886c114cf7fSHerbert Xu true);
887c114cf7fSHerbert Xu }
888c114cf7fSHerbert Xu
mv_cesa_sg_copy_from_sram(struct mv_cesa_engine * engine,struct scatterlist * sgl,unsigned int nents,unsigned int sram_off,size_t buflen,off_t skip)889c114cf7fSHerbert Xu static inline size_t mv_cesa_sg_copy_from_sram(struct mv_cesa_engine *engine,
890c114cf7fSHerbert Xu struct scatterlist *sgl,
891c114cf7fSHerbert Xu unsigned int nents,
892c114cf7fSHerbert Xu unsigned int sram_off,
893c114cf7fSHerbert Xu size_t buflen, off_t skip)
894c114cf7fSHerbert Xu {
895c114cf7fSHerbert Xu return mv_cesa_sg_copy(engine, sgl, nents, sram_off, buflen, skip,
896c114cf7fSHerbert Xu false);
897c114cf7fSHerbert Xu }
898c114cf7fSHerbert Xu
899655ff1a1SSrujanaChalla /* Algorithm definitions */
900655ff1a1SSrujanaChalla
901655ff1a1SSrujanaChalla extern struct ahash_alg mv_md5_alg;
902655ff1a1SSrujanaChalla extern struct ahash_alg mv_sha1_alg;
903655ff1a1SSrujanaChalla extern struct ahash_alg mv_sha256_alg;
904655ff1a1SSrujanaChalla extern struct ahash_alg mv_ahmac_md5_alg;
905655ff1a1SSrujanaChalla extern struct ahash_alg mv_ahmac_sha1_alg;
906655ff1a1SSrujanaChalla extern struct ahash_alg mv_ahmac_sha256_alg;
907655ff1a1SSrujanaChalla
908655ff1a1SSrujanaChalla extern struct skcipher_alg mv_cesa_ecb_des_alg;
909655ff1a1SSrujanaChalla extern struct skcipher_alg mv_cesa_cbc_des_alg;
910655ff1a1SSrujanaChalla extern struct skcipher_alg mv_cesa_ecb_des3_ede_alg;
911655ff1a1SSrujanaChalla extern struct skcipher_alg mv_cesa_cbc_des3_ede_alg;
912655ff1a1SSrujanaChalla extern struct skcipher_alg mv_cesa_ecb_aes_alg;
913655ff1a1SSrujanaChalla extern struct skcipher_alg mv_cesa_cbc_aes_alg;
914655ff1a1SSrujanaChalla
915655ff1a1SSrujanaChalla #endif /* __MARVELL_CESA_H__ */
916