1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
2 /* Copyright(c) 2014 - 2020 Intel Corporation */
3 #ifndef ADF_ACCEL_DEVICES_H_
4 #define ADF_ACCEL_DEVICES_H_
5 #include <linux/interrupt.h>
6 #include <linux/module.h>
7 #include <linux/list.h>
8 #include <linux/io.h>
9 #include <linux/ratelimit.h>
10 #include "adf_cfg_common.h"
11 #include "adf_pfvf_msg.h"
12 
13 #define ADF_DH895XCC_DEVICE_NAME "dh895xcc"
14 #define ADF_DH895XCCVF_DEVICE_NAME "dh895xccvf"
15 #define ADF_C62X_DEVICE_NAME "c6xx"
16 #define ADF_C62XVF_DEVICE_NAME "c6xxvf"
17 #define ADF_C3XXX_DEVICE_NAME "c3xxx"
18 #define ADF_C3XXXVF_DEVICE_NAME "c3xxxvf"
19 #define ADF_4XXX_DEVICE_NAME "4xxx"
20 #define ADF_4XXX_PCI_DEVICE_ID 0x4940
21 #define ADF_4XXXIOV_PCI_DEVICE_ID 0x4941
22 #define ADF_401XX_PCI_DEVICE_ID 0x4942
23 #define ADF_401XXIOV_PCI_DEVICE_ID 0x4943
24 #define ADF_402XX_PCI_DEVICE_ID 0x4944
25 #define ADF_402XXIOV_PCI_DEVICE_ID 0x4945
26 #define ADF_DEVICE_FUSECTL_OFFSET 0x40
27 #define ADF_DEVICE_LEGFUSE_OFFSET 0x4C
28 #define ADF_DEVICE_FUSECTL_MASK 0x80000000
29 #define ADF_PCI_MAX_BARS 3
30 #define ADF_DEVICE_NAME_LENGTH 32
31 #define ADF_ETR_MAX_RINGS_PER_BANK 16
32 #define ADF_MAX_MSIX_VECTOR_NAME 48
33 #define ADF_DEVICE_NAME_PREFIX "qat_"
34 
35 enum adf_accel_capabilities {
36 	ADF_ACCEL_CAPABILITIES_NULL = 0,
37 	ADF_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC = 1,
38 	ADF_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC = 2,
39 	ADF_ACCEL_CAPABILITIES_CIPHER = 4,
40 	ADF_ACCEL_CAPABILITIES_AUTHENTICATION = 8,
41 	ADF_ACCEL_CAPABILITIES_COMPRESSION = 32,
42 	ADF_ACCEL_CAPABILITIES_LZS_COMPRESSION = 64,
43 	ADF_ACCEL_CAPABILITIES_RANDOM_NUMBER = 128
44 };
45 
46 struct adf_bar {
47 	resource_size_t base_addr;
48 	void __iomem *virt_addr;
49 	resource_size_t size;
50 };
51 
52 struct adf_irq {
53 	bool enabled;
54 	char name[ADF_MAX_MSIX_VECTOR_NAME];
55 };
56 
57 struct adf_accel_msix {
58 	struct adf_irq *irqs;
59 	u32 num_entries;
60 };
61 
62 struct adf_accel_pci {
63 	struct pci_dev *pci_dev;
64 	struct adf_accel_msix msix_entries;
65 	struct adf_bar pci_bars[ADF_PCI_MAX_BARS];
66 	u8 revid;
67 	u8 sku;
68 };
69 
70 enum dev_state {
71 	DEV_DOWN = 0,
72 	DEV_UP
73 };
74 
75 enum dev_sku_info {
76 	DEV_SKU_1 = 0,
77 	DEV_SKU_2,
78 	DEV_SKU_3,
79 	DEV_SKU_4,
80 	DEV_SKU_VF,
81 	DEV_SKU_UNKNOWN,
82 };
83 
84 static inline const char *get_sku_info(enum dev_sku_info info)
85 {
86 	switch (info) {
87 	case DEV_SKU_1:
88 		return "SKU1";
89 	case DEV_SKU_2:
90 		return "SKU2";
91 	case DEV_SKU_3:
92 		return "SKU3";
93 	case DEV_SKU_4:
94 		return "SKU4";
95 	case DEV_SKU_VF:
96 		return "SKUVF";
97 	case DEV_SKU_UNKNOWN:
98 	default:
99 		break;
100 	}
101 	return "Unknown SKU";
102 }
103 
104 struct adf_hw_device_class {
105 	const char *name;
106 	const enum adf_device_type type;
107 	u32 instances;
108 };
109 
110 struct arb_info {
111 	u32 arb_cfg;
112 	u32 arb_offset;
113 	u32 wt2sam_offset;
114 };
115 
116 struct admin_info {
117 	u32 admin_msg_ur;
118 	u32 admin_msg_lr;
119 	u32 mailbox_offset;
120 };
121 
122 struct adf_hw_csr_ops {
123 	u64 (*build_csr_ring_base_addr)(dma_addr_t addr, u32 size);
124 	u32 (*read_csr_ring_head)(void __iomem *csr_base_addr, u32 bank,
125 				  u32 ring);
126 	void (*write_csr_ring_head)(void __iomem *csr_base_addr, u32 bank,
127 				    u32 ring, u32 value);
128 	u32 (*read_csr_ring_tail)(void __iomem *csr_base_addr, u32 bank,
129 				  u32 ring);
130 	void (*write_csr_ring_tail)(void __iomem *csr_base_addr, u32 bank,
131 				    u32 ring, u32 value);
132 	u32 (*read_csr_e_stat)(void __iomem *csr_base_addr, u32 bank);
133 	void (*write_csr_ring_config)(void __iomem *csr_base_addr, u32 bank,
134 				      u32 ring, u32 value);
135 	void (*write_csr_ring_base)(void __iomem *csr_base_addr, u32 bank,
136 				    u32 ring, dma_addr_t addr);
137 	void (*write_csr_int_flag)(void __iomem *csr_base_addr, u32 bank,
138 				   u32 value);
139 	void (*write_csr_int_srcsel)(void __iomem *csr_base_addr, u32 bank);
140 	void (*write_csr_int_col_en)(void __iomem *csr_base_addr, u32 bank,
141 				     u32 value);
142 	void (*write_csr_int_col_ctl)(void __iomem *csr_base_addr, u32 bank,
143 				      u32 value);
144 	void (*write_csr_int_flag_and_col)(void __iomem *csr_base_addr,
145 					   u32 bank, u32 value);
146 	void (*write_csr_ring_srv_arb_en)(void __iomem *csr_base_addr, u32 bank,
147 					  u32 value);
148 };
149 
150 struct adf_cfg_device_data;
151 struct adf_accel_dev;
152 struct adf_etr_data;
153 struct adf_etr_ring_data;
154 
155 struct adf_pfvf_ops {
156 	int (*enable_comms)(struct adf_accel_dev *accel_dev);
157 	u32 (*get_pf2vf_offset)(u32 i);
158 	u32 (*get_vf2pf_offset)(u32 i);
159 	void (*enable_vf2pf_interrupts)(void __iomem *pmisc_addr, u32 vf_mask);
160 	void (*disable_all_vf2pf_interrupts)(void __iomem *pmisc_addr);
161 	u32 (*disable_pending_vf2pf_interrupts)(void __iomem *pmisc_addr);
162 	int (*send_msg)(struct adf_accel_dev *accel_dev, struct pfvf_message msg,
163 			u32 pfvf_offset, struct mutex *csr_lock);
164 	struct pfvf_message (*recv_msg)(struct adf_accel_dev *accel_dev,
165 					u32 pfvf_offset, u8 compat_ver);
166 };
167 
168 struct adf_dc_ops {
169 	void (*build_deflate_ctx)(void *ctx);
170 };
171 
172 struct adf_hw_device_data {
173 	struct adf_hw_device_class *dev_class;
174 	u32 (*get_accel_mask)(struct adf_hw_device_data *self);
175 	u32 (*get_ae_mask)(struct adf_hw_device_data *self);
176 	u32 (*get_accel_cap)(struct adf_accel_dev *accel_dev);
177 	u32 (*get_sram_bar_id)(struct adf_hw_device_data *self);
178 	u32 (*get_misc_bar_id)(struct adf_hw_device_data *self);
179 	u32 (*get_etr_bar_id)(struct adf_hw_device_data *self);
180 	u32 (*get_num_aes)(struct adf_hw_device_data *self);
181 	u32 (*get_num_accels)(struct adf_hw_device_data *self);
182 	void (*get_arb_info)(struct arb_info *arb_csrs_info);
183 	void (*get_admin_info)(struct admin_info *admin_csrs_info);
184 	enum dev_sku_info (*get_sku)(struct adf_hw_device_data *self);
185 	u16 (*get_ring_to_svc_map)(struct adf_accel_dev *accel_dev);
186 	int (*alloc_irq)(struct adf_accel_dev *accel_dev);
187 	void (*free_irq)(struct adf_accel_dev *accel_dev);
188 	void (*enable_error_correction)(struct adf_accel_dev *accel_dev);
189 	int (*init_admin_comms)(struct adf_accel_dev *accel_dev);
190 	void (*exit_admin_comms)(struct adf_accel_dev *accel_dev);
191 	int (*send_admin_init)(struct adf_accel_dev *accel_dev);
192 	int (*start_timer)(struct adf_accel_dev *accel_dev);
193 	void (*stop_timer)(struct adf_accel_dev *accel_dev);
194 	void (*check_hb_ctrs)(struct adf_accel_dev *accel_dev);
195 	uint32_t (*get_hb_clock)(struct adf_hw_device_data *self);
196 	int (*measure_clock)(struct adf_accel_dev *accel_dev);
197 	int (*init_arb)(struct adf_accel_dev *accel_dev);
198 	void (*exit_arb)(struct adf_accel_dev *accel_dev);
199 	const u32 *(*get_arb_mapping)(struct adf_accel_dev *accel_dev);
200 	int (*init_device)(struct adf_accel_dev *accel_dev);
201 	int (*enable_pm)(struct adf_accel_dev *accel_dev);
202 	bool (*handle_pm_interrupt)(struct adf_accel_dev *accel_dev);
203 	void (*disable_iov)(struct adf_accel_dev *accel_dev);
204 	void (*configure_iov_threads)(struct adf_accel_dev *accel_dev,
205 				      bool enable);
206 	void (*enable_ints)(struct adf_accel_dev *accel_dev);
207 	void (*set_ssm_wdtimer)(struct adf_accel_dev *accel_dev);
208 	int (*ring_pair_reset)(struct adf_accel_dev *accel_dev, u32 bank_nr);
209 	void (*reset_device)(struct adf_accel_dev *accel_dev);
210 	void (*set_msix_rttable)(struct adf_accel_dev *accel_dev);
211 	const char *(*uof_get_name)(struct adf_accel_dev *accel_dev, u32 obj_num);
212 	u32 (*uof_get_num_objs)(void);
213 	u32 (*uof_get_ae_mask)(struct adf_accel_dev *accel_dev, u32 obj_num);
214 	int (*dev_config)(struct adf_accel_dev *accel_dev);
215 	struct adf_pfvf_ops pfvf_ops;
216 	struct adf_hw_csr_ops csr_ops;
217 	struct adf_dc_ops dc_ops;
218 	const char *fw_name;
219 	const char *fw_mmp_name;
220 	u32 fuses;
221 	u32 straps;
222 	u32 accel_capabilities_mask;
223 	u32 extended_dc_capabilities;
224 	u32 clock_frequency;
225 	u32 instance_id;
226 	u16 accel_mask;
227 	u32 ae_mask;
228 	u32 admin_ae_mask;
229 	u16 tx_rings_mask;
230 	u16 ring_to_svc_map;
231 	u8 tx_rx_gap;
232 	u8 num_banks;
233 	u16 num_banks_per_vf;
234 	u8 num_rings_per_bank;
235 	u8 num_accel;
236 	u8 num_logical_accel;
237 	u8 num_engines;
238 	u32 num_hb_ctrs;
239 };
240 
241 /* CSR write macro */
242 #define ADF_CSR_WR(csr_base, csr_offset, val) \
243 	__raw_writel(val, csr_base + csr_offset)
244 
245 /* CSR read macro */
246 #define ADF_CSR_RD(csr_base, csr_offset) __raw_readl(csr_base + csr_offset)
247 
248 #define ADF_CFG_NUM_SERVICES	4
249 #define ADF_SRV_TYPE_BIT_LEN	3
250 #define ADF_SRV_TYPE_MASK	0x7
251 #define ADF_AE_ADMIN_THREAD	7
252 #define ADF_NUM_THREADS_PER_AE	8
253 #define ADF_NUM_PKE_STRAND	2
254 #define ADF_AE_STRAND0_THREAD	8
255 #define ADF_AE_STRAND1_THREAD	9
256 
257 #define GET_DEV(accel_dev) ((accel_dev)->accel_pci_dev.pci_dev->dev)
258 #define GET_BARS(accel_dev) ((accel_dev)->accel_pci_dev.pci_bars)
259 #define GET_HW_DATA(accel_dev) (accel_dev->hw_device)
260 #define GET_MAX_BANKS(accel_dev) (GET_HW_DATA(accel_dev)->num_banks)
261 #define GET_NUM_RINGS_PER_BANK(accel_dev) \
262 	GET_HW_DATA(accel_dev)->num_rings_per_bank
263 #define GET_SRV_TYPE(accel_dev, idx) \
264 	(((GET_HW_DATA(accel_dev)->ring_to_svc_map) >> (ADF_SRV_TYPE_BIT_LEN * (idx))) \
265 	& ADF_SRV_TYPE_MASK)
266 #define GET_MAX_ACCELENGINES(accel_dev) (GET_HW_DATA(accel_dev)->num_engines)
267 #define GET_CSR_OPS(accel_dev) (&(accel_dev)->hw_device->csr_ops)
268 #define GET_PFVF_OPS(accel_dev) (&(accel_dev)->hw_device->pfvf_ops)
269 #define GET_DC_OPS(accel_dev) (&(accel_dev)->hw_device->dc_ops)
270 #define accel_to_pci_dev(accel_ptr) accel_ptr->accel_pci_dev.pci_dev
271 
272 struct adf_admin_comms;
273 struct icp_qat_fw_loader_handle;
274 struct adf_fw_loader_data {
275 	struct icp_qat_fw_loader_handle *fw_loader;
276 	const struct firmware *uof_fw;
277 	const struct firmware *mmp_fw;
278 };
279 
280 struct adf_accel_vf_info {
281 	struct adf_accel_dev *accel_dev;
282 	struct mutex pf2vf_lock; /* protect CSR access for PF2VF messages */
283 	struct ratelimit_state vf2pf_ratelimit;
284 	u32 vf_nr;
285 	bool init;
286 	u8 vf_compat_ver;
287 };
288 
289 struct adf_dc_data {
290 	u8 *ovf_buff;
291 	size_t ovf_buff_sz;
292 	dma_addr_t ovf_buff_p;
293 };
294 
295 struct adf_accel_dev {
296 	struct adf_etr_data *transport;
297 	struct adf_hw_device_data *hw_device;
298 	struct adf_cfg_device_data *cfg;
299 	struct adf_fw_loader_data *fw_loader;
300 	struct adf_admin_comms *admin;
301 	struct adf_dc_data *dc_data;
302 	struct list_head crypto_list;
303 	struct list_head compression_list;
304 	unsigned long status;
305 	atomic_t ref_count;
306 	struct dentry *debugfs_dir;
307 	struct dentry *fw_cntr_dbgfile;
308 	struct list_head list;
309 	struct module *owner;
310 	struct adf_accel_pci accel_pci_dev;
311 	struct adf_timer *timer;
312 	struct adf_heartbeat *heartbeat;
313 	union {
314 		struct {
315 			/* protects VF2PF interrupts access */
316 			spinlock_t vf2pf_ints_lock;
317 			/* vf_info is non-zero when SR-IOV is init'ed */
318 			struct adf_accel_vf_info *vf_info;
319 		} pf;
320 		struct {
321 			bool irq_enabled;
322 			char irq_name[ADF_MAX_MSIX_VECTOR_NAME];
323 			struct tasklet_struct pf2vf_bh_tasklet;
324 			struct mutex vf2pf_lock; /* protect CSR access */
325 			struct completion msg_received;
326 			struct pfvf_message response; /* temp field holding pf2vf response */
327 			u8 pf_compat_ver;
328 		} vf;
329 	};
330 	struct mutex state_lock; /* protect state of the device */
331 	bool is_vf;
332 	u32 accel_id;
333 };
334 #endif
335