1 /* 2 * Copyright (C) 2017 Marvell 3 * 4 * Antoine Tenart <antoine.tenart@free-electrons.com> 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without any 8 * warranty of any kind, whether express or implied. 9 */ 10 11 #ifndef __SAFEXCEL_H__ 12 #define __SAFEXCEL_H__ 13 14 #include <crypto/algapi.h> 15 #include <crypto/internal/hash.h> 16 #include <crypto/skcipher.h> 17 18 #define EIP197_HIA_VERSION_LE 0xca35 19 #define EIP197_HIA_VERSION_BE 0x35ca 20 21 /* Static configuration */ 22 #define EIP197_DEFAULT_RING_SIZE 400 23 #define EIP197_MAX_TOKENS 5 24 #define EIP197_MAX_RINGS 4 25 #define EIP197_FETCH_COUNT 1 26 #define EIP197_MAX_BATCH_SZ 64 27 28 #define EIP197_GFP_FLAGS(base) ((base).flags & CRYPTO_TFM_REQ_MAY_SLEEP ? \ 29 GFP_KERNEL : GFP_ATOMIC) 30 31 /* Register base offsets */ 32 #define EIP197_HIA_AIC(priv) ((priv)->base + (priv)->offsets.hia_aic) 33 #define EIP197_HIA_AIC_G(priv) ((priv)->base + (priv)->offsets.hia_aic_g) 34 #define EIP197_HIA_AIC_R(priv) ((priv)->base + (priv)->offsets.hia_aic_r) 35 #define EIP197_HIA_AIC_xDR(priv) ((priv)->base + (priv)->offsets.hia_aic_xdr) 36 #define EIP197_HIA_DFE(priv) ((priv)->base + (priv)->offsets.hia_dfe) 37 #define EIP197_HIA_DFE_THR(priv) ((priv)->base + (priv)->offsets.hia_dfe_thr) 38 #define EIP197_HIA_DSE(priv) ((priv)->base + (priv)->offsets.hia_dse) 39 #define EIP197_HIA_DSE_THR(priv) ((priv)->base + (priv)->offsets.hia_dse_thr) 40 #define EIP197_HIA_GEN_CFG(priv) ((priv)->base + (priv)->offsets.hia_gen_cfg) 41 #define EIP197_PE(priv) ((priv)->base + (priv)->offsets.pe) 42 43 /* EIP197 base offsets */ 44 #define EIP197_HIA_AIC_BASE 0x90000 45 #define EIP197_HIA_AIC_G_BASE 0x90000 46 #define EIP197_HIA_AIC_R_BASE 0x90800 47 #define EIP197_HIA_AIC_xDR_BASE 0x80000 48 #define EIP197_HIA_DFE_BASE 0x8c000 49 #define EIP197_HIA_DFE_THR_BASE 0x8c040 50 #define EIP197_HIA_DSE_BASE 0x8d000 51 #define EIP197_HIA_DSE_THR_BASE 0x8d040 52 #define EIP197_HIA_GEN_CFG_BASE 0xf0000 53 #define EIP197_PE_BASE 0xa0000 54 55 /* EIP97 base offsets */ 56 #define EIP97_HIA_AIC_BASE 0x0 57 #define EIP97_HIA_AIC_G_BASE 0x0 58 #define EIP97_HIA_AIC_R_BASE 0x0 59 #define EIP97_HIA_AIC_xDR_BASE 0x0 60 #define EIP97_HIA_DFE_BASE 0xf000 61 #define EIP97_HIA_DFE_THR_BASE 0xf200 62 #define EIP97_HIA_DSE_BASE 0xf400 63 #define EIP97_HIA_DSE_THR_BASE 0xf600 64 #define EIP97_HIA_GEN_CFG_BASE 0x10000 65 #define EIP97_PE_BASE 0x10000 66 67 /* CDR/RDR register offsets */ 68 #define EIP197_HIA_xDR_OFF(priv, r) (EIP197_HIA_AIC_xDR(priv) + (r) * 0x1000) 69 #define EIP197_HIA_CDR(priv, r) (EIP197_HIA_xDR_OFF(priv, r)) 70 #define EIP197_HIA_RDR(priv, r) (EIP197_HIA_xDR_OFF(priv, r) + 0x800) 71 #define EIP197_HIA_xDR_RING_BASE_ADDR_LO 0x0000 72 #define EIP197_HIA_xDR_RING_BASE_ADDR_HI 0x0004 73 #define EIP197_HIA_xDR_RING_SIZE 0x0018 74 #define EIP197_HIA_xDR_DESC_SIZE 0x001c 75 #define EIP197_HIA_xDR_CFG 0x0020 76 #define EIP197_HIA_xDR_DMA_CFG 0x0024 77 #define EIP197_HIA_xDR_THRESH 0x0028 78 #define EIP197_HIA_xDR_PREP_COUNT 0x002c 79 #define EIP197_HIA_xDR_PROC_COUNT 0x0030 80 #define EIP197_HIA_xDR_PREP_PNTR 0x0034 81 #define EIP197_HIA_xDR_PROC_PNTR 0x0038 82 #define EIP197_HIA_xDR_STAT 0x003c 83 84 /* register offsets */ 85 #define EIP197_HIA_DFE_CFG 0x0000 86 #define EIP197_HIA_DFE_THR_CTRL 0x0000 87 #define EIP197_HIA_DFE_THR_STAT 0x0004 88 #define EIP197_HIA_DSE_CFG 0x0000 89 #define EIP197_HIA_DSE_THR_CTRL 0x0000 90 #define EIP197_HIA_DSE_THR_STAT 0x0004 91 #define EIP197_HIA_RA_PE_CTRL 0x0010 92 #define EIP197_HIA_RA_PE_STAT 0x0014 93 #define EIP197_HIA_AIC_R_OFF(r) ((r) * 0x1000) 94 #define EIP197_HIA_AIC_R_ENABLE_CTRL(r) (0xe008 - EIP197_HIA_AIC_R_OFF(r)) 95 #define EIP197_HIA_AIC_R_ENABLED_STAT(r) (0xe010 - EIP197_HIA_AIC_R_OFF(r)) 96 #define EIP197_HIA_AIC_R_ACK(r) (0xe010 - EIP197_HIA_AIC_R_OFF(r)) 97 #define EIP197_HIA_AIC_R_ENABLE_CLR(r) (0xe014 - EIP197_HIA_AIC_R_OFF(r)) 98 #define EIP197_HIA_AIC_G_ENABLE_CTRL 0xf808 99 #define EIP197_HIA_AIC_G_ENABLED_STAT 0xf810 100 #define EIP197_HIA_AIC_G_ACK 0xf810 101 #define EIP197_HIA_MST_CTRL 0xfff4 102 #define EIP197_HIA_OPTIONS 0xfff8 103 #define EIP197_HIA_VERSION 0xfffc 104 #define EIP197_PE_IN_DBUF_THRES 0x0000 105 #define EIP197_PE_IN_TBUF_THRES 0x0100 106 #define EIP197_PE_ICE_SCRATCH_RAM 0x0800 107 #define EIP197_PE_ICE_PUE_CTRL 0x0c80 108 #define EIP197_PE_ICE_SCRATCH_CTRL 0x0d04 109 #define EIP197_PE_ICE_FPP_CTRL 0x0d80 110 #define EIP197_PE_ICE_RAM_CTRL 0x0ff0 111 #define EIP197_PE_EIP96_FUNCTION_EN 0x1004 112 #define EIP197_PE_EIP96_CONTEXT_CTRL 0x1008 113 #define EIP197_PE_EIP96_CONTEXT_STAT 0x100c 114 #define EIP197_PE_OUT_DBUF_THRES 0x1c00 115 #define EIP197_PE_OUT_TBUF_THRES 0x1d00 116 #define EIP197_MST_CTRL 0xfff4 117 118 /* EIP197-specific registers, no indirection */ 119 #define EIP197_CLASSIFICATION_RAMS 0xe0000 120 #define EIP197_TRC_CTRL 0xf0800 121 #define EIP197_TRC_LASTRES 0xf0804 122 #define EIP197_TRC_REGINDEX 0xf0808 123 #define EIP197_TRC_PARAMS 0xf0820 124 #define EIP197_TRC_FREECHAIN 0xf0824 125 #define EIP197_TRC_PARAMS2 0xf0828 126 #define EIP197_TRC_ECCCTRL 0xf0830 127 #define EIP197_TRC_ECCSTAT 0xf0834 128 #define EIP197_TRC_ECCADMINSTAT 0xf0838 129 #define EIP197_TRC_ECCDATASTAT 0xf083c 130 #define EIP197_TRC_ECCDATA 0xf0840 131 #define EIP197_CS_RAM_CTRL 0xf7ff0 132 133 /* EIP197_HIA_xDR_DESC_SIZE */ 134 #define EIP197_xDR_DESC_MODE_64BIT BIT(31) 135 136 /* EIP197_HIA_xDR_DMA_CFG */ 137 #define EIP197_HIA_xDR_WR_RES_BUF BIT(22) 138 #define EIP197_HIA_xDR_WR_CTRL_BUG BIT(23) 139 #define EIP197_HIA_xDR_WR_OWN_BUF BIT(24) 140 #define EIP197_HIA_xDR_CFG_WR_CACHE(n) (((n) & 0x7) << 25) 141 #define EIP197_HIA_xDR_CFG_RD_CACHE(n) (((n) & 0x7) << 29) 142 143 /* EIP197_HIA_CDR_THRESH */ 144 #define EIP197_HIA_CDR_THRESH_PROC_PKT(n) (n) 145 #define EIP197_HIA_CDR_THRESH_PROC_MODE BIT(22) 146 #define EIP197_HIA_CDR_THRESH_PKT_MODE BIT(23) 147 #define EIP197_HIA_CDR_THRESH_TIMEOUT(n) ((n) << 24) /* x256 clk cycles */ 148 149 /* EIP197_HIA_RDR_THRESH */ 150 #define EIP197_HIA_RDR_THRESH_PROC_PKT(n) (n) 151 #define EIP197_HIA_RDR_THRESH_PKT_MODE BIT(23) 152 #define EIP197_HIA_RDR_THRESH_TIMEOUT(n) ((n) << 24) /* x256 clk cycles */ 153 154 /* EIP197_HIA_xDR_PREP_COUNT */ 155 #define EIP197_xDR_PREP_CLR_COUNT BIT(31) 156 157 /* EIP197_HIA_xDR_PROC_COUNT */ 158 #define EIP197_xDR_PROC_xD_PKT_OFFSET 24 159 #define EIP197_xDR_PROC_xD_PKT_MASK GENMASK(6, 0) 160 #define EIP197_xDR_PROC_xD_COUNT(n) ((n) << 2) 161 #define EIP197_xDR_PROC_xD_PKT(n) ((n) << 24) 162 #define EIP197_xDR_PROC_CLR_COUNT BIT(31) 163 164 /* EIP197_HIA_xDR_STAT */ 165 #define EIP197_xDR_DMA_ERR BIT(0) 166 #define EIP197_xDR_PREP_CMD_THRES BIT(1) 167 #define EIP197_xDR_ERR BIT(2) 168 #define EIP197_xDR_THRESH BIT(4) 169 #define EIP197_xDR_TIMEOUT BIT(5) 170 171 #define EIP197_HIA_RA_PE_CTRL_RESET BIT(31) 172 #define EIP197_HIA_RA_PE_CTRL_EN BIT(30) 173 174 /* EIP197_HIA_AIC_R_ENABLE_CTRL */ 175 #define EIP197_CDR_IRQ(n) BIT((n) * 2) 176 #define EIP197_RDR_IRQ(n) BIT((n) * 2 + 1) 177 178 /* EIP197_HIA_DFE/DSE_CFG */ 179 #define EIP197_HIA_DxE_CFG_MIN_DATA_SIZE(n) ((n) << 0) 180 #define EIP197_HIA_DxE_CFG_DATA_CACHE_CTRL(n) (((n) & 0x7) << 4) 181 #define EIP197_HIA_DxE_CFG_MAX_DATA_SIZE(n) ((n) << 8) 182 #define EIP197_HIA_DSE_CFG_ALLWAYS_BUFFERABLE GENMASK(15, 14) 183 #define EIP197_HIA_DxE_CFG_MIN_CTRL_SIZE(n) ((n) << 16) 184 #define EIP197_HIA_DxE_CFG_CTRL_CACHE_CTRL(n) (((n) & 0x7) << 20) 185 #define EIP197_HIA_DxE_CFG_MAX_CTRL_SIZE(n) ((n) << 24) 186 #define EIP197_HIA_DFE_CFG_DIS_DEBUG (BIT(31) | BIT(29)) 187 #define EIP197_HIA_DSE_CFG_EN_SINGLE_WR BIT(29) 188 #define EIP197_HIA_DSE_CFG_DIS_DEBUG BIT(31) 189 190 /* EIP197_HIA_DFE/DSE_THR_CTRL */ 191 #define EIP197_DxE_THR_CTRL_EN BIT(30) 192 #define EIP197_DxE_THR_CTRL_RESET_PE BIT(31) 193 194 /* EIP197_HIA_AIC_G_ENABLED_STAT */ 195 #define EIP197_G_IRQ_DFE(n) BIT((n) << 1) 196 #define EIP197_G_IRQ_DSE(n) BIT(((n) << 1) + 1) 197 #define EIP197_G_IRQ_RING BIT(16) 198 #define EIP197_G_IRQ_PE(n) BIT((n) + 20) 199 200 /* EIP197_HIA_MST_CTRL */ 201 #define RD_CACHE_3BITS 0x5 202 #define WR_CACHE_3BITS 0x3 203 #define RD_CACHE_4BITS (RD_CACHE_3BITS << 1 | BIT(0)) 204 #define WR_CACHE_4BITS (WR_CACHE_3BITS << 1 | BIT(0)) 205 #define EIP197_MST_CTRL_RD_CACHE(n) (((n) & 0xf) << 0) 206 #define EIP197_MST_CTRL_WD_CACHE(n) (((n) & 0xf) << 4) 207 #define EIP197_MST_CTRL_BYTE_SWAP BIT(24) 208 #define EIP197_MST_CTRL_NO_BYTE_SWAP BIT(25) 209 210 /* EIP197_PE_IN_DBUF/TBUF_THRES */ 211 #define EIP197_PE_IN_xBUF_THRES_MIN(n) ((n) << 8) 212 #define EIP197_PE_IN_xBUF_THRES_MAX(n) ((n) << 12) 213 214 /* EIP197_PE_OUT_DBUF_THRES */ 215 #define EIP197_PE_OUT_DBUF_THRES_MIN(n) ((n) << 0) 216 #define EIP197_PE_OUT_DBUF_THRES_MAX(n) ((n) << 4) 217 218 /* EIP197_PE_ICE_SCRATCH_CTRL */ 219 #define EIP197_PE_ICE_SCRATCH_CTRL_CHANGE_TIMER BIT(2) 220 #define EIP197_PE_ICE_SCRATCH_CTRL_TIMER_EN BIT(3) 221 #define EIP197_PE_ICE_SCRATCH_CTRL_CHANGE_ACCESS BIT(24) 222 #define EIP197_PE_ICE_SCRATCH_CTRL_SCRATCH_ACCESS BIT(25) 223 224 /* EIP197_PE_ICE_SCRATCH_RAM */ 225 #define EIP197_NUM_OF_SCRATCH_BLOCKS 32 226 227 /* EIP197_PE_ICE_PUE/FPP_CTRL */ 228 #define EIP197_PE_ICE_x_CTRL_SW_RESET BIT(0) 229 #define EIP197_PE_ICE_x_CTRL_CLR_ECC_NON_CORR BIT(14) 230 #define EIP197_PE_ICE_x_CTRL_CLR_ECC_CORR BIT(15) 231 232 /* EIP197_PE_ICE_RAM_CTRL */ 233 #define EIP197_PE_ICE_RAM_CTRL_PUE_PROG_EN BIT(0) 234 #define EIP197_PE_ICE_RAM_CTRL_FPP_PROG_EN BIT(1) 235 236 /* EIP197_PE_EIP96_FUNCTION_EN */ 237 #define EIP197_FUNCTION_RSVD (BIT(6) | BIT(15) | BIT(20) | BIT(23)) 238 #define EIP197_PROTOCOL_HASH_ONLY BIT(0) 239 #define EIP197_PROTOCOL_ENCRYPT_ONLY BIT(1) 240 #define EIP197_PROTOCOL_HASH_ENCRYPT BIT(2) 241 #define EIP197_PROTOCOL_HASH_DECRYPT BIT(3) 242 #define EIP197_PROTOCOL_ENCRYPT_HASH BIT(4) 243 #define EIP197_PROTOCOL_DECRYPT_HASH BIT(5) 244 #define EIP197_ALG_ARC4 BIT(7) 245 #define EIP197_ALG_AES_ECB BIT(8) 246 #define EIP197_ALG_AES_CBC BIT(9) 247 #define EIP197_ALG_AES_CTR_ICM BIT(10) 248 #define EIP197_ALG_AES_OFB BIT(11) 249 #define EIP197_ALG_AES_CFB BIT(12) 250 #define EIP197_ALG_DES_ECB BIT(13) 251 #define EIP197_ALG_DES_CBC BIT(14) 252 #define EIP197_ALG_DES_OFB BIT(16) 253 #define EIP197_ALG_DES_CFB BIT(17) 254 #define EIP197_ALG_3DES_ECB BIT(18) 255 #define EIP197_ALG_3DES_CBC BIT(19) 256 #define EIP197_ALG_3DES_OFB BIT(21) 257 #define EIP197_ALG_3DES_CFB BIT(22) 258 #define EIP197_ALG_MD5 BIT(24) 259 #define EIP197_ALG_HMAC_MD5 BIT(25) 260 #define EIP197_ALG_SHA1 BIT(26) 261 #define EIP197_ALG_HMAC_SHA1 BIT(27) 262 #define EIP197_ALG_SHA2 BIT(28) 263 #define EIP197_ALG_HMAC_SHA2 BIT(29) 264 #define EIP197_ALG_AES_XCBC_MAC BIT(30) 265 #define EIP197_ALG_GCM_HASH BIT(31) 266 267 /* EIP197_PE_EIP96_CONTEXT_CTRL */ 268 #define EIP197_CONTEXT_SIZE(n) (n) 269 #define EIP197_ADDRESS_MODE BIT(8) 270 #define EIP197_CONTROL_MODE BIT(9) 271 272 /* Context Control */ 273 struct safexcel_context_record { 274 u32 control0; 275 u32 control1; 276 277 __le32 data[12]; 278 } __packed; 279 280 /* control0 */ 281 #define CONTEXT_CONTROL_TYPE_NULL_OUT 0x0 282 #define CONTEXT_CONTROL_TYPE_NULL_IN 0x1 283 #define CONTEXT_CONTROL_TYPE_HASH_OUT 0x2 284 #define CONTEXT_CONTROL_TYPE_HASH_IN 0x3 285 #define CONTEXT_CONTROL_TYPE_CRYPTO_OUT 0x4 286 #define CONTEXT_CONTROL_TYPE_CRYPTO_IN 0x5 287 #define CONTEXT_CONTROL_TYPE_ENCRYPT_HASH_OUT 0x6 288 #define CONTEXT_CONTROL_TYPE_DECRYPT_HASH_IN 0x7 289 #define CONTEXT_CONTROL_TYPE_HASH_ENCRYPT_OUT 0x14 290 #define CONTEXT_CONTROL_TYPE_HASH_DECRYPT_OUT 0x15 291 #define CONTEXT_CONTROL_RESTART_HASH BIT(4) 292 #define CONTEXT_CONTROL_NO_FINISH_HASH BIT(5) 293 #define CONTEXT_CONTROL_SIZE(n) ((n) << 8) 294 #define CONTEXT_CONTROL_KEY_EN BIT(16) 295 #define CONTEXT_CONTROL_CRYPTO_ALG_AES128 (0x5 << 17) 296 #define CONTEXT_CONTROL_CRYPTO_ALG_AES192 (0x6 << 17) 297 #define CONTEXT_CONTROL_CRYPTO_ALG_AES256 (0x7 << 17) 298 #define CONTEXT_CONTROL_DIGEST_PRECOMPUTED (0x1 << 21) 299 #define CONTEXT_CONTROL_DIGEST_HMAC (0x3 << 21) 300 #define CONTEXT_CONTROL_CRYPTO_ALG_SHA1 (0x2 << 23) 301 #define CONTEXT_CONTROL_CRYPTO_ALG_SHA224 (0x4 << 23) 302 #define CONTEXT_CONTROL_CRYPTO_ALG_SHA256 (0x3 << 23) 303 #define CONTEXT_CONTROL_INV_FR (0x5 << 24) 304 #define CONTEXT_CONTROL_INV_TR (0x6 << 24) 305 306 /* control1 */ 307 #define CONTEXT_CONTROL_CRYPTO_MODE_ECB (0 << 0) 308 #define CONTEXT_CONTROL_CRYPTO_MODE_CBC (1 << 0) 309 #define CONTEXT_CONTROL_IV0 BIT(5) 310 #define CONTEXT_CONTROL_IV1 BIT(6) 311 #define CONTEXT_CONTROL_IV2 BIT(7) 312 #define CONTEXT_CONTROL_IV3 BIT(8) 313 #define CONTEXT_CONTROL_DIGEST_CNT BIT(9) 314 #define CONTEXT_CONTROL_COUNTER_MODE BIT(10) 315 #define CONTEXT_CONTROL_HASH_STORE BIT(19) 316 317 /* EIP197_CS_RAM_CTRL */ 318 #define EIP197_TRC_ENABLE_0 BIT(4) 319 #define EIP197_TRC_ENABLE_1 BIT(5) 320 #define EIP197_TRC_ENABLE_2 BIT(6) 321 #define EIP197_TRC_ENABLE_MASK GENMASK(6, 4) 322 323 /* EIP197_TRC_PARAMS */ 324 #define EIP197_TRC_PARAMS_SW_RESET BIT(0) 325 #define EIP197_TRC_PARAMS_DATA_ACCESS BIT(2) 326 #define EIP197_TRC_PARAMS_HTABLE_SZ(x) ((x) << 4) 327 #define EIP197_TRC_PARAMS_BLK_TIMER_SPEED(x) ((x) << 10) 328 #define EIP197_TRC_PARAMS_RC_SZ_LARGE(n) ((n) << 18) 329 330 /* EIP197_TRC_FREECHAIN */ 331 #define EIP197_TRC_FREECHAIN_HEAD_PTR(p) (p) 332 #define EIP197_TRC_FREECHAIN_TAIL_PTR(p) ((p) << 16) 333 334 /* EIP197_TRC_PARAMS2 */ 335 #define EIP197_TRC_PARAMS2_HTABLE_PTR(p) (p) 336 #define EIP197_TRC_PARAMS2_RC_SZ_SMALL(n) ((n) << 18) 337 338 /* Cache helpers */ 339 #define EIP197_CS_RC_MAX 52 340 #define EIP197_CS_RC_SIZE (4 * sizeof(u32)) 341 #define EIP197_CS_RC_NEXT(x) (x) 342 #define EIP197_CS_RC_PREV(x) ((x) << 10) 343 #define EIP197_RC_NULL 0x3ff 344 #define EIP197_CS_TRC_REC_WC 59 345 #define EIP197_CS_TRC_LG_REC_WC 73 346 347 /* Result data */ 348 struct result_data_desc { 349 u32 packet_length:17; 350 u32 error_code:15; 351 352 u8 bypass_length:4; 353 u8 e15:1; 354 u16 rsvd0; 355 u8 hash_bytes:1; 356 u8 hash_length:6; 357 u8 generic_bytes:1; 358 u8 checksum:1; 359 u8 next_header:1; 360 u8 length:1; 361 362 u16 application_id; 363 u16 rsvd1; 364 365 u32 rsvd2; 366 } __packed; 367 368 369 /* Basic Result Descriptor format */ 370 struct safexcel_result_desc { 371 u32 particle_size:17; 372 u8 rsvd0:3; 373 u8 descriptor_overflow:1; 374 u8 buffer_overflow:1; 375 u8 last_seg:1; 376 u8 first_seg:1; 377 u16 result_size:8; 378 379 u32 rsvd1; 380 381 u32 data_lo; 382 u32 data_hi; 383 384 struct result_data_desc result_data; 385 } __packed; 386 387 struct safexcel_token { 388 u32 packet_length:17; 389 u8 stat:2; 390 u16 instructions:9; 391 u8 opcode:4; 392 } __packed; 393 394 #define EIP197_TOKEN_STAT_LAST_HASH BIT(0) 395 #define EIP197_TOKEN_STAT_LAST_PACKET BIT(1) 396 #define EIP197_TOKEN_OPCODE_DIRECTION 0x0 397 #define EIP197_TOKEN_OPCODE_INSERT 0x2 398 #define EIP197_TOKEN_OPCODE_NOOP EIP197_TOKEN_OPCODE_INSERT 399 #define EIP197_TOKEN_OPCODE_BYPASS GENMASK(3, 0) 400 401 static inline void eip197_noop_token(struct safexcel_token *token) 402 { 403 token->opcode = EIP197_TOKEN_OPCODE_NOOP; 404 token->packet_length = BIT(2); 405 } 406 407 /* Instructions */ 408 #define EIP197_TOKEN_INS_INSERT_HASH_DIGEST 0x1c 409 #define EIP197_TOKEN_INS_TYPE_OUTPUT BIT(5) 410 #define EIP197_TOKEN_INS_TYPE_HASH BIT(6) 411 #define EIP197_TOKEN_INS_TYPE_CRYTO BIT(7) 412 #define EIP197_TOKEN_INS_LAST BIT(8) 413 414 /* Processing Engine Control Data */ 415 struct safexcel_control_data_desc { 416 u32 packet_length:17; 417 u16 options:13; 418 u8 type:2; 419 420 u16 application_id; 421 u16 rsvd; 422 423 u8 refresh:2; 424 u32 context_lo:30; 425 u32 context_hi; 426 427 u32 control0; 428 u32 control1; 429 430 u32 token[EIP197_MAX_TOKENS]; 431 } __packed; 432 433 #define EIP197_OPTION_MAGIC_VALUE BIT(0) 434 #define EIP197_OPTION_64BIT_CTX BIT(1) 435 #define EIP197_OPTION_CTX_CTRL_IN_CMD BIT(8) 436 #define EIP197_OPTION_4_TOKEN_IV_CMD GENMASK(11, 9) 437 438 #define EIP197_TYPE_EXTENDED 0x3 439 440 /* Basic Command Descriptor format */ 441 struct safexcel_command_desc { 442 u32 particle_size:17; 443 u8 rsvd0:5; 444 u8 last_seg:1; 445 u8 first_seg:1; 446 u16 additional_cdata_size:8; 447 448 u32 rsvd1; 449 450 u32 data_lo; 451 u32 data_hi; 452 453 struct safexcel_control_data_desc control_data; 454 } __packed; 455 456 /* 457 * Internal structures & functions 458 */ 459 460 enum eip197_fw { 461 FW_IFPP = 0, 462 FW_IPUE, 463 FW_NB 464 }; 465 466 struct safexcel_ring { 467 void *base; 468 void *base_end; 469 dma_addr_t base_dma; 470 471 /* write and read pointers */ 472 void *write; 473 void *read; 474 475 /* number of elements used in the ring */ 476 unsigned nr; 477 unsigned offset; 478 }; 479 480 enum safexcel_alg_type { 481 SAFEXCEL_ALG_TYPE_SKCIPHER, 482 SAFEXCEL_ALG_TYPE_AHASH, 483 }; 484 485 struct safexcel_request { 486 struct list_head list; 487 struct crypto_async_request *req; 488 }; 489 490 struct safexcel_config { 491 u32 rings; 492 493 u32 cd_size; 494 u32 cd_offset; 495 496 u32 rd_size; 497 u32 rd_offset; 498 }; 499 500 struct safexcel_work_data { 501 struct work_struct work; 502 struct safexcel_crypto_priv *priv; 503 int ring; 504 }; 505 506 enum safexcel_eip_version { 507 EIP97, 508 EIP197, 509 }; 510 511 struct safexcel_register_offsets { 512 u32 hia_aic; 513 u32 hia_aic_g; 514 u32 hia_aic_r; 515 u32 hia_aic_xdr; 516 u32 hia_dfe; 517 u32 hia_dfe_thr; 518 u32 hia_dse; 519 u32 hia_dse_thr; 520 u32 hia_gen_cfg; 521 u32 pe; 522 }; 523 524 struct safexcel_crypto_priv { 525 void __iomem *base; 526 struct device *dev; 527 struct clk *clk; 528 struct safexcel_config config; 529 530 enum safexcel_eip_version version; 531 struct safexcel_register_offsets offsets; 532 533 /* context DMA pool */ 534 struct dma_pool *context_pool; 535 536 atomic_t ring_used; 537 538 struct { 539 spinlock_t lock; 540 spinlock_t egress_lock; 541 542 struct list_head list; 543 struct workqueue_struct *workqueue; 544 struct safexcel_work_data work_data; 545 546 /* command/result rings */ 547 struct safexcel_ring cdr; 548 struct safexcel_ring rdr; 549 550 /* queue */ 551 struct crypto_queue queue; 552 spinlock_t queue_lock; 553 554 /* Number of requests in the engine that needs the threshold 555 * interrupt to be set up. 556 */ 557 int requests_left; 558 559 /* The ring is currently handling at least one request */ 560 bool busy; 561 562 /* Store for current requests when bailing out of the dequeueing 563 * function when no enough resources are available. 564 */ 565 struct crypto_async_request *req; 566 struct crypto_async_request *backlog; 567 } ring[EIP197_MAX_RINGS]; 568 }; 569 570 struct safexcel_context { 571 int (*send)(struct crypto_async_request *req, int ring, 572 struct safexcel_request *request, int *commands, 573 int *results); 574 int (*handle_result)(struct safexcel_crypto_priv *priv, int ring, 575 struct crypto_async_request *req, bool *complete, 576 int *ret); 577 struct safexcel_context_record *ctxr; 578 dma_addr_t ctxr_dma; 579 580 int ring; 581 bool needs_inv; 582 bool exit_inv; 583 584 /* Used for ahash requests */ 585 dma_addr_t result_dma; 586 void *cache; 587 dma_addr_t cache_dma; 588 unsigned int cache_sz; 589 }; 590 591 /* 592 * Template structure to describe the algorithms in order to register them. 593 * It also has the purpose to contain our private structure and is actually 594 * the only way I know in this framework to avoid having global pointers... 595 */ 596 struct safexcel_alg_template { 597 struct safexcel_crypto_priv *priv; 598 enum safexcel_alg_type type; 599 union { 600 struct skcipher_alg skcipher; 601 struct ahash_alg ahash; 602 } alg; 603 }; 604 605 struct safexcel_inv_result { 606 struct completion completion; 607 int error; 608 }; 609 610 void safexcel_dequeue(struct safexcel_crypto_priv *priv, int ring); 611 void safexcel_complete(struct safexcel_crypto_priv *priv, int ring); 612 void safexcel_free_context(struct safexcel_crypto_priv *priv, 613 struct crypto_async_request *req, 614 int result_sz); 615 int safexcel_invalidate_cache(struct crypto_async_request *async, 616 struct safexcel_crypto_priv *priv, 617 dma_addr_t ctxr_dma, int ring, 618 struct safexcel_request *request); 619 int safexcel_init_ring_descriptors(struct safexcel_crypto_priv *priv, 620 struct safexcel_ring *cdr, 621 struct safexcel_ring *rdr); 622 int safexcel_select_ring(struct safexcel_crypto_priv *priv); 623 void *safexcel_ring_next_rptr(struct safexcel_crypto_priv *priv, 624 struct safexcel_ring *ring); 625 void safexcel_ring_rollback_wptr(struct safexcel_crypto_priv *priv, 626 struct safexcel_ring *ring); 627 struct safexcel_command_desc *safexcel_add_cdesc(struct safexcel_crypto_priv *priv, 628 int ring_id, 629 bool first, bool last, 630 dma_addr_t data, u32 len, 631 u32 full_data_len, 632 dma_addr_t context); 633 struct safexcel_result_desc *safexcel_add_rdesc(struct safexcel_crypto_priv *priv, 634 int ring_id, 635 bool first, bool last, 636 dma_addr_t data, u32 len); 637 void safexcel_inv_complete(struct crypto_async_request *req, int error); 638 639 /* available algorithms */ 640 extern struct safexcel_alg_template safexcel_alg_ecb_aes; 641 extern struct safexcel_alg_template safexcel_alg_cbc_aes; 642 extern struct safexcel_alg_template safexcel_alg_sha1; 643 extern struct safexcel_alg_template safexcel_alg_sha224; 644 extern struct safexcel_alg_template safexcel_alg_sha256; 645 extern struct safexcel_alg_template safexcel_alg_hmac_sha1; 646 647 #endif 648