1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2017 Marvell 4 * 5 * Antoine Tenart <antoine.tenart@free-electrons.com> 6 */ 7 8 #ifndef __SAFEXCEL_H__ 9 #define __SAFEXCEL_H__ 10 11 #include <crypto/aead.h> 12 #include <crypto/algapi.h> 13 #include <crypto/internal/hash.h> 14 #include <crypto/sha.h> 15 #include <crypto/skcipher.h> 16 17 #define EIP197_HIA_VERSION_LE 0xca35 18 #define EIP197_HIA_VERSION_BE 0x35ca 19 20 /* Static configuration */ 21 #define EIP197_DEFAULT_RING_SIZE 400 22 #define EIP197_MAX_TOKENS 8 23 #define EIP197_MAX_RINGS 4 24 #define EIP197_FETCH_COUNT 1 25 #define EIP197_MAX_BATCH_SZ 64 26 27 #define EIP197_GFP_FLAGS(base) ((base).flags & CRYPTO_TFM_REQ_MAY_SLEEP ? \ 28 GFP_KERNEL : GFP_ATOMIC) 29 30 /* Custom on-stack requests (for invalidation) */ 31 #define EIP197_SKCIPHER_REQ_SIZE sizeof(struct skcipher_request) + \ 32 sizeof(struct safexcel_cipher_req) 33 #define EIP197_AHASH_REQ_SIZE sizeof(struct ahash_request) + \ 34 sizeof(struct safexcel_ahash_req) 35 #define EIP197_AEAD_REQ_SIZE sizeof(struct aead_request) + \ 36 sizeof(struct safexcel_cipher_req) 37 #define EIP197_REQUEST_ON_STACK(name, type, size) \ 38 char __##name##_desc[size] CRYPTO_MINALIGN_ATTR; \ 39 struct type##_request *name = (void *)__##name##_desc 40 41 /* Register base offsets */ 42 #define EIP197_HIA_AIC(priv) ((priv)->base + (priv)->offsets.hia_aic) 43 #define EIP197_HIA_AIC_G(priv) ((priv)->base + (priv)->offsets.hia_aic_g) 44 #define EIP197_HIA_AIC_R(priv) ((priv)->base + (priv)->offsets.hia_aic_r) 45 #define EIP197_HIA_AIC_xDR(priv) ((priv)->base + (priv)->offsets.hia_aic_xdr) 46 #define EIP197_HIA_DFE(priv) ((priv)->base + (priv)->offsets.hia_dfe) 47 #define EIP197_HIA_DFE_THR(priv) ((priv)->base + (priv)->offsets.hia_dfe_thr) 48 #define EIP197_HIA_DSE(priv) ((priv)->base + (priv)->offsets.hia_dse) 49 #define EIP197_HIA_DSE_THR(priv) ((priv)->base + (priv)->offsets.hia_dse_thr) 50 #define EIP197_HIA_GEN_CFG(priv) ((priv)->base + (priv)->offsets.hia_gen_cfg) 51 #define EIP197_PE(priv) ((priv)->base + (priv)->offsets.pe) 52 53 /* EIP197 base offsets */ 54 #define EIP197_HIA_AIC_BASE 0x90000 55 #define EIP197_HIA_AIC_G_BASE 0x90000 56 #define EIP197_HIA_AIC_R_BASE 0x90800 57 #define EIP197_HIA_AIC_xDR_BASE 0x80000 58 #define EIP197_HIA_DFE_BASE 0x8c000 59 #define EIP197_HIA_DFE_THR_BASE 0x8c040 60 #define EIP197_HIA_DSE_BASE 0x8d000 61 #define EIP197_HIA_DSE_THR_BASE 0x8d040 62 #define EIP197_HIA_GEN_CFG_BASE 0xf0000 63 #define EIP197_PE_BASE 0xa0000 64 65 /* EIP97 base offsets */ 66 #define EIP97_HIA_AIC_BASE 0x0 67 #define EIP97_HIA_AIC_G_BASE 0x0 68 #define EIP97_HIA_AIC_R_BASE 0x0 69 #define EIP97_HIA_AIC_xDR_BASE 0x0 70 #define EIP97_HIA_DFE_BASE 0xf000 71 #define EIP97_HIA_DFE_THR_BASE 0xf200 72 #define EIP97_HIA_DSE_BASE 0xf400 73 #define EIP97_HIA_DSE_THR_BASE 0xf600 74 #define EIP97_HIA_GEN_CFG_BASE 0x10000 75 #define EIP97_PE_BASE 0x10000 76 77 /* CDR/RDR register offsets */ 78 #define EIP197_HIA_xDR_OFF(priv, r) (EIP197_HIA_AIC_xDR(priv) + (r) * 0x1000) 79 #define EIP197_HIA_CDR(priv, r) (EIP197_HIA_xDR_OFF(priv, r)) 80 #define EIP197_HIA_RDR(priv, r) (EIP197_HIA_xDR_OFF(priv, r) + 0x800) 81 #define EIP197_HIA_xDR_RING_BASE_ADDR_LO 0x0000 82 #define EIP197_HIA_xDR_RING_BASE_ADDR_HI 0x0004 83 #define EIP197_HIA_xDR_RING_SIZE 0x0018 84 #define EIP197_HIA_xDR_DESC_SIZE 0x001c 85 #define EIP197_HIA_xDR_CFG 0x0020 86 #define EIP197_HIA_xDR_DMA_CFG 0x0024 87 #define EIP197_HIA_xDR_THRESH 0x0028 88 #define EIP197_HIA_xDR_PREP_COUNT 0x002c 89 #define EIP197_HIA_xDR_PROC_COUNT 0x0030 90 #define EIP197_HIA_xDR_PREP_PNTR 0x0034 91 #define EIP197_HIA_xDR_PROC_PNTR 0x0038 92 #define EIP197_HIA_xDR_STAT 0x003c 93 94 /* register offsets */ 95 #define EIP197_HIA_DFE_CFG(n) (0x0000 + (128 * (n))) 96 #define EIP197_HIA_DFE_THR_CTRL(n) (0x0000 + (128 * (n))) 97 #define EIP197_HIA_DFE_THR_STAT(n) (0x0004 + (128 * (n))) 98 #define EIP197_HIA_DSE_CFG(n) (0x0000 + (128 * (n))) 99 #define EIP197_HIA_DSE_THR_CTRL(n) (0x0000 + (128 * (n))) 100 #define EIP197_HIA_DSE_THR_STAT(n) (0x0004 + (128 * (n))) 101 #define EIP197_HIA_RA_PE_CTRL(n) (0x0010 + (8 * (n))) 102 #define EIP197_HIA_RA_PE_STAT 0x0014 103 #define EIP197_HIA_AIC_R_OFF(r) ((r) * 0x1000) 104 #define EIP197_HIA_AIC_R_ENABLE_CTRL(r) (0xe008 - EIP197_HIA_AIC_R_OFF(r)) 105 #define EIP197_HIA_AIC_R_ENABLED_STAT(r) (0xe010 - EIP197_HIA_AIC_R_OFF(r)) 106 #define EIP197_HIA_AIC_R_ACK(r) (0xe010 - EIP197_HIA_AIC_R_OFF(r)) 107 #define EIP197_HIA_AIC_R_ENABLE_CLR(r) (0xe014 - EIP197_HIA_AIC_R_OFF(r)) 108 #define EIP197_HIA_AIC_G_ENABLE_CTRL 0xf808 109 #define EIP197_HIA_AIC_G_ENABLED_STAT 0xf810 110 #define EIP197_HIA_AIC_G_ACK 0xf810 111 #define EIP197_HIA_MST_CTRL 0xfff4 112 #define EIP197_HIA_OPTIONS 0xfff8 113 #define EIP197_HIA_VERSION 0xfffc 114 #define EIP197_PE_IN_DBUF_THRES(n) (0x0000 + (0x2000 * (n))) 115 #define EIP197_PE_IN_TBUF_THRES(n) (0x0100 + (0x2000 * (n))) 116 #define EIP197_PE_ICE_SCRATCH_RAM(n) (0x0800 + (0x2000 * (n))) 117 #define EIP197_PE_ICE_PUE_CTRL(n) (0x0c80 + (0x2000 * (n))) 118 #define EIP197_PE_ICE_SCRATCH_CTRL(n) (0x0d04 + (0x2000 * (n))) 119 #define EIP197_PE_ICE_FPP_CTRL(n) (0x0d80 + (0x2000 * (n))) 120 #define EIP197_PE_ICE_RAM_CTRL(n) (0x0ff0 + (0x2000 * (n))) 121 #define EIP197_PE_EIP96_TOKEN_CTRL(n) (0x1000 + (0x2000 * (n))) 122 #define EIP197_PE_EIP96_FUNCTION_EN(n) (0x1004 + (0x2000 * (n))) 123 #define EIP197_PE_EIP96_CONTEXT_CTRL(n) (0x1008 + (0x2000 * (n))) 124 #define EIP197_PE_EIP96_CONTEXT_STAT(n) (0x100c + (0x2000 * (n))) 125 #define EIP197_PE_OUT_DBUF_THRES(n) (0x1c00 + (0x2000 * (n))) 126 #define EIP197_PE_OUT_TBUF_THRES(n) (0x1d00 + (0x2000 * (n))) 127 #define EIP197_MST_CTRL 0xfff4 128 129 /* EIP197-specific registers, no indirection */ 130 #define EIP197_CLASSIFICATION_RAMS 0xe0000 131 #define EIP197_TRC_CTRL 0xf0800 132 #define EIP197_TRC_LASTRES 0xf0804 133 #define EIP197_TRC_REGINDEX 0xf0808 134 #define EIP197_TRC_PARAMS 0xf0820 135 #define EIP197_TRC_FREECHAIN 0xf0824 136 #define EIP197_TRC_PARAMS2 0xf0828 137 #define EIP197_TRC_ECCCTRL 0xf0830 138 #define EIP197_TRC_ECCSTAT 0xf0834 139 #define EIP197_TRC_ECCADMINSTAT 0xf0838 140 #define EIP197_TRC_ECCDATASTAT 0xf083c 141 #define EIP197_TRC_ECCDATA 0xf0840 142 #define EIP197_CS_RAM_CTRL 0xf7ff0 143 144 /* EIP197_HIA_xDR_DESC_SIZE */ 145 #define EIP197_xDR_DESC_MODE_64BIT BIT(31) 146 147 /* EIP197_HIA_xDR_DMA_CFG */ 148 #define EIP197_HIA_xDR_WR_RES_BUF BIT(22) 149 #define EIP197_HIA_xDR_WR_CTRL_BUF BIT(23) 150 #define EIP197_HIA_xDR_WR_OWN_BUF BIT(24) 151 #define EIP197_HIA_xDR_CFG_WR_CACHE(n) (((n) & 0x7) << 25) 152 #define EIP197_HIA_xDR_CFG_RD_CACHE(n) (((n) & 0x7) << 29) 153 154 /* EIP197_HIA_CDR_THRESH */ 155 #define EIP197_HIA_CDR_THRESH_PROC_PKT(n) (n) 156 #define EIP197_HIA_CDR_THRESH_PROC_MODE BIT(22) 157 #define EIP197_HIA_CDR_THRESH_PKT_MODE BIT(23) 158 #define EIP197_HIA_CDR_THRESH_TIMEOUT(n) ((n) << 24) /* x256 clk cycles */ 159 160 /* EIP197_HIA_RDR_THRESH */ 161 #define EIP197_HIA_RDR_THRESH_PROC_PKT(n) (n) 162 #define EIP197_HIA_RDR_THRESH_PKT_MODE BIT(23) 163 #define EIP197_HIA_RDR_THRESH_TIMEOUT(n) ((n) << 24) /* x256 clk cycles */ 164 165 /* EIP197_HIA_xDR_PREP_COUNT */ 166 #define EIP197_xDR_PREP_CLR_COUNT BIT(31) 167 168 /* EIP197_HIA_xDR_PROC_COUNT */ 169 #define EIP197_xDR_PROC_xD_PKT_OFFSET 24 170 #define EIP197_xDR_PROC_xD_PKT_MASK GENMASK(6, 0) 171 #define EIP197_xDR_PROC_xD_COUNT(n) ((n) << 2) 172 #define EIP197_xDR_PROC_xD_PKT(n) ((n) << 24) 173 #define EIP197_xDR_PROC_CLR_COUNT BIT(31) 174 175 /* EIP197_HIA_xDR_STAT */ 176 #define EIP197_xDR_DMA_ERR BIT(0) 177 #define EIP197_xDR_PREP_CMD_THRES BIT(1) 178 #define EIP197_xDR_ERR BIT(2) 179 #define EIP197_xDR_THRESH BIT(4) 180 #define EIP197_xDR_TIMEOUT BIT(5) 181 182 #define EIP197_HIA_RA_PE_CTRL_RESET BIT(31) 183 #define EIP197_HIA_RA_PE_CTRL_EN BIT(30) 184 185 /* EIP197_HIA_OPTIONS */ 186 #define EIP197_N_PES_OFFSET 4 187 #define EIP197_N_PES_MASK GENMASK(4, 0) 188 #define EIP97_N_PES_MASK GENMASK(2, 0) 189 190 /* EIP197_HIA_AIC_R_ENABLE_CTRL */ 191 #define EIP197_CDR_IRQ(n) BIT((n) * 2) 192 #define EIP197_RDR_IRQ(n) BIT((n) * 2 + 1) 193 194 /* EIP197_HIA_DFE/DSE_CFG */ 195 #define EIP197_HIA_DxE_CFG_MIN_DATA_SIZE(n) ((n) << 0) 196 #define EIP197_HIA_DxE_CFG_DATA_CACHE_CTRL(n) (((n) & 0x7) << 4) 197 #define EIP197_HIA_DxE_CFG_MAX_DATA_SIZE(n) ((n) << 8) 198 #define EIP197_HIA_DSE_CFG_ALWAYS_BUFFERABLE GENMASK(15, 14) 199 #define EIP197_HIA_DxE_CFG_MIN_CTRL_SIZE(n) ((n) << 16) 200 #define EIP197_HIA_DxE_CFG_CTRL_CACHE_CTRL(n) (((n) & 0x7) << 20) 201 #define EIP197_HIA_DxE_CFG_MAX_CTRL_SIZE(n) ((n) << 24) 202 #define EIP197_HIA_DFE_CFG_DIS_DEBUG (BIT(31) | BIT(29)) 203 #define EIP197_HIA_DSE_CFG_EN_SINGLE_WR BIT(29) 204 #define EIP197_HIA_DSE_CFG_DIS_DEBUG BIT(31) 205 206 /* EIP197_HIA_DFE/DSE_THR_CTRL */ 207 #define EIP197_DxE_THR_CTRL_EN BIT(30) 208 #define EIP197_DxE_THR_CTRL_RESET_PE BIT(31) 209 210 /* EIP197_HIA_AIC_G_ENABLED_STAT */ 211 #define EIP197_G_IRQ_DFE(n) BIT((n) << 1) 212 #define EIP197_G_IRQ_DSE(n) BIT(((n) << 1) + 1) 213 #define EIP197_G_IRQ_RING BIT(16) 214 #define EIP197_G_IRQ_PE(n) BIT((n) + 20) 215 216 /* EIP197_HIA_MST_CTRL */ 217 #define RD_CACHE_3BITS 0x5 218 #define WR_CACHE_3BITS 0x3 219 #define RD_CACHE_4BITS (RD_CACHE_3BITS << 1 | BIT(0)) 220 #define WR_CACHE_4BITS (WR_CACHE_3BITS << 1 | BIT(0)) 221 #define EIP197_MST_CTRL_RD_CACHE(n) (((n) & 0xf) << 0) 222 #define EIP197_MST_CTRL_WD_CACHE(n) (((n) & 0xf) << 4) 223 #define EIP197_MST_CTRL_TX_MAX_CMD(n) (((n) & 0xf) << 20) 224 #define EIP197_MST_CTRL_BYTE_SWAP BIT(24) 225 #define EIP197_MST_CTRL_NO_BYTE_SWAP BIT(25) 226 227 /* EIP197_PE_IN_DBUF/TBUF_THRES */ 228 #define EIP197_PE_IN_xBUF_THRES_MIN(n) ((n) << 8) 229 #define EIP197_PE_IN_xBUF_THRES_MAX(n) ((n) << 12) 230 231 /* EIP197_PE_OUT_DBUF_THRES */ 232 #define EIP197_PE_OUT_DBUF_THRES_MIN(n) ((n) << 0) 233 #define EIP197_PE_OUT_DBUF_THRES_MAX(n) ((n) << 4) 234 235 /* EIP197_PE_ICE_SCRATCH_CTRL */ 236 #define EIP197_PE_ICE_SCRATCH_CTRL_CHANGE_TIMER BIT(2) 237 #define EIP197_PE_ICE_SCRATCH_CTRL_TIMER_EN BIT(3) 238 #define EIP197_PE_ICE_SCRATCH_CTRL_CHANGE_ACCESS BIT(24) 239 #define EIP197_PE_ICE_SCRATCH_CTRL_SCRATCH_ACCESS BIT(25) 240 241 /* EIP197_PE_ICE_SCRATCH_RAM */ 242 #define EIP197_NUM_OF_SCRATCH_BLOCKS 32 243 244 /* EIP197_PE_ICE_PUE/FPP_CTRL */ 245 #define EIP197_PE_ICE_x_CTRL_SW_RESET BIT(0) 246 #define EIP197_PE_ICE_x_CTRL_CLR_ECC_NON_CORR BIT(14) 247 #define EIP197_PE_ICE_x_CTRL_CLR_ECC_CORR BIT(15) 248 249 /* EIP197_PE_ICE_RAM_CTRL */ 250 #define EIP197_PE_ICE_RAM_CTRL_PUE_PROG_EN BIT(0) 251 #define EIP197_PE_ICE_RAM_CTRL_FPP_PROG_EN BIT(1) 252 253 /* EIP197_PE_EIP96_TOKEN_CTRL */ 254 #define EIP197_PE_EIP96_TOKEN_CTRL_CTX_UPDATES BIT(16) 255 #define EIP197_PE_EIP96_TOKEN_CTRL_REUSE_CTX BIT(19) 256 #define EIP197_PE_EIP96_TOKEN_CTRL_POST_REUSE_CTX BIT(20) 257 258 /* EIP197_PE_EIP96_FUNCTION_EN */ 259 #define EIP197_FUNCTION_RSVD (BIT(6) | BIT(15) | BIT(20) | BIT(23)) 260 #define EIP197_PROTOCOL_HASH_ONLY BIT(0) 261 #define EIP197_PROTOCOL_ENCRYPT_ONLY BIT(1) 262 #define EIP197_PROTOCOL_HASH_ENCRYPT BIT(2) 263 #define EIP197_PROTOCOL_HASH_DECRYPT BIT(3) 264 #define EIP197_PROTOCOL_ENCRYPT_HASH BIT(4) 265 #define EIP197_PROTOCOL_DECRYPT_HASH BIT(5) 266 #define EIP197_ALG_ARC4 BIT(7) 267 #define EIP197_ALG_AES_ECB BIT(8) 268 #define EIP197_ALG_AES_CBC BIT(9) 269 #define EIP197_ALG_AES_CTR_ICM BIT(10) 270 #define EIP197_ALG_AES_OFB BIT(11) 271 #define EIP197_ALG_AES_CFB BIT(12) 272 #define EIP197_ALG_DES_ECB BIT(13) 273 #define EIP197_ALG_DES_CBC BIT(14) 274 #define EIP197_ALG_DES_OFB BIT(16) 275 #define EIP197_ALG_DES_CFB BIT(17) 276 #define EIP197_ALG_3DES_ECB BIT(18) 277 #define EIP197_ALG_3DES_CBC BIT(19) 278 #define EIP197_ALG_3DES_OFB BIT(21) 279 #define EIP197_ALG_3DES_CFB BIT(22) 280 #define EIP197_ALG_MD5 BIT(24) 281 #define EIP197_ALG_HMAC_MD5 BIT(25) 282 #define EIP197_ALG_SHA1 BIT(26) 283 #define EIP197_ALG_HMAC_SHA1 BIT(27) 284 #define EIP197_ALG_SHA2 BIT(28) 285 #define EIP197_ALG_HMAC_SHA2 BIT(29) 286 #define EIP197_ALG_AES_XCBC_MAC BIT(30) 287 #define EIP197_ALG_GCM_HASH BIT(31) 288 289 /* EIP197_PE_EIP96_CONTEXT_CTRL */ 290 #define EIP197_CONTEXT_SIZE(n) (n) 291 #define EIP197_ADDRESS_MODE BIT(8) 292 #define EIP197_CONTROL_MODE BIT(9) 293 294 /* Context Control */ 295 struct safexcel_context_record { 296 u32 control0; 297 u32 control1; 298 299 __le32 data[40]; 300 } __packed; 301 302 /* control0 */ 303 #define CONTEXT_CONTROL_TYPE_NULL_OUT 0x0 304 #define CONTEXT_CONTROL_TYPE_NULL_IN 0x1 305 #define CONTEXT_CONTROL_TYPE_HASH_OUT 0x2 306 #define CONTEXT_CONTROL_TYPE_HASH_IN 0x3 307 #define CONTEXT_CONTROL_TYPE_CRYPTO_OUT 0x4 308 #define CONTEXT_CONTROL_TYPE_CRYPTO_IN 0x5 309 #define CONTEXT_CONTROL_TYPE_ENCRYPT_HASH_OUT 0x6 310 #define CONTEXT_CONTROL_TYPE_DECRYPT_HASH_IN 0x7 311 #define CONTEXT_CONTROL_TYPE_HASH_ENCRYPT_OUT 0xe 312 #define CONTEXT_CONTROL_TYPE_HASH_DECRYPT_IN 0xf 313 #define CONTEXT_CONTROL_RESTART_HASH BIT(4) 314 #define CONTEXT_CONTROL_NO_FINISH_HASH BIT(5) 315 #define CONTEXT_CONTROL_SIZE(n) ((n) << 8) 316 #define CONTEXT_CONTROL_KEY_EN BIT(16) 317 #define CONTEXT_CONTROL_CRYPTO_ALG_DES (0x0 << 17) 318 #define CONTEXT_CONTROL_CRYPTO_ALG_3DES (0x2 << 17) 319 #define CONTEXT_CONTROL_CRYPTO_ALG_AES128 (0x5 << 17) 320 #define CONTEXT_CONTROL_CRYPTO_ALG_AES192 (0x6 << 17) 321 #define CONTEXT_CONTROL_CRYPTO_ALG_AES256 (0x7 << 17) 322 #define CONTEXT_CONTROL_DIGEST_PRECOMPUTED (0x1 << 21) 323 #define CONTEXT_CONTROL_DIGEST_HMAC (0x3 << 21) 324 #define CONTEXT_CONTROL_CRYPTO_ALG_MD5 (0x0 << 23) 325 #define CONTEXT_CONTROL_CRYPTO_ALG_SHA1 (0x2 << 23) 326 #define CONTEXT_CONTROL_CRYPTO_ALG_SHA224 (0x4 << 23) 327 #define CONTEXT_CONTROL_CRYPTO_ALG_SHA256 (0x3 << 23) 328 #define CONTEXT_CONTROL_CRYPTO_ALG_SHA384 (0x6 << 23) 329 #define CONTEXT_CONTROL_CRYPTO_ALG_SHA512 (0x5 << 23) 330 #define CONTEXT_CONTROL_INV_FR (0x5 << 24) 331 #define CONTEXT_CONTROL_INV_TR (0x6 << 24) 332 333 /* control1 */ 334 #define CONTEXT_CONTROL_CRYPTO_MODE_ECB (0 << 0) 335 #define CONTEXT_CONTROL_CRYPTO_MODE_CBC (1 << 0) 336 #define CONTEXT_CONTROL_IV0 BIT(5) 337 #define CONTEXT_CONTROL_IV1 BIT(6) 338 #define CONTEXT_CONTROL_IV2 BIT(7) 339 #define CONTEXT_CONTROL_IV3 BIT(8) 340 #define CONTEXT_CONTROL_DIGEST_CNT BIT(9) 341 #define CONTEXT_CONTROL_COUNTER_MODE BIT(10) 342 #define CONTEXT_CONTROL_CRYPTO_STORE BIT(12) 343 #define CONTEXT_CONTROL_HASH_STORE BIT(19) 344 345 /* The hash counter given to the engine in the context has a granularity of 346 * 64 bits. 347 */ 348 #define EIP197_COUNTER_BLOCK_SIZE 64 349 350 /* EIP197_CS_RAM_CTRL */ 351 #define EIP197_TRC_ENABLE_0 BIT(4) 352 #define EIP197_TRC_ENABLE_1 BIT(5) 353 #define EIP197_TRC_ENABLE_2 BIT(6) 354 #define EIP197_TRC_ENABLE_MASK GENMASK(6, 4) 355 356 /* EIP197_TRC_PARAMS */ 357 #define EIP197_TRC_PARAMS_SW_RESET BIT(0) 358 #define EIP197_TRC_PARAMS_DATA_ACCESS BIT(2) 359 #define EIP197_TRC_PARAMS_HTABLE_SZ(x) ((x) << 4) 360 #define EIP197_TRC_PARAMS_BLK_TIMER_SPEED(x) ((x) << 10) 361 #define EIP197_TRC_PARAMS_RC_SZ_LARGE(n) ((n) << 18) 362 363 /* EIP197_TRC_FREECHAIN */ 364 #define EIP197_TRC_FREECHAIN_HEAD_PTR(p) (p) 365 #define EIP197_TRC_FREECHAIN_TAIL_PTR(p) ((p) << 16) 366 367 /* EIP197_TRC_PARAMS2 */ 368 #define EIP197_TRC_PARAMS2_HTABLE_PTR(p) (p) 369 #define EIP197_TRC_PARAMS2_RC_SZ_SMALL(n) ((n) << 18) 370 371 /* Cache helpers */ 372 #define EIP197B_CS_RC_MAX 52 373 #define EIP197D_CS_RC_MAX 96 374 #define EIP197_CS_RC_SIZE (4 * sizeof(u32)) 375 #define EIP197_CS_RC_NEXT(x) (x) 376 #define EIP197_CS_RC_PREV(x) ((x) << 10) 377 #define EIP197_RC_NULL 0x3ff 378 #define EIP197B_CS_TRC_REC_WC 59 379 #define EIP197D_CS_TRC_REC_WC 64 380 #define EIP197B_CS_TRC_LG_REC_WC 73 381 #define EIP197D_CS_TRC_LG_REC_WC 80 382 #define EIP197B_CS_HT_WC 64 383 #define EIP197D_CS_HT_WC 256 384 385 386 /* Result data */ 387 struct result_data_desc { 388 u32 packet_length:17; 389 u32 error_code:15; 390 391 u8 bypass_length:4; 392 u8 e15:1; 393 u16 rsvd0; 394 u8 hash_bytes:1; 395 u8 hash_length:6; 396 u8 generic_bytes:1; 397 u8 checksum:1; 398 u8 next_header:1; 399 u8 length:1; 400 401 u16 application_id; 402 u16 rsvd1; 403 404 u32 rsvd2; 405 } __packed; 406 407 408 /* Basic Result Descriptor format */ 409 struct safexcel_result_desc { 410 u32 particle_size:17; 411 u8 rsvd0:3; 412 u8 descriptor_overflow:1; 413 u8 buffer_overflow:1; 414 u8 last_seg:1; 415 u8 first_seg:1; 416 u16 result_size:8; 417 418 u32 rsvd1; 419 420 u32 data_lo; 421 u32 data_hi; 422 423 struct result_data_desc result_data; 424 } __packed; 425 426 struct safexcel_token { 427 u32 packet_length:17; 428 u8 stat:2; 429 u16 instructions:9; 430 u8 opcode:4; 431 } __packed; 432 433 #define EIP197_TOKEN_HASH_RESULT_VERIFY BIT(16) 434 435 #define EIP197_TOKEN_CTX_OFFSET(x) (x) 436 #define EIP197_TOKEN_DIRECTION_EXTERNAL BIT(11) 437 #define EIP197_TOKEN_EXEC_IF_SUCCESSFUL (0x1 << 12) 438 439 #define EIP197_TOKEN_STAT_LAST_HASH BIT(0) 440 #define EIP197_TOKEN_STAT_LAST_PACKET BIT(1) 441 #define EIP197_TOKEN_OPCODE_DIRECTION 0x0 442 #define EIP197_TOKEN_OPCODE_INSERT 0x2 443 #define EIP197_TOKEN_OPCODE_NOOP EIP197_TOKEN_OPCODE_INSERT 444 #define EIP197_TOKEN_OPCODE_RETRIEVE 0x4 445 #define EIP197_TOKEN_OPCODE_VERIFY 0xd 446 #define EIP197_TOKEN_OPCODE_CTX_ACCESS 0xe 447 #define EIP197_TOKEN_OPCODE_BYPASS GENMASK(3, 0) 448 449 static inline void eip197_noop_token(struct safexcel_token *token) 450 { 451 token->opcode = EIP197_TOKEN_OPCODE_NOOP; 452 token->packet_length = BIT(2); 453 } 454 455 /* Instructions */ 456 #define EIP197_TOKEN_INS_INSERT_HASH_DIGEST 0x1c 457 #define EIP197_TOKEN_INS_ORIGIN_IV0 0x14 458 #define EIP197_TOKEN_INS_ORIGIN_LEN(x) ((x) << 5) 459 #define EIP197_TOKEN_INS_TYPE_OUTPUT BIT(5) 460 #define EIP197_TOKEN_INS_TYPE_HASH BIT(6) 461 #define EIP197_TOKEN_INS_TYPE_CRYTO BIT(7) 462 #define EIP197_TOKEN_INS_LAST BIT(8) 463 464 /* Processing Engine Control Data */ 465 struct safexcel_control_data_desc { 466 u32 packet_length:17; 467 u16 options:13; 468 u8 type:2; 469 470 u16 application_id; 471 u16 rsvd; 472 473 u8 refresh:2; 474 u32 context_lo:30; 475 u32 context_hi; 476 477 u32 control0; 478 u32 control1; 479 480 u32 token[EIP197_MAX_TOKENS]; 481 } __packed; 482 483 #define EIP197_OPTION_MAGIC_VALUE BIT(0) 484 #define EIP197_OPTION_64BIT_CTX BIT(1) 485 #define EIP197_OPTION_RC_AUTO (0x2 << 3) 486 #define EIP197_OPTION_CTX_CTRL_IN_CMD BIT(8) 487 #define EIP197_OPTION_2_TOKEN_IV_CMD GENMASK(11, 10) 488 #define EIP197_OPTION_4_TOKEN_IV_CMD GENMASK(11, 9) 489 490 #define EIP197_TYPE_EXTENDED 0x3 491 492 /* Basic Command Descriptor format */ 493 struct safexcel_command_desc { 494 u32 particle_size:17; 495 u8 rsvd0:5; 496 u8 last_seg:1; 497 u8 first_seg:1; 498 u16 additional_cdata_size:8; 499 500 u32 rsvd1; 501 502 u32 data_lo; 503 u32 data_hi; 504 505 struct safexcel_control_data_desc control_data; 506 } __packed; 507 508 /* 509 * Internal structures & functions 510 */ 511 512 enum eip197_fw { 513 FW_IFPP = 0, 514 FW_IPUE, 515 FW_NB 516 }; 517 518 struct safexcel_desc_ring { 519 void *base; 520 void *base_end; 521 dma_addr_t base_dma; 522 523 /* write and read pointers */ 524 void *write; 525 void *read; 526 527 /* descriptor element offset */ 528 unsigned offset; 529 }; 530 531 enum safexcel_alg_type { 532 SAFEXCEL_ALG_TYPE_SKCIPHER, 533 SAFEXCEL_ALG_TYPE_AEAD, 534 SAFEXCEL_ALG_TYPE_AHASH, 535 }; 536 537 struct safexcel_config { 538 u32 pes; 539 u32 rings; 540 541 u32 cd_size; 542 u32 cd_offset; 543 544 u32 rd_size; 545 u32 rd_offset; 546 }; 547 548 struct safexcel_work_data { 549 struct work_struct work; 550 struct safexcel_crypto_priv *priv; 551 int ring; 552 }; 553 554 struct safexcel_ring { 555 spinlock_t lock; 556 557 struct workqueue_struct *workqueue; 558 struct safexcel_work_data work_data; 559 560 /* command/result rings */ 561 struct safexcel_desc_ring cdr; 562 struct safexcel_desc_ring rdr; 563 564 /* result ring crypto API request */ 565 struct crypto_async_request **rdr_req; 566 567 /* queue */ 568 struct crypto_queue queue; 569 spinlock_t queue_lock; 570 571 /* Number of requests in the engine. */ 572 int requests; 573 574 /* The ring is currently handling at least one request */ 575 bool busy; 576 577 /* Store for current requests when bailing out of the dequeueing 578 * function when no enough resources are available. 579 */ 580 struct crypto_async_request *req; 581 struct crypto_async_request *backlog; 582 }; 583 584 enum safexcel_eip_version { 585 EIP97IES = BIT(0), 586 EIP197B = BIT(1), 587 EIP197D = BIT(2), 588 }; 589 590 struct safexcel_register_offsets { 591 u32 hia_aic; 592 u32 hia_aic_g; 593 u32 hia_aic_r; 594 u32 hia_aic_xdr; 595 u32 hia_dfe; 596 u32 hia_dfe_thr; 597 u32 hia_dse; 598 u32 hia_dse_thr; 599 u32 hia_gen_cfg; 600 u32 pe; 601 }; 602 603 enum safexcel_flags { 604 EIP197_TRC_CACHE = BIT(0), 605 }; 606 607 struct safexcel_crypto_priv { 608 void __iomem *base; 609 struct device *dev; 610 struct clk *clk; 611 struct clk *reg_clk; 612 struct safexcel_config config; 613 614 enum safexcel_eip_version version; 615 struct safexcel_register_offsets offsets; 616 u32 flags; 617 618 /* context DMA pool */ 619 struct dma_pool *context_pool; 620 621 atomic_t ring_used; 622 623 struct safexcel_ring *ring; 624 }; 625 626 struct safexcel_context { 627 int (*send)(struct crypto_async_request *req, int ring, 628 int *commands, int *results); 629 int (*handle_result)(struct safexcel_crypto_priv *priv, int ring, 630 struct crypto_async_request *req, bool *complete, 631 int *ret); 632 struct safexcel_context_record *ctxr; 633 dma_addr_t ctxr_dma; 634 635 int ring; 636 bool needs_inv; 637 bool exit_inv; 638 }; 639 640 struct safexcel_ahash_export_state { 641 u64 len[2]; 642 u64 processed[2]; 643 644 u32 digest; 645 646 u32 state[SHA512_DIGEST_SIZE / sizeof(u32)]; 647 u8 cache[SHA512_BLOCK_SIZE << 1]; 648 }; 649 650 /* 651 * Template structure to describe the algorithms in order to register them. 652 * It also has the purpose to contain our private structure and is actually 653 * the only way I know in this framework to avoid having global pointers... 654 */ 655 struct safexcel_alg_template { 656 struct safexcel_crypto_priv *priv; 657 enum safexcel_alg_type type; 658 u32 engines; 659 union { 660 struct skcipher_alg skcipher; 661 struct aead_alg aead; 662 struct ahash_alg ahash; 663 } alg; 664 }; 665 666 struct safexcel_inv_result { 667 struct completion completion; 668 int error; 669 }; 670 671 void safexcel_dequeue(struct safexcel_crypto_priv *priv, int ring); 672 int safexcel_rdesc_check_errors(struct safexcel_crypto_priv *priv, 673 struct safexcel_result_desc *rdesc); 674 void safexcel_complete(struct safexcel_crypto_priv *priv, int ring); 675 int safexcel_invalidate_cache(struct crypto_async_request *async, 676 struct safexcel_crypto_priv *priv, 677 dma_addr_t ctxr_dma, int ring); 678 int safexcel_init_ring_descriptors(struct safexcel_crypto_priv *priv, 679 struct safexcel_desc_ring *cdr, 680 struct safexcel_desc_ring *rdr); 681 int safexcel_select_ring(struct safexcel_crypto_priv *priv); 682 void *safexcel_ring_next_rptr(struct safexcel_crypto_priv *priv, 683 struct safexcel_desc_ring *ring); 684 void *safexcel_ring_first_rptr(struct safexcel_crypto_priv *priv, int ring); 685 void safexcel_ring_rollback_wptr(struct safexcel_crypto_priv *priv, 686 struct safexcel_desc_ring *ring); 687 struct safexcel_command_desc *safexcel_add_cdesc(struct safexcel_crypto_priv *priv, 688 int ring_id, 689 bool first, bool last, 690 dma_addr_t data, u32 len, 691 u32 full_data_len, 692 dma_addr_t context); 693 struct safexcel_result_desc *safexcel_add_rdesc(struct safexcel_crypto_priv *priv, 694 int ring_id, 695 bool first, bool last, 696 dma_addr_t data, u32 len); 697 int safexcel_ring_first_rdr_index(struct safexcel_crypto_priv *priv, 698 int ring); 699 int safexcel_ring_rdr_rdesc_index(struct safexcel_crypto_priv *priv, 700 int ring, 701 struct safexcel_result_desc *rdesc); 702 void safexcel_rdr_req_set(struct safexcel_crypto_priv *priv, 703 int ring, 704 struct safexcel_result_desc *rdesc, 705 struct crypto_async_request *req); 706 inline struct crypto_async_request * 707 safexcel_rdr_req_get(struct safexcel_crypto_priv *priv, int ring); 708 void safexcel_inv_complete(struct crypto_async_request *req, int error); 709 int safexcel_hmac_setkey(const char *alg, const u8 *key, unsigned int keylen, 710 void *istate, void *ostate); 711 712 /* available algorithms */ 713 extern struct safexcel_alg_template safexcel_alg_ecb_des; 714 extern struct safexcel_alg_template safexcel_alg_cbc_des; 715 extern struct safexcel_alg_template safexcel_alg_ecb_des3_ede; 716 extern struct safexcel_alg_template safexcel_alg_cbc_des3_ede; 717 extern struct safexcel_alg_template safexcel_alg_ecb_aes; 718 extern struct safexcel_alg_template safexcel_alg_cbc_aes; 719 extern struct safexcel_alg_template safexcel_alg_md5; 720 extern struct safexcel_alg_template safexcel_alg_sha1; 721 extern struct safexcel_alg_template safexcel_alg_sha224; 722 extern struct safexcel_alg_template safexcel_alg_sha256; 723 extern struct safexcel_alg_template safexcel_alg_sha384; 724 extern struct safexcel_alg_template safexcel_alg_sha512; 725 extern struct safexcel_alg_template safexcel_alg_hmac_md5; 726 extern struct safexcel_alg_template safexcel_alg_hmac_sha1; 727 extern struct safexcel_alg_template safexcel_alg_hmac_sha224; 728 extern struct safexcel_alg_template safexcel_alg_hmac_sha256; 729 extern struct safexcel_alg_template safexcel_alg_hmac_sha384; 730 extern struct safexcel_alg_template safexcel_alg_hmac_sha512; 731 extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha1_cbc_aes; 732 extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha224_cbc_aes; 733 extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha256_cbc_aes; 734 extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha384_cbc_aes; 735 extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha512_cbc_aes; 736 737 #endif 738