1 /* 2 * Copyright (C) 2017 Marvell 3 * 4 * Antoine Tenart <antoine.tenart@free-electrons.com> 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without any 8 * warranty of any kind, whether express or implied. 9 */ 10 11 #ifndef __SAFEXCEL_H__ 12 #define __SAFEXCEL_H__ 13 14 #include <crypto/algapi.h> 15 #include <crypto/internal/hash.h> 16 #include <crypto/skcipher.h> 17 18 #define EIP197_HIA_VERSION_LE 0xca35 19 #define EIP197_HIA_VERSION_BE 0x35ca 20 21 /* Static configuration */ 22 #define EIP197_DEFAULT_RING_SIZE 64 23 #define EIP197_MAX_TOKENS 5 24 #define EIP197_MAX_RINGS 4 25 #define EIP197_FETCH_COUNT 1 26 #define EIP197_MAX_BATCH_SZ EIP197_DEFAULT_RING_SIZE 27 28 #define EIP197_GFP_FLAGS(base) ((base).flags & CRYPTO_TFM_REQ_MAY_SLEEP ? \ 29 GFP_KERNEL : GFP_ATOMIC) 30 31 /* CDR/RDR register offsets */ 32 #define EIP197_HIA_xDR_OFF(r) (0x80000 + (r) * 0x1000) 33 #define EIP197_HIA_CDR(r) (EIP197_HIA_xDR_OFF(r)) 34 #define EIP197_HIA_RDR(r) (EIP197_HIA_xDR_OFF(r) + 0x800) 35 #define EIP197_HIA_xDR_RING_BASE_ADDR_LO 0x0 36 #define EIP197_HIA_xDR_RING_BASE_ADDR_HI 0x4 37 #define EIP197_HIA_xDR_RING_SIZE 0x18 38 #define EIP197_HIA_xDR_DESC_SIZE 0x1c 39 #define EIP197_HIA_xDR_CFG 0x20 40 #define EIP197_HIA_xDR_DMA_CFG 0x24 41 #define EIP197_HIA_xDR_THRESH 0x28 42 #define EIP197_HIA_xDR_PREP_COUNT 0x2c 43 #define EIP197_HIA_xDR_PROC_COUNT 0x30 44 #define EIP197_HIA_xDR_PREP_PNTR 0x34 45 #define EIP197_HIA_xDR_PROC_PNTR 0x38 46 #define EIP197_HIA_xDR_STAT 0x3c 47 48 /* register offsets */ 49 #define EIP197_HIA_DFE_CFG 0x8c000 50 #define EIP197_HIA_DFE_THR_CTRL 0x8c040 51 #define EIP197_HIA_DFE_THR_STAT 0x8c044 52 #define EIP197_HIA_DSE_CFG 0x8d000 53 #define EIP197_HIA_DSE_THR_CTRL 0x8d040 54 #define EIP197_HIA_DSE_THR_STAT 0x8d044 55 #define EIP197_HIA_RA_PE_CTRL 0x90010 56 #define EIP197_HIA_RA_PE_STAT 0x90014 57 #define EIP197_HIA_AIC_R_OFF(r) ((r) * 0x1000) 58 #define EIP197_HIA_AIC_R_ENABLE_CTRL(r) (0x9e808 - EIP197_HIA_AIC_R_OFF(r)) 59 #define EIP197_HIA_AIC_R_ENABLED_STAT(r) (0x9e810 - EIP197_HIA_AIC_R_OFF(r)) 60 #define EIP197_HIA_AIC_R_ACK(r) (0x9e810 - EIP197_HIA_AIC_R_OFF(r)) 61 #define EIP197_HIA_AIC_R_ENABLE_CLR(r) (0x9e814 - EIP197_HIA_AIC_R_OFF(r)) 62 #define EIP197_HIA_AIC_G_ENABLE_CTRL 0x9f808 63 #define EIP197_HIA_AIC_G_ENABLED_STAT 0x9f810 64 #define EIP197_HIA_AIC_G_ACK 0x9f810 65 #define EIP197_HIA_MST_CTRL 0x9fff4 66 #define EIP197_HIA_OPTIONS 0x9fff8 67 #define EIP197_HIA_VERSION 0x9fffc 68 #define EIP197_PE_IN_DBUF_THRES 0xa0000 69 #define EIP197_PE_IN_TBUF_THRES 0xa0100 70 #define EIP197_PE_ICE_SCRATCH_RAM 0xa0800 71 #define EIP197_PE_ICE_PUE_CTRL 0xa0c80 72 #define EIP197_PE_ICE_SCRATCH_CTRL 0xa0d04 73 #define EIP197_PE_ICE_FPP_CTRL 0xa0d80 74 #define EIP197_PE_ICE_RAM_CTRL 0xa0ff0 75 #define EIP197_PE_EIP96_FUNCTION_EN 0xa1004 76 #define EIP197_PE_EIP96_CONTEXT_CTRL 0xa1008 77 #define EIP197_PE_EIP96_CONTEXT_STAT 0xa100c 78 #define EIP197_PE_OUT_DBUF_THRES 0xa1c00 79 #define EIP197_PE_OUT_TBUF_THRES 0xa1d00 80 #define EIP197_CLASSIFICATION_RAMS 0xe0000 81 #define EIP197_TRC_CTRL 0xf0800 82 #define EIP197_TRC_LASTRES 0xf0804 83 #define EIP197_TRC_REGINDEX 0xf0808 84 #define EIP197_TRC_PARAMS 0xf0820 85 #define EIP197_TRC_FREECHAIN 0xf0824 86 #define EIP197_TRC_PARAMS2 0xf0828 87 #define EIP197_TRC_ECCCTRL 0xf0830 88 #define EIP197_TRC_ECCSTAT 0xf0834 89 #define EIP197_TRC_ECCADMINSTAT 0xf0838 90 #define EIP197_TRC_ECCDATASTAT 0xf083c 91 #define EIP197_TRC_ECCDATA 0xf0840 92 #define EIP197_CS_RAM_CTRL 0xf7ff0 93 #define EIP197_MST_CTRL 0xffff4 94 95 /* EIP197_HIA_xDR_DESC_SIZE */ 96 #define EIP197_xDR_DESC_MODE_64BIT BIT(31) 97 98 /* EIP197_HIA_xDR_DMA_CFG */ 99 #define EIP197_HIA_xDR_WR_RES_BUF BIT(22) 100 #define EIP197_HIA_xDR_WR_CTRL_BUG BIT(23) 101 #define EIP197_HIA_xDR_WR_OWN_BUF BIT(24) 102 #define EIP197_HIA_xDR_CFG_WR_CACHE(n) (((n) & 0x7) << 25) 103 #define EIP197_HIA_xDR_CFG_RD_CACHE(n) (((n) & 0x7) << 29) 104 105 /* EIP197_HIA_CDR_THRESH */ 106 #define EIP197_HIA_CDR_THRESH_PROC_PKT(n) (n) 107 #define EIP197_HIA_CDR_THRESH_PROC_MODE BIT(22) 108 #define EIP197_HIA_CDR_THRESH_PKT_MODE BIT(23) 109 #define EIP197_HIA_CDR_THRESH_TIMEOUT(n) ((n) << 24) /* x256 clk cycles */ 110 111 /* EIP197_HIA_RDR_THRESH */ 112 #define EIP197_HIA_RDR_THRESH_PROC_PKT(n) (n) 113 #define EIP197_HIA_RDR_THRESH_PKT_MODE BIT(23) 114 #define EIP197_HIA_RDR_THRESH_TIMEOUT(n) ((n) << 24) /* x256 clk cycles */ 115 116 /* EIP197_HIA_xDR_PREP_COUNT */ 117 #define EIP197_xDR_PREP_CLR_COUNT BIT(31) 118 119 /* EIP197_HIA_xDR_PROC_COUNT */ 120 #define EIP197_xDR_PROC_xD_COUNT(n) ((n) << 2) 121 #define EIP197_xDR_PROC_xD_PKT(n) ((n) << 24) 122 #define EIP197_xDR_PROC_CLR_COUNT BIT(31) 123 124 /* EIP197_HIA_xDR_STAT */ 125 #define EIP197_xDR_DMA_ERR BIT(0) 126 #define EIP197_xDR_PREP_CMD_THRES BIT(1) 127 #define EIP197_xDR_ERR BIT(2) 128 #define EIP197_xDR_THRESH BIT(4) 129 #define EIP197_xDR_TIMEOUT BIT(5) 130 131 #define EIP197_HIA_RA_PE_CTRL_RESET BIT(31) 132 #define EIP197_HIA_RA_PE_CTRL_EN BIT(30) 133 134 /* EIP197_HIA_AIC_R_ENABLE_CTRL */ 135 #define EIP197_CDR_IRQ(n) BIT((n) * 2) 136 #define EIP197_RDR_IRQ(n) BIT((n) * 2 + 1) 137 138 /* EIP197_HIA_DFE/DSE_CFG */ 139 #define EIP197_HIA_DxE_CFG_MIN_DATA_SIZE(n) ((n) << 0) 140 #define EIP197_HIA_DxE_CFG_DATA_CACHE_CTRL(n) (((n) & 0x7) << 4) 141 #define EIP197_HIA_DxE_CFG_MAX_DATA_SIZE(n) ((n) << 8) 142 #define EIP197_HIA_DSE_CFG_ALLWAYS_BUFFERABLE GENMASK(15, 14) 143 #define EIP197_HIA_DxE_CFG_MIN_CTRL_SIZE(n) ((n) << 16) 144 #define EIP197_HIA_DxE_CFG_CTRL_CACHE_CTRL(n) (((n) & 0x7) << 20) 145 #define EIP197_HIA_DxE_CFG_MAX_CTRL_SIZE(n) ((n) << 24) 146 #define EIP197_HIA_DFE_CFG_DIS_DEBUG (BIT(31) | BIT(29)) 147 #define EIP197_HIA_DSE_CFG_EN_SINGLE_WR BIT(29) 148 #define EIP197_HIA_DSE_CFG_DIS_DEBUG BIT(31) 149 150 /* EIP197_HIA_DFE/DSE_THR_CTRL */ 151 #define EIP197_DxE_THR_CTRL_EN BIT(30) 152 #define EIP197_DxE_THR_CTRL_RESET_PE BIT(31) 153 154 /* EIP197_HIA_AIC_G_ENABLED_STAT */ 155 #define EIP197_G_IRQ_DFE(n) BIT((n) << 1) 156 #define EIP197_G_IRQ_DSE(n) BIT(((n) << 1) + 1) 157 #define EIP197_G_IRQ_RING BIT(16) 158 #define EIP197_G_IRQ_PE(n) BIT((n) + 20) 159 160 /* EIP197_HIA_MST_CTRL */ 161 #define RD_CACHE_3BITS 0x5 162 #define WR_CACHE_3BITS 0x3 163 #define RD_CACHE_4BITS (RD_CACHE_3BITS << 1 | BIT(0)) 164 #define WR_CACHE_4BITS (WR_CACHE_3BITS << 1 | BIT(0)) 165 #define EIP197_MST_CTRL_RD_CACHE(n) (((n) & 0xf) << 0) 166 #define EIP197_MST_CTRL_WD_CACHE(n) (((n) & 0xf) << 4) 167 #define EIP197_MST_CTRL_BYTE_SWAP BIT(24) 168 #define EIP197_MST_CTRL_NO_BYTE_SWAP BIT(25) 169 170 /* EIP197_PE_IN_DBUF/TBUF_THRES */ 171 #define EIP197_PE_IN_xBUF_THRES_MIN(n) ((n) << 8) 172 #define EIP197_PE_IN_xBUF_THRES_MAX(n) ((n) << 12) 173 174 /* EIP197_PE_OUT_DBUF_THRES */ 175 #define EIP197_PE_OUT_DBUF_THRES_MIN(n) ((n) << 0) 176 #define EIP197_PE_OUT_DBUF_THRES_MAX(n) ((n) << 4) 177 178 /* EIP197_PE_ICE_SCRATCH_CTRL */ 179 #define EIP197_PE_ICE_SCRATCH_CTRL_CHANGE_TIMER BIT(2) 180 #define EIP197_PE_ICE_SCRATCH_CTRL_TIMER_EN BIT(3) 181 #define EIP197_PE_ICE_SCRATCH_CTRL_CHANGE_ACCESS BIT(24) 182 #define EIP197_PE_ICE_SCRATCH_CTRL_SCRATCH_ACCESS BIT(25) 183 184 /* EIP197_PE_ICE_SCRATCH_RAM */ 185 #define EIP197_NUM_OF_SCRATCH_BLOCKS 32 186 187 /* EIP197_PE_ICE_PUE/FPP_CTRL */ 188 #define EIP197_PE_ICE_x_CTRL_SW_RESET BIT(0) 189 #define EIP197_PE_ICE_x_CTRL_CLR_ECC_NON_CORR BIT(14) 190 #define EIP197_PE_ICE_x_CTRL_CLR_ECC_CORR BIT(15) 191 192 /* EIP197_PE_ICE_RAM_CTRL */ 193 #define EIP197_PE_ICE_RAM_CTRL_PUE_PROG_EN BIT(0) 194 #define EIP197_PE_ICE_RAM_CTRL_FPP_PROG_EN BIT(1) 195 196 /* EIP197_PE_EIP96_FUNCTION_EN */ 197 #define EIP197_FUNCTION_RSVD (BIT(6) | BIT(15) | BIT(20) | BIT(23)) 198 #define EIP197_PROTOCOL_HASH_ONLY BIT(0) 199 #define EIP197_PROTOCOL_ENCRYPT_ONLY BIT(1) 200 #define EIP197_PROTOCOL_HASH_ENCRYPT BIT(2) 201 #define EIP197_PROTOCOL_HASH_DECRYPT BIT(3) 202 #define EIP197_PROTOCOL_ENCRYPT_HASH BIT(4) 203 #define EIP197_PROTOCOL_DECRYPT_HASH BIT(5) 204 #define EIP197_ALG_ARC4 BIT(7) 205 #define EIP197_ALG_AES_ECB BIT(8) 206 #define EIP197_ALG_AES_CBC BIT(9) 207 #define EIP197_ALG_AES_CTR_ICM BIT(10) 208 #define EIP197_ALG_AES_OFB BIT(11) 209 #define EIP197_ALG_AES_CFB BIT(12) 210 #define EIP197_ALG_DES_ECB BIT(13) 211 #define EIP197_ALG_DES_CBC BIT(14) 212 #define EIP197_ALG_DES_OFB BIT(16) 213 #define EIP197_ALG_DES_CFB BIT(17) 214 #define EIP197_ALG_3DES_ECB BIT(18) 215 #define EIP197_ALG_3DES_CBC BIT(19) 216 #define EIP197_ALG_3DES_OFB BIT(21) 217 #define EIP197_ALG_3DES_CFB BIT(22) 218 #define EIP197_ALG_MD5 BIT(24) 219 #define EIP197_ALG_HMAC_MD5 BIT(25) 220 #define EIP197_ALG_SHA1 BIT(26) 221 #define EIP197_ALG_HMAC_SHA1 BIT(27) 222 #define EIP197_ALG_SHA2 BIT(28) 223 #define EIP197_ALG_HMAC_SHA2 BIT(29) 224 #define EIP197_ALG_AES_XCBC_MAC BIT(30) 225 #define EIP197_ALG_GCM_HASH BIT(31) 226 227 /* EIP197_PE_EIP96_CONTEXT_CTRL */ 228 #define EIP197_CONTEXT_SIZE(n) (n) 229 #define EIP197_ADDRESS_MODE BIT(8) 230 #define EIP197_CONTROL_MODE BIT(9) 231 232 /* Context Control */ 233 struct safexcel_context_record { 234 u32 control0; 235 u32 control1; 236 237 __le32 data[12]; 238 } __packed; 239 240 /* control0 */ 241 #define CONTEXT_CONTROL_TYPE_NULL_OUT 0x0 242 #define CONTEXT_CONTROL_TYPE_NULL_IN 0x1 243 #define CONTEXT_CONTROL_TYPE_HASH_OUT 0x2 244 #define CONTEXT_CONTROL_TYPE_HASH_IN 0x3 245 #define CONTEXT_CONTROL_TYPE_CRYPTO_OUT 0x4 246 #define CONTEXT_CONTROL_TYPE_CRYPTO_IN 0x5 247 #define CONTEXT_CONTROL_TYPE_ENCRYPT_HASH_OUT 0x6 248 #define CONTEXT_CONTROL_TYPE_DECRYPT_HASH_IN 0x7 249 #define CONTEXT_CONTROL_TYPE_HASH_ENCRYPT_OUT 0x14 250 #define CONTEXT_CONTROL_TYPE_HASH_DECRYPT_OUT 0x15 251 #define CONTEXT_CONTROL_RESTART_HASH BIT(4) 252 #define CONTEXT_CONTROL_NO_FINISH_HASH BIT(5) 253 #define CONTEXT_CONTROL_SIZE(n) ((n) << 8) 254 #define CONTEXT_CONTROL_KEY_EN BIT(16) 255 #define CONTEXT_CONTROL_CRYPTO_ALG_AES128 (0x5 << 17) 256 #define CONTEXT_CONTROL_CRYPTO_ALG_AES192 (0x6 << 17) 257 #define CONTEXT_CONTROL_CRYPTO_ALG_AES256 (0x7 << 17) 258 #define CONTEXT_CONTROL_DIGEST_PRECOMPUTED (0x1 << 21) 259 #define CONTEXT_CONTROL_DIGEST_HMAC (0x3 << 21) 260 #define CONTEXT_CONTROL_CRYPTO_ALG_SHA1 (0x2 << 23) 261 #define CONTEXT_CONTROL_CRYPTO_ALG_SHA224 (0x4 << 23) 262 #define CONTEXT_CONTROL_CRYPTO_ALG_SHA256 (0x3 << 23) 263 #define CONTEXT_CONTROL_INV_FR (0x5 << 24) 264 #define CONTEXT_CONTROL_INV_TR (0x6 << 24) 265 266 /* control1 */ 267 #define CONTEXT_CONTROL_CRYPTO_MODE_ECB (0 << 0) 268 #define CONTEXT_CONTROL_CRYPTO_MODE_CBC (1 << 0) 269 #define CONTEXT_CONTROL_IV0 BIT(5) 270 #define CONTEXT_CONTROL_IV1 BIT(6) 271 #define CONTEXT_CONTROL_IV2 BIT(7) 272 #define CONTEXT_CONTROL_IV3 BIT(8) 273 #define CONTEXT_CONTROL_DIGEST_CNT BIT(9) 274 #define CONTEXT_CONTROL_COUNTER_MODE BIT(10) 275 #define CONTEXT_CONTROL_HASH_STORE BIT(19) 276 277 /* EIP197_CS_RAM_CTRL */ 278 #define EIP197_TRC_ENABLE_0 BIT(4) 279 #define EIP197_TRC_ENABLE_1 BIT(5) 280 #define EIP197_TRC_ENABLE_2 BIT(6) 281 #define EIP197_TRC_ENABLE_MASK GENMASK(6, 4) 282 283 /* EIP197_TRC_PARAMS */ 284 #define EIP197_TRC_PARAMS_SW_RESET BIT(0) 285 #define EIP197_TRC_PARAMS_DATA_ACCESS BIT(2) 286 #define EIP197_TRC_PARAMS_HTABLE_SZ(x) ((x) << 4) 287 #define EIP197_TRC_PARAMS_BLK_TIMER_SPEED(x) ((x) << 10) 288 #define EIP197_TRC_PARAMS_RC_SZ_LARGE(n) ((n) << 18) 289 290 /* EIP197_TRC_FREECHAIN */ 291 #define EIP197_TRC_FREECHAIN_HEAD_PTR(p) (p) 292 #define EIP197_TRC_FREECHAIN_TAIL_PTR(p) ((p) << 16) 293 294 /* EIP197_TRC_PARAMS2 */ 295 #define EIP197_TRC_PARAMS2_HTABLE_PTR(p) (p) 296 #define EIP197_TRC_PARAMS2_RC_SZ_SMALL(n) ((n) << 18) 297 298 /* Cache helpers */ 299 #define EIP197_CS_RC_MAX 52 300 #define EIP197_CS_RC_SIZE (4 * sizeof(u32)) 301 #define EIP197_CS_RC_NEXT(x) (x) 302 #define EIP197_CS_RC_PREV(x) ((x) << 10) 303 #define EIP197_RC_NULL 0x3ff 304 #define EIP197_CS_TRC_REC_WC 59 305 #define EIP197_CS_TRC_LG_REC_WC 73 306 307 /* Result data */ 308 struct result_data_desc { 309 u32 packet_length:17; 310 u32 error_code:15; 311 312 u8 bypass_length:4; 313 u8 e15:1; 314 u16 rsvd0; 315 u8 hash_bytes:1; 316 u8 hash_length:6; 317 u8 generic_bytes:1; 318 u8 checksum:1; 319 u8 next_header:1; 320 u8 length:1; 321 322 u16 application_id; 323 u16 rsvd1; 324 325 u32 rsvd2; 326 } __packed; 327 328 329 /* Basic Result Descriptor format */ 330 struct safexcel_result_desc { 331 u32 particle_size:17; 332 u8 rsvd0:3; 333 u8 descriptor_overflow:1; 334 u8 buffer_overflow:1; 335 u8 last_seg:1; 336 u8 first_seg:1; 337 u16 result_size:8; 338 339 u32 rsvd1; 340 341 u32 data_lo; 342 u32 data_hi; 343 344 struct result_data_desc result_data; 345 } __packed; 346 347 struct safexcel_token { 348 u32 packet_length:17; 349 u8 stat:2; 350 u16 instructions:9; 351 u8 opcode:4; 352 } __packed; 353 354 #define EIP197_TOKEN_STAT_LAST_HASH BIT(0) 355 #define EIP197_TOKEN_STAT_LAST_PACKET BIT(1) 356 #define EIP197_TOKEN_OPCODE_DIRECTION 0x0 357 #define EIP197_TOKEN_OPCODE_INSERT 0x2 358 #define EIP197_TOKEN_OPCODE_NOOP EIP197_TOKEN_OPCODE_INSERT 359 #define EIP197_TOKEN_OPCODE_BYPASS GENMASK(3, 0) 360 361 static inline void eip197_noop_token(struct safexcel_token *token) 362 { 363 token->opcode = EIP197_TOKEN_OPCODE_NOOP; 364 token->packet_length = BIT(2); 365 } 366 367 /* Instructions */ 368 #define EIP197_TOKEN_INS_INSERT_HASH_DIGEST 0x1c 369 #define EIP197_TOKEN_INS_TYPE_OUTPUT BIT(5) 370 #define EIP197_TOKEN_INS_TYPE_HASH BIT(6) 371 #define EIP197_TOKEN_INS_TYPE_CRYTO BIT(7) 372 #define EIP197_TOKEN_INS_LAST BIT(8) 373 374 /* Processing Engine Control Data */ 375 struct safexcel_control_data_desc { 376 u32 packet_length:17; 377 u16 options:13; 378 u8 type:2; 379 380 u16 application_id; 381 u16 rsvd; 382 383 u8 refresh:2; 384 u32 context_lo:30; 385 u32 context_hi; 386 387 u32 control0; 388 u32 control1; 389 390 u32 token[EIP197_MAX_TOKENS]; 391 } __packed; 392 393 #define EIP197_OPTION_MAGIC_VALUE BIT(0) 394 #define EIP197_OPTION_64BIT_CTX BIT(1) 395 #define EIP197_OPTION_CTX_CTRL_IN_CMD BIT(8) 396 #define EIP197_OPTION_4_TOKEN_IV_CMD GENMASK(11, 9) 397 398 #define EIP197_TYPE_EXTENDED 0x3 399 400 /* Basic Command Descriptor format */ 401 struct safexcel_command_desc { 402 u32 particle_size:17; 403 u8 rsvd0:5; 404 u8 last_seg:1; 405 u8 first_seg:1; 406 u16 additional_cdata_size:8; 407 408 u32 rsvd1; 409 410 u32 data_lo; 411 u32 data_hi; 412 413 struct safexcel_control_data_desc control_data; 414 } __packed; 415 416 /* 417 * Internal structures & functions 418 */ 419 420 enum eip197_fw { 421 FW_IFPP = 0, 422 FW_IPUE, 423 FW_NB 424 }; 425 426 struct safexcel_ring { 427 void *base; 428 void *base_end; 429 dma_addr_t base_dma; 430 431 /* write and read pointers */ 432 void *write; 433 void *read; 434 435 /* number of elements used in the ring */ 436 unsigned nr; 437 unsigned offset; 438 }; 439 440 enum safexcel_alg_type { 441 SAFEXCEL_ALG_TYPE_SKCIPHER, 442 SAFEXCEL_ALG_TYPE_AHASH, 443 }; 444 445 struct safexcel_request { 446 struct list_head list; 447 struct crypto_async_request *req; 448 }; 449 450 struct safexcel_config { 451 u32 rings; 452 453 u32 cd_size; 454 u32 cd_offset; 455 456 u32 rd_size; 457 u32 rd_offset; 458 }; 459 460 struct safexcel_work_data { 461 struct work_struct work; 462 struct safexcel_crypto_priv *priv; 463 int ring; 464 }; 465 466 struct safexcel_crypto_priv { 467 void __iomem *base; 468 struct device *dev; 469 struct clk *clk; 470 struct safexcel_config config; 471 472 /* context DMA pool */ 473 struct dma_pool *context_pool; 474 475 atomic_t ring_used; 476 477 struct { 478 spinlock_t lock; 479 spinlock_t egress_lock; 480 481 struct list_head list; 482 struct workqueue_struct *workqueue; 483 struct safexcel_work_data work_data; 484 485 /* command/result rings */ 486 struct safexcel_ring cdr; 487 struct safexcel_ring rdr; 488 489 /* queue */ 490 struct crypto_queue queue; 491 spinlock_t queue_lock; 492 bool need_dequeue; 493 } ring[EIP197_MAX_RINGS]; 494 }; 495 496 struct safexcel_context { 497 int (*send)(struct crypto_async_request *req, int ring, 498 struct safexcel_request *request, int *commands, 499 int *results); 500 int (*handle_result)(struct safexcel_crypto_priv *priv, int ring, 501 struct crypto_async_request *req, bool *complete, 502 int *ret); 503 struct safexcel_context_record *ctxr; 504 dma_addr_t ctxr_dma; 505 506 int ring; 507 bool needs_inv; 508 bool exit_inv; 509 510 /* Used for ahash requests */ 511 dma_addr_t result_dma; 512 void *cache; 513 dma_addr_t cache_dma; 514 unsigned int cache_sz; 515 }; 516 517 /* 518 * Template structure to describe the algorithms in order to register them. 519 * It also has the purpose to contain our private structure and is actually 520 * the only way I know in this framework to avoid having global pointers... 521 */ 522 struct safexcel_alg_template { 523 struct safexcel_crypto_priv *priv; 524 enum safexcel_alg_type type; 525 union { 526 struct skcipher_alg skcipher; 527 struct ahash_alg ahash; 528 } alg; 529 }; 530 531 struct safexcel_inv_result { 532 struct completion completion; 533 int error; 534 }; 535 536 void safexcel_dequeue(struct safexcel_crypto_priv *priv, int ring); 537 void safexcel_complete(struct safexcel_crypto_priv *priv, int ring); 538 void safexcel_free_context(struct safexcel_crypto_priv *priv, 539 struct crypto_async_request *req, 540 int result_sz); 541 int safexcel_invalidate_cache(struct crypto_async_request *async, 542 struct safexcel_context *ctx, 543 struct safexcel_crypto_priv *priv, 544 dma_addr_t ctxr_dma, int ring, 545 struct safexcel_request *request); 546 int safexcel_init_ring_descriptors(struct safexcel_crypto_priv *priv, 547 struct safexcel_ring *cdr, 548 struct safexcel_ring *rdr); 549 int safexcel_select_ring(struct safexcel_crypto_priv *priv); 550 void *safexcel_ring_next_rptr(struct safexcel_crypto_priv *priv, 551 struct safexcel_ring *ring); 552 void safexcel_ring_rollback_wptr(struct safexcel_crypto_priv *priv, 553 struct safexcel_ring *ring); 554 struct safexcel_command_desc *safexcel_add_cdesc(struct safexcel_crypto_priv *priv, 555 int ring_id, 556 bool first, bool last, 557 dma_addr_t data, u32 len, 558 u32 full_data_len, 559 dma_addr_t context); 560 struct safexcel_result_desc *safexcel_add_rdesc(struct safexcel_crypto_priv *priv, 561 int ring_id, 562 bool first, bool last, 563 dma_addr_t data, u32 len); 564 void safexcel_inv_complete(struct crypto_async_request *req, int error); 565 566 /* available algorithms */ 567 extern struct safexcel_alg_template safexcel_alg_ecb_aes; 568 extern struct safexcel_alg_template safexcel_alg_cbc_aes; 569 extern struct safexcel_alg_template safexcel_alg_sha1; 570 extern struct safexcel_alg_template safexcel_alg_sha224; 571 extern struct safexcel_alg_template safexcel_alg_sha256; 572 extern struct safexcel_alg_template safexcel_alg_hmac_sha1; 573 574 #endif 575