1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2019 HiSilicon Limited. */ 3 #include <linux/acpi.h> 4 #include <linux/aer.h> 5 #include <linux/bitops.h> 6 #include <linux/debugfs.h> 7 #include <linux/init.h> 8 #include <linux/io.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/seq_file.h> 13 #include <linux/topology.h> 14 #include <linux/uacce.h> 15 #include "zip.h" 16 17 #define PCI_DEVICE_ID_ZIP_PF 0xa250 18 #define PCI_DEVICE_ID_ZIP_VF 0xa251 19 20 #define HZIP_QUEUE_NUM_V1 4096 21 22 #define HZIP_CLOCK_GATE_CTRL 0x301004 23 #define COMP0_ENABLE BIT(0) 24 #define COMP1_ENABLE BIT(1) 25 #define DECOMP0_ENABLE BIT(2) 26 #define DECOMP1_ENABLE BIT(3) 27 #define DECOMP2_ENABLE BIT(4) 28 #define DECOMP3_ENABLE BIT(5) 29 #define DECOMP4_ENABLE BIT(6) 30 #define DECOMP5_ENABLE BIT(7) 31 #define HZIP_ALL_COMP_DECOMP_EN (COMP0_ENABLE | COMP1_ENABLE | \ 32 DECOMP0_ENABLE | DECOMP1_ENABLE | \ 33 DECOMP2_ENABLE | DECOMP3_ENABLE | \ 34 DECOMP4_ENABLE | DECOMP5_ENABLE) 35 #define HZIP_DECOMP_CHECK_ENABLE BIT(16) 36 #define HZIP_FSM_MAX_CNT 0x301008 37 38 #define HZIP_PORT_ARCA_CHE_0 0x301040 39 #define HZIP_PORT_ARCA_CHE_1 0x301044 40 #define HZIP_PORT_AWCA_CHE_0 0x301060 41 #define HZIP_PORT_AWCA_CHE_1 0x301064 42 #define HZIP_CACHE_ALL_EN 0xffffffff 43 44 #define HZIP_BD_RUSER_32_63 0x301110 45 #define HZIP_SGL_RUSER_32_63 0x30111c 46 #define HZIP_DATA_RUSER_32_63 0x301128 47 #define HZIP_DATA_WUSER_32_63 0x301134 48 #define HZIP_BD_WUSER_32_63 0x301140 49 50 #define HZIP_QM_IDEL_STATUS 0x3040e4 51 52 #define HZIP_CORE_DEBUG_COMP_0 0x302000 53 #define HZIP_CORE_DEBUG_COMP_1 0x303000 54 #define HZIP_CORE_DEBUG_DECOMP_0 0x304000 55 #define HZIP_CORE_DEBUG_DECOMP_1 0x305000 56 #define HZIP_CORE_DEBUG_DECOMP_2 0x306000 57 #define HZIP_CORE_DEBUG_DECOMP_3 0x307000 58 #define HZIP_CORE_DEBUG_DECOMP_4 0x308000 59 #define HZIP_CORE_DEBUG_DECOMP_5 0x309000 60 61 #define HZIP_CORE_INT_SOURCE 0x3010A0 62 #define HZIP_CORE_INT_MASK_REG 0x3010A4 63 #define HZIP_CORE_INT_SET 0x3010A8 64 #define HZIP_CORE_INT_STATUS 0x3010AC 65 #define HZIP_CORE_INT_STATUS_M_ECC BIT(1) 66 #define HZIP_CORE_SRAM_ECC_ERR_INFO 0x301148 67 #define HZIP_CORE_INT_RAS_CE_ENB 0x301160 68 #define HZIP_CORE_INT_RAS_CE_ENABLE 0x1 69 #define HZIP_CORE_INT_RAS_NFE_ENB 0x301164 70 #define HZIP_CORE_INT_RAS_FE_ENB 0x301168 71 #define HZIP_CORE_INT_RAS_NFE_ENABLE 0x7FE 72 #define HZIP_SRAM_ECC_ERR_NUM_SHIFT 16 73 #define HZIP_SRAM_ECC_ERR_ADDR_SHIFT 24 74 #define HZIP_CORE_INT_MASK_ALL GENMASK(10, 0) 75 #define HZIP_COMP_CORE_NUM 2 76 #define HZIP_DECOMP_CORE_NUM 6 77 #define HZIP_CORE_NUM (HZIP_COMP_CORE_NUM + \ 78 HZIP_DECOMP_CORE_NUM) 79 #define HZIP_SQE_SIZE 128 80 #define HZIP_SQ_SIZE (HZIP_SQE_SIZE * QM_Q_DEPTH) 81 #define HZIP_PF_DEF_Q_NUM 64 82 #define HZIP_PF_DEF_Q_BASE 0 83 84 #define HZIP_SOFT_CTRL_CNT_CLR_CE 0x301000 85 #define HZIP_SOFT_CTRL_CNT_CLR_CE_BIT BIT(0) 86 #define HZIP_SOFT_CTRL_ZIP_CONTROL 0x30100C 87 #define HZIP_AXI_SHUTDOWN_ENABLE BIT(14) 88 #define HZIP_WR_PORT BIT(11) 89 90 #define HZIP_BUF_SIZE 22 91 #define HZIP_SQE_MASK_OFFSET 64 92 #define HZIP_SQE_MASK_LEN 48 93 94 #define HZIP_CNT_CLR_CE_EN BIT(0) 95 #define HZIP_RO_CNT_CLR_CE_EN BIT(2) 96 #define HZIP_RD_CNT_CLR_CE_EN (HZIP_CNT_CLR_CE_EN | \ 97 HZIP_RO_CNT_CLR_CE_EN) 98 99 static const char hisi_zip_name[] = "hisi_zip"; 100 static struct dentry *hzip_debugfs_root; 101 102 struct hisi_zip_hw_error { 103 u32 int_msk; 104 const char *msg; 105 }; 106 107 struct zip_dfx_item { 108 const char *name; 109 u32 offset; 110 }; 111 112 static struct hisi_qm_list zip_devices = { 113 .register_to_crypto = hisi_zip_register_to_crypto, 114 .unregister_from_crypto = hisi_zip_unregister_from_crypto, 115 }; 116 117 static struct zip_dfx_item zip_dfx_files[] = { 118 {"send_cnt", offsetof(struct hisi_zip_dfx, send_cnt)}, 119 {"recv_cnt", offsetof(struct hisi_zip_dfx, recv_cnt)}, 120 {"send_busy_cnt", offsetof(struct hisi_zip_dfx, send_busy_cnt)}, 121 {"err_bd_cnt", offsetof(struct hisi_zip_dfx, err_bd_cnt)}, 122 }; 123 124 static const struct hisi_zip_hw_error zip_hw_error[] = { 125 { .int_msk = BIT(0), .msg = "zip_ecc_1bitt_err" }, 126 { .int_msk = BIT(1), .msg = "zip_ecc_2bit_err" }, 127 { .int_msk = BIT(2), .msg = "zip_axi_rresp_err" }, 128 { .int_msk = BIT(3), .msg = "zip_axi_bresp_err" }, 129 { .int_msk = BIT(4), .msg = "zip_src_addr_parse_err" }, 130 { .int_msk = BIT(5), .msg = "zip_dst_addr_parse_err" }, 131 { .int_msk = BIT(6), .msg = "zip_pre_in_addr_err" }, 132 { .int_msk = BIT(7), .msg = "zip_pre_in_data_err" }, 133 { .int_msk = BIT(8), .msg = "zip_com_inf_err" }, 134 { .int_msk = BIT(9), .msg = "zip_enc_inf_err" }, 135 { .int_msk = BIT(10), .msg = "zip_pre_out_err" }, 136 { /* sentinel */ } 137 }; 138 139 enum ctrl_debug_file_index { 140 HZIP_CLEAR_ENABLE, 141 HZIP_DEBUG_FILE_NUM, 142 }; 143 144 static const char * const ctrl_debug_file_name[] = { 145 [HZIP_CLEAR_ENABLE] = "clear_enable", 146 }; 147 148 struct ctrl_debug_file { 149 enum ctrl_debug_file_index index; 150 spinlock_t lock; 151 struct hisi_zip_ctrl *ctrl; 152 }; 153 154 /* 155 * One ZIP controller has one PF and multiple VFs, some global configurations 156 * which PF has need this structure. 157 * 158 * Just relevant for PF. 159 */ 160 struct hisi_zip_ctrl { 161 struct hisi_zip *hisi_zip; 162 struct ctrl_debug_file files[HZIP_DEBUG_FILE_NUM]; 163 }; 164 165 enum { 166 HZIP_COMP_CORE0, 167 HZIP_COMP_CORE1, 168 HZIP_DECOMP_CORE0, 169 HZIP_DECOMP_CORE1, 170 HZIP_DECOMP_CORE2, 171 HZIP_DECOMP_CORE3, 172 HZIP_DECOMP_CORE4, 173 HZIP_DECOMP_CORE5, 174 }; 175 176 static const u64 core_offsets[] = { 177 [HZIP_COMP_CORE0] = 0x302000, 178 [HZIP_COMP_CORE1] = 0x303000, 179 [HZIP_DECOMP_CORE0] = 0x304000, 180 [HZIP_DECOMP_CORE1] = 0x305000, 181 [HZIP_DECOMP_CORE2] = 0x306000, 182 [HZIP_DECOMP_CORE3] = 0x307000, 183 [HZIP_DECOMP_CORE4] = 0x308000, 184 [HZIP_DECOMP_CORE5] = 0x309000, 185 }; 186 187 static const struct debugfs_reg32 hzip_dfx_regs[] = { 188 {"HZIP_GET_BD_NUM ", 0x00ull}, 189 {"HZIP_GET_RIGHT_BD ", 0x04ull}, 190 {"HZIP_GET_ERROR_BD ", 0x08ull}, 191 {"HZIP_DONE_BD_NUM ", 0x0cull}, 192 {"HZIP_WORK_CYCLE ", 0x10ull}, 193 {"HZIP_IDLE_CYCLE ", 0x18ull}, 194 {"HZIP_MAX_DELAY ", 0x20ull}, 195 {"HZIP_MIN_DELAY ", 0x24ull}, 196 {"HZIP_AVG_DELAY ", 0x28ull}, 197 {"HZIP_MEM_VISIBLE_DATA ", 0x30ull}, 198 {"HZIP_MEM_VISIBLE_ADDR ", 0x34ull}, 199 {"HZIP_COMSUMED_BYTE ", 0x38ull}, 200 {"HZIP_PRODUCED_BYTE ", 0x40ull}, 201 {"HZIP_COMP_INF ", 0x70ull}, 202 {"HZIP_PRE_OUT ", 0x78ull}, 203 {"HZIP_BD_RD ", 0x7cull}, 204 {"HZIP_BD_WR ", 0x80ull}, 205 {"HZIP_GET_BD_AXI_ERR_NUM ", 0x84ull}, 206 {"HZIP_GET_BD_PARSE_ERR_NUM ", 0x88ull}, 207 {"HZIP_ADD_BD_AXI_ERR_NUM ", 0x8cull}, 208 {"HZIP_DECOMP_STF_RELOAD_CURR_ST ", 0x94ull}, 209 {"HZIP_DECOMP_LZ77_CURR_ST ", 0x9cull}, 210 }; 211 212 static const struct kernel_param_ops zip_uacce_mode_ops = { 213 .set = uacce_mode_set, 214 .get = param_get_int, 215 }; 216 217 /* 218 * uacce_mode = 0 means zip only register to crypto, 219 * uacce_mode = 1 means zip both register to crypto and uacce. 220 */ 221 static u32 uacce_mode = UACCE_MODE_NOUACCE; 222 module_param_cb(uacce_mode, &zip_uacce_mode_ops, &uacce_mode, 0444); 223 MODULE_PARM_DESC(uacce_mode, UACCE_MODE_DESC); 224 225 static int pf_q_num_set(const char *val, const struct kernel_param *kp) 226 { 227 return q_num_set(val, kp, PCI_DEVICE_ID_ZIP_PF); 228 } 229 230 static const struct kernel_param_ops pf_q_num_ops = { 231 .set = pf_q_num_set, 232 .get = param_get_int, 233 }; 234 235 static u32 pf_q_num = HZIP_PF_DEF_Q_NUM; 236 module_param_cb(pf_q_num, &pf_q_num_ops, &pf_q_num, 0444); 237 MODULE_PARM_DESC(pf_q_num, "Number of queues in PF(v1 2-4096, v2 2-1024)"); 238 239 static const struct kernel_param_ops vfs_num_ops = { 240 .set = vfs_num_set, 241 .get = param_get_int, 242 }; 243 244 static u32 vfs_num; 245 module_param_cb(vfs_num, &vfs_num_ops, &vfs_num, 0444); 246 MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)"); 247 248 static const struct pci_device_id hisi_zip_dev_ids[] = { 249 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_ZIP_PF) }, 250 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_ZIP_VF) }, 251 { 0, } 252 }; 253 MODULE_DEVICE_TABLE(pci, hisi_zip_dev_ids); 254 255 int zip_create_qps(struct hisi_qp **qps, int qp_num, int node) 256 { 257 if (node == NUMA_NO_NODE) 258 node = cpu_to_node(smp_processor_id()); 259 260 return hisi_qm_alloc_qps_node(&zip_devices, qp_num, 0, node, qps); 261 } 262 263 static int hisi_zip_set_user_domain_and_cache(struct hisi_qm *qm) 264 { 265 void __iomem *base = qm->io_base; 266 267 /* qm user domain */ 268 writel(AXUSER_BASE, base + QM_ARUSER_M_CFG_1); 269 writel(ARUSER_M_CFG_ENABLE, base + QM_ARUSER_M_CFG_ENABLE); 270 writel(AXUSER_BASE, base + QM_AWUSER_M_CFG_1); 271 writel(AWUSER_M_CFG_ENABLE, base + QM_AWUSER_M_CFG_ENABLE); 272 writel(WUSER_M_CFG_ENABLE, base + QM_WUSER_M_CFG_ENABLE); 273 274 /* qm cache */ 275 writel(AXI_M_CFG, base + QM_AXI_M_CFG); 276 writel(AXI_M_CFG_ENABLE, base + QM_AXI_M_CFG_ENABLE); 277 278 /* disable FLR triggered by BME(bus master enable) */ 279 writel(PEH_AXUSER_CFG, base + QM_PEH_AXUSER_CFG); 280 writel(PEH_AXUSER_CFG_ENABLE, base + QM_PEH_AXUSER_CFG_ENABLE); 281 282 /* cache */ 283 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_ARCA_CHE_0); 284 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_ARCA_CHE_1); 285 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_AWCA_CHE_0); 286 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_AWCA_CHE_1); 287 288 /* user domain configurations */ 289 writel(AXUSER_BASE, base + HZIP_BD_RUSER_32_63); 290 writel(AXUSER_BASE, base + HZIP_SGL_RUSER_32_63); 291 writel(AXUSER_BASE, base + HZIP_BD_WUSER_32_63); 292 293 if (qm->use_sva && qm->ver == QM_HW_V2) { 294 writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_DATA_RUSER_32_63); 295 writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_DATA_WUSER_32_63); 296 } else { 297 writel(AXUSER_BASE, base + HZIP_DATA_RUSER_32_63); 298 writel(AXUSER_BASE, base + HZIP_DATA_WUSER_32_63); 299 } 300 301 /* let's open all compression/decompression cores */ 302 writel(HZIP_DECOMP_CHECK_ENABLE | HZIP_ALL_COMP_DECOMP_EN, 303 base + HZIP_CLOCK_GATE_CTRL); 304 305 /* enable sqc,cqc writeback */ 306 writel(SQC_CACHE_ENABLE | CQC_CACHE_ENABLE | SQC_CACHE_WB_ENABLE | 307 CQC_CACHE_WB_ENABLE | FIELD_PREP(SQC_CACHE_WB_THRD, 1) | 308 FIELD_PREP(CQC_CACHE_WB_THRD, 1), base + QM_CACHE_CTL); 309 310 return 0; 311 } 312 313 static void hisi_zip_hw_error_enable(struct hisi_qm *qm) 314 { 315 u32 val; 316 317 if (qm->ver == QM_HW_V1) { 318 writel(HZIP_CORE_INT_MASK_ALL, 319 qm->io_base + HZIP_CORE_INT_MASK_REG); 320 dev_info(&qm->pdev->dev, "Does not support hw error handle\n"); 321 return; 322 } 323 324 /* clear ZIP hw error source if having */ 325 writel(HZIP_CORE_INT_MASK_ALL, qm->io_base + HZIP_CORE_INT_SOURCE); 326 327 /* configure error type */ 328 writel(HZIP_CORE_INT_RAS_CE_ENABLE, 329 qm->io_base + HZIP_CORE_INT_RAS_CE_ENB); 330 writel(0x0, qm->io_base + HZIP_CORE_INT_RAS_FE_ENB); 331 writel(HZIP_CORE_INT_RAS_NFE_ENABLE, 332 qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 333 334 /* enable ZIP hw error interrupts */ 335 writel(0, qm->io_base + HZIP_CORE_INT_MASK_REG); 336 337 /* enable ZIP block master OOO when m-bit error occur */ 338 val = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 339 val = val | HZIP_AXI_SHUTDOWN_ENABLE; 340 writel(val, qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 341 } 342 343 static void hisi_zip_hw_error_disable(struct hisi_qm *qm) 344 { 345 u32 val; 346 347 /* disable ZIP hw error interrupts */ 348 writel(HZIP_CORE_INT_MASK_ALL, qm->io_base + HZIP_CORE_INT_MASK_REG); 349 350 /* disable ZIP block master OOO when m-bit error occur */ 351 val = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 352 val = val & ~HZIP_AXI_SHUTDOWN_ENABLE; 353 writel(val, qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 354 } 355 356 static inline struct hisi_qm *file_to_qm(struct ctrl_debug_file *file) 357 { 358 struct hisi_zip *hisi_zip = file->ctrl->hisi_zip; 359 360 return &hisi_zip->qm; 361 } 362 363 static u32 clear_enable_read(struct ctrl_debug_file *file) 364 { 365 struct hisi_qm *qm = file_to_qm(file); 366 367 return readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) & 368 HZIP_SOFT_CTRL_CNT_CLR_CE_BIT; 369 } 370 371 static int clear_enable_write(struct ctrl_debug_file *file, u32 val) 372 { 373 struct hisi_qm *qm = file_to_qm(file); 374 u32 tmp; 375 376 if (val != 1 && val != 0) 377 return -EINVAL; 378 379 tmp = (readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) & 380 ~HZIP_SOFT_CTRL_CNT_CLR_CE_BIT) | val; 381 writel(tmp, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE); 382 383 return 0; 384 } 385 386 static ssize_t hisi_zip_ctrl_debug_read(struct file *filp, char __user *buf, 387 size_t count, loff_t *pos) 388 { 389 struct ctrl_debug_file *file = filp->private_data; 390 char tbuf[HZIP_BUF_SIZE]; 391 u32 val; 392 int ret; 393 394 spin_lock_irq(&file->lock); 395 switch (file->index) { 396 case HZIP_CLEAR_ENABLE: 397 val = clear_enable_read(file); 398 break; 399 default: 400 spin_unlock_irq(&file->lock); 401 return -EINVAL; 402 } 403 spin_unlock_irq(&file->lock); 404 ret = scnprintf(tbuf, sizeof(tbuf), "%u\n", val); 405 return simple_read_from_buffer(buf, count, pos, tbuf, ret); 406 } 407 408 static ssize_t hisi_zip_ctrl_debug_write(struct file *filp, 409 const char __user *buf, 410 size_t count, loff_t *pos) 411 { 412 struct ctrl_debug_file *file = filp->private_data; 413 char tbuf[HZIP_BUF_SIZE]; 414 unsigned long val; 415 int len, ret; 416 417 if (*pos != 0) 418 return 0; 419 420 if (count >= HZIP_BUF_SIZE) 421 return -ENOSPC; 422 423 len = simple_write_to_buffer(tbuf, HZIP_BUF_SIZE - 1, pos, buf, count); 424 if (len < 0) 425 return len; 426 427 tbuf[len] = '\0'; 428 if (kstrtoul(tbuf, 0, &val)) 429 return -EFAULT; 430 431 spin_lock_irq(&file->lock); 432 switch (file->index) { 433 case HZIP_CLEAR_ENABLE: 434 ret = clear_enable_write(file, val); 435 if (ret) 436 goto err_input; 437 break; 438 default: 439 ret = -EINVAL; 440 goto err_input; 441 } 442 spin_unlock_irq(&file->lock); 443 444 return count; 445 446 err_input: 447 spin_unlock_irq(&file->lock); 448 return ret; 449 } 450 451 static const struct file_operations ctrl_debug_fops = { 452 .owner = THIS_MODULE, 453 .open = simple_open, 454 .read = hisi_zip_ctrl_debug_read, 455 .write = hisi_zip_ctrl_debug_write, 456 }; 457 458 static int zip_debugfs_atomic64_set(void *data, u64 val) 459 { 460 if (val) 461 return -EINVAL; 462 463 atomic64_set((atomic64_t *)data, 0); 464 465 return 0; 466 } 467 468 static int zip_debugfs_atomic64_get(void *data, u64 *val) 469 { 470 *val = atomic64_read((atomic64_t *)data); 471 472 return 0; 473 } 474 475 DEFINE_DEBUGFS_ATTRIBUTE(zip_atomic64_ops, zip_debugfs_atomic64_get, 476 zip_debugfs_atomic64_set, "%llu\n"); 477 478 static int hisi_zip_core_debug_init(struct hisi_qm *qm) 479 { 480 struct device *dev = &qm->pdev->dev; 481 struct debugfs_regset32 *regset; 482 struct dentry *tmp_d; 483 char buf[HZIP_BUF_SIZE]; 484 int i; 485 486 for (i = 0; i < HZIP_CORE_NUM; i++) { 487 if (i < HZIP_COMP_CORE_NUM) 488 scnprintf(buf, sizeof(buf), "comp_core%d", i); 489 else 490 scnprintf(buf, sizeof(buf), "decomp_core%d", 491 i - HZIP_COMP_CORE_NUM); 492 493 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 494 if (!regset) 495 return -ENOENT; 496 497 regset->regs = hzip_dfx_regs; 498 regset->nregs = ARRAY_SIZE(hzip_dfx_regs); 499 regset->base = qm->io_base + core_offsets[i]; 500 501 tmp_d = debugfs_create_dir(buf, qm->debug.debug_root); 502 debugfs_create_regset32("regs", 0444, tmp_d, regset); 503 } 504 505 return 0; 506 } 507 508 static void hisi_zip_dfx_debug_init(struct hisi_qm *qm) 509 { 510 struct hisi_zip *zip = container_of(qm, struct hisi_zip, qm); 511 struct hisi_zip_dfx *dfx = &zip->dfx; 512 struct dentry *tmp_dir; 513 void *data; 514 int i; 515 516 tmp_dir = debugfs_create_dir("zip_dfx", qm->debug.debug_root); 517 for (i = 0; i < ARRAY_SIZE(zip_dfx_files); i++) { 518 data = (atomic64_t *)((uintptr_t)dfx + zip_dfx_files[i].offset); 519 debugfs_create_file(zip_dfx_files[i].name, 520 0644, tmp_dir, data, 521 &zip_atomic64_ops); 522 } 523 } 524 525 static int hisi_zip_ctrl_debug_init(struct hisi_qm *qm) 526 { 527 struct hisi_zip *zip = container_of(qm, struct hisi_zip, qm); 528 int i; 529 530 for (i = HZIP_CLEAR_ENABLE; i < HZIP_DEBUG_FILE_NUM; i++) { 531 spin_lock_init(&zip->ctrl->files[i].lock); 532 zip->ctrl->files[i].ctrl = zip->ctrl; 533 zip->ctrl->files[i].index = i; 534 535 debugfs_create_file(ctrl_debug_file_name[i], 0600, 536 qm->debug.debug_root, 537 zip->ctrl->files + i, 538 &ctrl_debug_fops); 539 } 540 541 return hisi_zip_core_debug_init(qm); 542 } 543 544 static int hisi_zip_debugfs_init(struct hisi_qm *qm) 545 { 546 struct device *dev = &qm->pdev->dev; 547 struct dentry *dev_d; 548 int ret; 549 550 dev_d = debugfs_create_dir(dev_name(dev), hzip_debugfs_root); 551 552 qm->debug.sqe_mask_offset = HZIP_SQE_MASK_OFFSET; 553 qm->debug.sqe_mask_len = HZIP_SQE_MASK_LEN; 554 qm->debug.debug_root = dev_d; 555 hisi_qm_debug_init(qm); 556 557 if (qm->fun_type == QM_HW_PF) { 558 ret = hisi_zip_ctrl_debug_init(qm); 559 if (ret) 560 goto failed_to_create; 561 } 562 563 hisi_zip_dfx_debug_init(qm); 564 565 return 0; 566 567 failed_to_create: 568 debugfs_remove_recursive(hzip_debugfs_root); 569 return ret; 570 } 571 572 /* hisi_zip_debug_regs_clear() - clear the zip debug regs */ 573 static void hisi_zip_debug_regs_clear(struct hisi_qm *qm) 574 { 575 int i, j; 576 577 /* enable register read_clear bit */ 578 writel(HZIP_RD_CNT_CLR_CE_EN, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE); 579 for (i = 0; i < ARRAY_SIZE(core_offsets); i++) 580 for (j = 0; j < ARRAY_SIZE(hzip_dfx_regs); j++) 581 readl(qm->io_base + core_offsets[i] + 582 hzip_dfx_regs[j].offset); 583 584 /* disable register read_clear bit */ 585 writel(0x0, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE); 586 587 hisi_qm_debug_regs_clear(qm); 588 } 589 590 static void hisi_zip_debugfs_exit(struct hisi_qm *qm) 591 { 592 debugfs_remove_recursive(qm->debug.debug_root); 593 594 if (qm->fun_type == QM_HW_PF) { 595 hisi_zip_debug_regs_clear(qm); 596 qm->debug.curr_qm_qp_num = 0; 597 } 598 } 599 600 static void hisi_zip_log_hw_error(struct hisi_qm *qm, u32 err_sts) 601 { 602 const struct hisi_zip_hw_error *err = zip_hw_error; 603 struct device *dev = &qm->pdev->dev; 604 u32 err_val; 605 606 while (err->msg) { 607 if (err->int_msk & err_sts) { 608 dev_err(dev, "%s [error status=0x%x] found\n", 609 err->msg, err->int_msk); 610 611 if (err->int_msk & HZIP_CORE_INT_STATUS_M_ECC) { 612 err_val = readl(qm->io_base + 613 HZIP_CORE_SRAM_ECC_ERR_INFO); 614 dev_err(dev, "hisi-zip multi ecc sram num=0x%x\n", 615 ((err_val >> 616 HZIP_SRAM_ECC_ERR_NUM_SHIFT) & 0xFF)); 617 } 618 } 619 err++; 620 } 621 } 622 623 static u32 hisi_zip_get_hw_err_status(struct hisi_qm *qm) 624 { 625 return readl(qm->io_base + HZIP_CORE_INT_STATUS); 626 } 627 628 static void hisi_zip_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts) 629 { 630 writel(err_sts, qm->io_base + HZIP_CORE_INT_SOURCE); 631 } 632 633 static void hisi_zip_open_axi_master_ooo(struct hisi_qm *qm) 634 { 635 u32 val; 636 637 val = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 638 639 writel(val & ~HZIP_AXI_SHUTDOWN_ENABLE, 640 qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 641 642 writel(val | HZIP_AXI_SHUTDOWN_ENABLE, 643 qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 644 } 645 646 static void hisi_zip_close_axi_master_ooo(struct hisi_qm *qm) 647 { 648 u32 nfe_enb; 649 650 /* Disable ECC Mbit error report. */ 651 nfe_enb = readl(qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 652 writel(nfe_enb & ~HZIP_CORE_INT_STATUS_M_ECC, 653 qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 654 655 /* Inject zip ECC Mbit error to block master ooo. */ 656 writel(HZIP_CORE_INT_STATUS_M_ECC, 657 qm->io_base + HZIP_CORE_INT_SET); 658 } 659 660 static const struct hisi_qm_err_ini hisi_zip_err_ini = { 661 .hw_init = hisi_zip_set_user_domain_and_cache, 662 .hw_err_enable = hisi_zip_hw_error_enable, 663 .hw_err_disable = hisi_zip_hw_error_disable, 664 .get_dev_hw_err_status = hisi_zip_get_hw_err_status, 665 .clear_dev_hw_err_status = hisi_zip_clear_hw_err_status, 666 .log_dev_hw_err = hisi_zip_log_hw_error, 667 .open_axi_master_ooo = hisi_zip_open_axi_master_ooo, 668 .close_axi_master_ooo = hisi_zip_close_axi_master_ooo, 669 .err_info = { 670 .ce = QM_BASE_CE, 671 .nfe = QM_BASE_NFE | 672 QM_ACC_WB_NOT_READY_TIMEOUT, 673 .fe = 0, 674 .ecc_2bits_mask = HZIP_CORE_INT_STATUS_M_ECC, 675 .dev_ce_mask = HZIP_CORE_INT_RAS_CE_ENABLE, 676 .msi_wr_port = HZIP_WR_PORT, 677 .acpi_rst = "ZRST", 678 } 679 }; 680 681 static int hisi_zip_pf_probe_init(struct hisi_zip *hisi_zip) 682 { 683 struct hisi_qm *qm = &hisi_zip->qm; 684 struct hisi_zip_ctrl *ctrl; 685 686 ctrl = devm_kzalloc(&qm->pdev->dev, sizeof(*ctrl), GFP_KERNEL); 687 if (!ctrl) 688 return -ENOMEM; 689 690 hisi_zip->ctrl = ctrl; 691 ctrl->hisi_zip = hisi_zip; 692 qm->err_ini = &hisi_zip_err_ini; 693 694 hisi_zip_set_user_domain_and_cache(qm); 695 hisi_qm_dev_err_init(qm); 696 hisi_zip_debug_regs_clear(qm); 697 698 return 0; 699 } 700 701 static int hisi_zip_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) 702 { 703 int ret; 704 705 qm->pdev = pdev; 706 qm->ver = pdev->revision; 707 qm->algs = "zlib\ngzip"; 708 qm->mode = uacce_mode; 709 qm->sqe_size = HZIP_SQE_SIZE; 710 qm->dev_name = hisi_zip_name; 711 712 qm->fun_type = (pdev->device == PCI_DEVICE_ID_ZIP_PF) ? 713 QM_HW_PF : QM_HW_VF; 714 if (qm->fun_type == QM_HW_PF) { 715 qm->qp_base = HZIP_PF_DEF_Q_BASE; 716 qm->qp_num = pf_q_num; 717 qm->debug.curr_qm_qp_num = pf_q_num; 718 qm->qm_list = &zip_devices; 719 } else if (qm->fun_type == QM_HW_VF && qm->ver == QM_HW_V1) { 720 /* 721 * have no way to get qm configure in VM in v1 hardware, 722 * so currently force PF to uses HZIP_PF_DEF_Q_NUM, and force 723 * to trigger only one VF in v1 hardware. 724 * 725 * v2 hardware has no such problem. 726 */ 727 qm->qp_base = HZIP_PF_DEF_Q_NUM; 728 qm->qp_num = HZIP_QUEUE_NUM_V1 - HZIP_PF_DEF_Q_NUM; 729 } 730 731 qm->wq = alloc_workqueue("%s", WQ_HIGHPRI | WQ_MEM_RECLAIM | 732 WQ_UNBOUND, num_online_cpus(), 733 pci_name(qm->pdev)); 734 if (!qm->wq) { 735 pci_err(qm->pdev, "fail to alloc workqueue\n"); 736 return -ENOMEM; 737 } 738 739 ret = hisi_qm_init(qm); 740 if (ret) 741 destroy_workqueue(qm->wq); 742 743 return ret; 744 } 745 746 static void hisi_zip_qm_uninit(struct hisi_qm *qm) 747 { 748 hisi_qm_uninit(qm); 749 destroy_workqueue(qm->wq); 750 } 751 752 static int hisi_zip_probe_init(struct hisi_zip *hisi_zip) 753 { 754 struct hisi_qm *qm = &hisi_zip->qm; 755 int ret; 756 757 if (qm->fun_type == QM_HW_PF) { 758 ret = hisi_zip_pf_probe_init(hisi_zip); 759 if (ret) 760 return ret; 761 } 762 763 return 0; 764 } 765 766 static int hisi_zip_probe(struct pci_dev *pdev, const struct pci_device_id *id) 767 { 768 struct hisi_zip *hisi_zip; 769 struct hisi_qm *qm; 770 int ret; 771 772 hisi_zip = devm_kzalloc(&pdev->dev, sizeof(*hisi_zip), GFP_KERNEL); 773 if (!hisi_zip) 774 return -ENOMEM; 775 776 qm = &hisi_zip->qm; 777 778 ret = hisi_zip_qm_init(qm, pdev); 779 if (ret) { 780 pci_err(pdev, "Failed to init ZIP QM (%d)!\n", ret); 781 return ret; 782 } 783 784 ret = hisi_zip_probe_init(hisi_zip); 785 if (ret) { 786 pci_err(pdev, "Failed to probe (%d)!\n", ret); 787 goto err_qm_uninit; 788 } 789 790 ret = hisi_qm_start(qm); 791 if (ret) 792 goto err_dev_err_uninit; 793 794 ret = hisi_zip_debugfs_init(qm); 795 if (ret) 796 pci_err(pdev, "failed to init debugfs (%d)!\n", ret); 797 798 ret = hisi_qm_alg_register(qm, &zip_devices); 799 if (ret < 0) { 800 pci_err(pdev, "failed to register driver to crypto!\n"); 801 goto err_qm_stop; 802 } 803 804 if (qm->uacce) { 805 ret = uacce_register(qm->uacce); 806 if (ret) { 807 pci_err(pdev, "failed to register uacce (%d)!\n", ret); 808 goto err_qm_alg_unregister; 809 } 810 } 811 812 if (qm->fun_type == QM_HW_PF && vfs_num > 0) { 813 ret = hisi_qm_sriov_enable(pdev, vfs_num); 814 if (ret < 0) 815 goto err_qm_alg_unregister; 816 } 817 818 return 0; 819 820 err_qm_alg_unregister: 821 hisi_qm_alg_unregister(qm, &zip_devices); 822 823 err_qm_stop: 824 hisi_zip_debugfs_exit(qm); 825 hisi_qm_stop(qm, QM_NORMAL); 826 827 err_dev_err_uninit: 828 hisi_qm_dev_err_uninit(qm); 829 830 err_qm_uninit: 831 hisi_zip_qm_uninit(qm); 832 833 return ret; 834 } 835 836 static void hisi_zip_remove(struct pci_dev *pdev) 837 { 838 struct hisi_qm *qm = pci_get_drvdata(pdev); 839 840 hisi_qm_wait_task_finish(qm, &zip_devices); 841 hisi_qm_alg_unregister(qm, &zip_devices); 842 843 if (qm->fun_type == QM_HW_PF && qm->vfs_num) 844 hisi_qm_sriov_disable(pdev, true); 845 846 hisi_zip_debugfs_exit(qm); 847 hisi_qm_stop(qm, QM_NORMAL); 848 hisi_qm_dev_err_uninit(qm); 849 hisi_zip_qm_uninit(qm); 850 } 851 852 static const struct pci_error_handlers hisi_zip_err_handler = { 853 .error_detected = hisi_qm_dev_err_detected, 854 .slot_reset = hisi_qm_dev_slot_reset, 855 .reset_prepare = hisi_qm_reset_prepare, 856 .reset_done = hisi_qm_reset_done, 857 }; 858 859 static struct pci_driver hisi_zip_pci_driver = { 860 .name = "hisi_zip", 861 .id_table = hisi_zip_dev_ids, 862 .probe = hisi_zip_probe, 863 .remove = hisi_zip_remove, 864 .sriov_configure = IS_ENABLED(CONFIG_PCI_IOV) ? 865 hisi_qm_sriov_configure : NULL, 866 .err_handler = &hisi_zip_err_handler, 867 .shutdown = hisi_qm_dev_shutdown, 868 }; 869 870 static void hisi_zip_register_debugfs(void) 871 { 872 if (!debugfs_initialized()) 873 return; 874 875 hzip_debugfs_root = debugfs_create_dir("hisi_zip", NULL); 876 } 877 878 static void hisi_zip_unregister_debugfs(void) 879 { 880 debugfs_remove_recursive(hzip_debugfs_root); 881 } 882 883 static int __init hisi_zip_init(void) 884 { 885 int ret; 886 887 hisi_qm_init_list(&zip_devices); 888 hisi_zip_register_debugfs(); 889 890 ret = pci_register_driver(&hisi_zip_pci_driver); 891 if (ret < 0) { 892 hisi_zip_unregister_debugfs(); 893 pr_err("Failed to register pci driver.\n"); 894 } 895 896 return ret; 897 } 898 899 static void __exit hisi_zip_exit(void) 900 { 901 pci_unregister_driver(&hisi_zip_pci_driver); 902 hisi_zip_unregister_debugfs(); 903 } 904 905 module_init(hisi_zip_init); 906 module_exit(hisi_zip_exit); 907 908 MODULE_LICENSE("GPL v2"); 909 MODULE_AUTHOR("Zhou Wang <wangzhou1@hisilicon.com>"); 910 MODULE_DESCRIPTION("Driver for HiSilicon ZIP accelerator"); 911