1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2019 HiSilicon Limited. */ 3 #include <linux/acpi.h> 4 #include <linux/aer.h> 5 #include <linux/bitops.h> 6 #include <linux/debugfs.h> 7 #include <linux/init.h> 8 #include <linux/io.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/seq_file.h> 14 #include <linux/topology.h> 15 #include <linux/uacce.h> 16 #include "zip.h" 17 18 #define PCI_DEVICE_ID_ZIP_PF 0xa250 19 #define PCI_DEVICE_ID_ZIP_VF 0xa251 20 21 #define HZIP_QUEUE_NUM_V1 4096 22 23 #define HZIP_CLOCK_GATE_CTRL 0x301004 24 #define COMP0_ENABLE BIT(0) 25 #define COMP1_ENABLE BIT(1) 26 #define DECOMP0_ENABLE BIT(2) 27 #define DECOMP1_ENABLE BIT(3) 28 #define DECOMP2_ENABLE BIT(4) 29 #define DECOMP3_ENABLE BIT(5) 30 #define DECOMP4_ENABLE BIT(6) 31 #define DECOMP5_ENABLE BIT(7) 32 #define HZIP_ALL_COMP_DECOMP_EN (COMP0_ENABLE | COMP1_ENABLE | \ 33 DECOMP0_ENABLE | DECOMP1_ENABLE | \ 34 DECOMP2_ENABLE | DECOMP3_ENABLE | \ 35 DECOMP4_ENABLE | DECOMP5_ENABLE) 36 #define HZIP_DECOMP_CHECK_ENABLE BIT(16) 37 #define HZIP_FSM_MAX_CNT 0x301008 38 39 #define HZIP_PORT_ARCA_CHE_0 0x301040 40 #define HZIP_PORT_ARCA_CHE_1 0x301044 41 #define HZIP_PORT_AWCA_CHE_0 0x301060 42 #define HZIP_PORT_AWCA_CHE_1 0x301064 43 #define HZIP_CACHE_ALL_EN 0xffffffff 44 45 #define HZIP_BD_RUSER_32_63 0x301110 46 #define HZIP_SGL_RUSER_32_63 0x30111c 47 #define HZIP_DATA_RUSER_32_63 0x301128 48 #define HZIP_DATA_WUSER_32_63 0x301134 49 #define HZIP_BD_WUSER_32_63 0x301140 50 51 #define HZIP_QM_IDEL_STATUS 0x3040e4 52 53 #define HZIP_CORE_DEBUG_COMP_0 0x302000 54 #define HZIP_CORE_DEBUG_COMP_1 0x303000 55 #define HZIP_CORE_DEBUG_DECOMP_0 0x304000 56 #define HZIP_CORE_DEBUG_DECOMP_1 0x305000 57 #define HZIP_CORE_DEBUG_DECOMP_2 0x306000 58 #define HZIP_CORE_DEBUG_DECOMP_3 0x307000 59 #define HZIP_CORE_DEBUG_DECOMP_4 0x308000 60 #define HZIP_CORE_DEBUG_DECOMP_5 0x309000 61 62 #define HZIP_CORE_INT_SOURCE 0x3010A0 63 #define HZIP_CORE_INT_MASK_REG 0x3010A4 64 #define HZIP_CORE_INT_SET 0x3010A8 65 #define HZIP_CORE_INT_STATUS 0x3010AC 66 #define HZIP_CORE_INT_STATUS_M_ECC BIT(1) 67 #define HZIP_CORE_SRAM_ECC_ERR_INFO 0x301148 68 #define HZIP_CORE_INT_RAS_CE_ENB 0x301160 69 #define HZIP_CORE_INT_RAS_CE_ENABLE 0x1 70 #define HZIP_CORE_INT_RAS_NFE_ENB 0x301164 71 #define HZIP_CORE_INT_RAS_FE_ENB 0x301168 72 #define HZIP_OOO_SHUTDOWN_SEL 0x30120C 73 #define HZIP_CORE_INT_RAS_NFE_ENABLE 0x1FFE 74 #define HZIP_SRAM_ECC_ERR_NUM_SHIFT 16 75 #define HZIP_SRAM_ECC_ERR_ADDR_SHIFT 24 76 #define HZIP_CORE_INT_MASK_ALL GENMASK(12, 0) 77 #define HZIP_COMP_CORE_NUM 2 78 #define HZIP_DECOMP_CORE_NUM 6 79 #define HZIP_CORE_NUM (HZIP_COMP_CORE_NUM + \ 80 HZIP_DECOMP_CORE_NUM) 81 #define HZIP_SQE_SIZE 128 82 #define HZIP_SQ_SIZE (HZIP_SQE_SIZE * QM_Q_DEPTH) 83 #define HZIP_PF_DEF_Q_NUM 64 84 #define HZIP_PF_DEF_Q_BASE 0 85 86 #define HZIP_SOFT_CTRL_CNT_CLR_CE 0x301000 87 #define HZIP_SOFT_CTRL_CNT_CLR_CE_BIT BIT(0) 88 #define HZIP_SOFT_CTRL_ZIP_CONTROL 0x30100C 89 #define HZIP_AXI_SHUTDOWN_ENABLE BIT(14) 90 #define HZIP_WR_PORT BIT(11) 91 92 #define HZIP_BUF_SIZE 22 93 #define HZIP_SQE_MASK_OFFSET 64 94 #define HZIP_SQE_MASK_LEN 48 95 96 #define HZIP_CNT_CLR_CE_EN BIT(0) 97 #define HZIP_RO_CNT_CLR_CE_EN BIT(2) 98 #define HZIP_RD_CNT_CLR_CE_EN (HZIP_CNT_CLR_CE_EN | \ 99 HZIP_RO_CNT_CLR_CE_EN) 100 101 #define HZIP_PREFETCH_CFG 0x3011B0 102 #define HZIP_SVA_TRANS 0x3011C4 103 #define HZIP_PREFETCH_ENABLE (~(BIT(26) | BIT(17) | BIT(0))) 104 #define HZIP_SVA_PREFETCH_DISABLE BIT(26) 105 #define HZIP_SVA_DISABLE_READY (BIT(26) | BIT(30)) 106 #define HZIP_SHAPER_RATE_COMPRESS 252 107 #define HZIP_SHAPER_RATE_DECOMPRESS 229 108 #define HZIP_DELAY_1_US 1 109 #define HZIP_POLL_TIMEOUT_US 1000 110 111 /* clock gating */ 112 #define HZIP_PEH_CFG_AUTO_GATE 0x3011A8 113 #define HZIP_PEH_CFG_AUTO_GATE_EN BIT(0) 114 #define HZIP_CORE_GATED_EN GENMASK(15, 8) 115 #define HZIP_CORE_GATED_OOO_EN BIT(29) 116 #define HZIP_CLOCK_GATED_EN (HZIP_CORE_GATED_EN | \ 117 HZIP_CORE_GATED_OOO_EN) 118 119 static const char hisi_zip_name[] = "hisi_zip"; 120 static struct dentry *hzip_debugfs_root; 121 122 struct hisi_zip_hw_error { 123 u32 int_msk; 124 const char *msg; 125 }; 126 127 struct zip_dfx_item { 128 const char *name; 129 u32 offset; 130 }; 131 132 static struct hisi_qm_list zip_devices = { 133 .register_to_crypto = hisi_zip_register_to_crypto, 134 .unregister_from_crypto = hisi_zip_unregister_from_crypto, 135 }; 136 137 static struct zip_dfx_item zip_dfx_files[] = { 138 {"send_cnt", offsetof(struct hisi_zip_dfx, send_cnt)}, 139 {"recv_cnt", offsetof(struct hisi_zip_dfx, recv_cnt)}, 140 {"send_busy_cnt", offsetof(struct hisi_zip_dfx, send_busy_cnt)}, 141 {"err_bd_cnt", offsetof(struct hisi_zip_dfx, err_bd_cnt)}, 142 }; 143 144 static const struct hisi_zip_hw_error zip_hw_error[] = { 145 { .int_msk = BIT(0), .msg = "zip_ecc_1bitt_err" }, 146 { .int_msk = BIT(1), .msg = "zip_ecc_2bit_err" }, 147 { .int_msk = BIT(2), .msg = "zip_axi_rresp_err" }, 148 { .int_msk = BIT(3), .msg = "zip_axi_bresp_err" }, 149 { .int_msk = BIT(4), .msg = "zip_src_addr_parse_err" }, 150 { .int_msk = BIT(5), .msg = "zip_dst_addr_parse_err" }, 151 { .int_msk = BIT(6), .msg = "zip_pre_in_addr_err" }, 152 { .int_msk = BIT(7), .msg = "zip_pre_in_data_err" }, 153 { .int_msk = BIT(8), .msg = "zip_com_inf_err" }, 154 { .int_msk = BIT(9), .msg = "zip_enc_inf_err" }, 155 { .int_msk = BIT(10), .msg = "zip_pre_out_err" }, 156 { .int_msk = BIT(11), .msg = "zip_axi_poison_err" }, 157 { .int_msk = BIT(12), .msg = "zip_sva_err" }, 158 { /* sentinel */ } 159 }; 160 161 enum ctrl_debug_file_index { 162 HZIP_CLEAR_ENABLE, 163 HZIP_DEBUG_FILE_NUM, 164 }; 165 166 static const char * const ctrl_debug_file_name[] = { 167 [HZIP_CLEAR_ENABLE] = "clear_enable", 168 }; 169 170 struct ctrl_debug_file { 171 enum ctrl_debug_file_index index; 172 spinlock_t lock; 173 struct hisi_zip_ctrl *ctrl; 174 }; 175 176 /* 177 * One ZIP controller has one PF and multiple VFs, some global configurations 178 * which PF has need this structure. 179 * 180 * Just relevant for PF. 181 */ 182 struct hisi_zip_ctrl { 183 struct hisi_zip *hisi_zip; 184 struct ctrl_debug_file files[HZIP_DEBUG_FILE_NUM]; 185 }; 186 187 enum { 188 HZIP_COMP_CORE0, 189 HZIP_COMP_CORE1, 190 HZIP_DECOMP_CORE0, 191 HZIP_DECOMP_CORE1, 192 HZIP_DECOMP_CORE2, 193 HZIP_DECOMP_CORE3, 194 HZIP_DECOMP_CORE4, 195 HZIP_DECOMP_CORE5, 196 }; 197 198 static const u64 core_offsets[] = { 199 [HZIP_COMP_CORE0] = 0x302000, 200 [HZIP_COMP_CORE1] = 0x303000, 201 [HZIP_DECOMP_CORE0] = 0x304000, 202 [HZIP_DECOMP_CORE1] = 0x305000, 203 [HZIP_DECOMP_CORE2] = 0x306000, 204 [HZIP_DECOMP_CORE3] = 0x307000, 205 [HZIP_DECOMP_CORE4] = 0x308000, 206 [HZIP_DECOMP_CORE5] = 0x309000, 207 }; 208 209 static const struct debugfs_reg32 hzip_dfx_regs[] = { 210 {"HZIP_GET_BD_NUM ", 0x00ull}, 211 {"HZIP_GET_RIGHT_BD ", 0x04ull}, 212 {"HZIP_GET_ERROR_BD ", 0x08ull}, 213 {"HZIP_DONE_BD_NUM ", 0x0cull}, 214 {"HZIP_WORK_CYCLE ", 0x10ull}, 215 {"HZIP_IDLE_CYCLE ", 0x18ull}, 216 {"HZIP_MAX_DELAY ", 0x20ull}, 217 {"HZIP_MIN_DELAY ", 0x24ull}, 218 {"HZIP_AVG_DELAY ", 0x28ull}, 219 {"HZIP_MEM_VISIBLE_DATA ", 0x30ull}, 220 {"HZIP_MEM_VISIBLE_ADDR ", 0x34ull}, 221 {"HZIP_CONSUMED_BYTE ", 0x38ull}, 222 {"HZIP_PRODUCED_BYTE ", 0x40ull}, 223 {"HZIP_COMP_INF ", 0x70ull}, 224 {"HZIP_PRE_OUT ", 0x78ull}, 225 {"HZIP_BD_RD ", 0x7cull}, 226 {"HZIP_BD_WR ", 0x80ull}, 227 {"HZIP_GET_BD_AXI_ERR_NUM ", 0x84ull}, 228 {"HZIP_GET_BD_PARSE_ERR_NUM ", 0x88ull}, 229 {"HZIP_ADD_BD_AXI_ERR_NUM ", 0x8cull}, 230 {"HZIP_DECOMP_STF_RELOAD_CURR_ST ", 0x94ull}, 231 {"HZIP_DECOMP_LZ77_CURR_ST ", 0x9cull}, 232 }; 233 234 static const struct kernel_param_ops zip_uacce_mode_ops = { 235 .set = uacce_mode_set, 236 .get = param_get_int, 237 }; 238 239 /* 240 * uacce_mode = 0 means zip only register to crypto, 241 * uacce_mode = 1 means zip both register to crypto and uacce. 242 */ 243 static u32 uacce_mode = UACCE_MODE_NOUACCE; 244 module_param_cb(uacce_mode, &zip_uacce_mode_ops, &uacce_mode, 0444); 245 MODULE_PARM_DESC(uacce_mode, UACCE_MODE_DESC); 246 247 static int pf_q_num_set(const char *val, const struct kernel_param *kp) 248 { 249 return q_num_set(val, kp, PCI_DEVICE_ID_ZIP_PF); 250 } 251 252 static const struct kernel_param_ops pf_q_num_ops = { 253 .set = pf_q_num_set, 254 .get = param_get_int, 255 }; 256 257 static u32 pf_q_num = HZIP_PF_DEF_Q_NUM; 258 module_param_cb(pf_q_num, &pf_q_num_ops, &pf_q_num, 0444); 259 MODULE_PARM_DESC(pf_q_num, "Number of queues in PF(v1 2-4096, v2 2-1024)"); 260 261 static const struct kernel_param_ops vfs_num_ops = { 262 .set = vfs_num_set, 263 .get = param_get_int, 264 }; 265 266 static u32 vfs_num; 267 module_param_cb(vfs_num, &vfs_num_ops, &vfs_num, 0444); 268 MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)"); 269 270 static const struct pci_device_id hisi_zip_dev_ids[] = { 271 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_ZIP_PF) }, 272 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_ZIP_VF) }, 273 { 0, } 274 }; 275 MODULE_DEVICE_TABLE(pci, hisi_zip_dev_ids); 276 277 int zip_create_qps(struct hisi_qp **qps, int qp_num, int node) 278 { 279 if (node == NUMA_NO_NODE) 280 node = cpu_to_node(smp_processor_id()); 281 282 return hisi_qm_alloc_qps_node(&zip_devices, qp_num, 0, node, qps); 283 } 284 285 static void hisi_zip_open_sva_prefetch(struct hisi_qm *qm) 286 { 287 u32 val; 288 int ret; 289 290 if (qm->ver < QM_HW_V3) 291 return; 292 293 /* Enable prefetch */ 294 val = readl_relaxed(qm->io_base + HZIP_PREFETCH_CFG); 295 val &= HZIP_PREFETCH_ENABLE; 296 writel(val, qm->io_base + HZIP_PREFETCH_CFG); 297 298 ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_PREFETCH_CFG, 299 val, !(val & HZIP_SVA_PREFETCH_DISABLE), 300 HZIP_DELAY_1_US, HZIP_POLL_TIMEOUT_US); 301 if (ret) 302 pci_err(qm->pdev, "failed to open sva prefetch\n"); 303 } 304 305 static void hisi_zip_close_sva_prefetch(struct hisi_qm *qm) 306 { 307 u32 val; 308 int ret; 309 310 if (qm->ver < QM_HW_V3) 311 return; 312 313 val = readl_relaxed(qm->io_base + HZIP_PREFETCH_CFG); 314 val |= HZIP_SVA_PREFETCH_DISABLE; 315 writel(val, qm->io_base + HZIP_PREFETCH_CFG); 316 317 ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_SVA_TRANS, 318 val, !(val & HZIP_SVA_DISABLE_READY), 319 HZIP_DELAY_1_US, HZIP_POLL_TIMEOUT_US); 320 if (ret) 321 pci_err(qm->pdev, "failed to close sva prefetch\n"); 322 } 323 324 static void hisi_zip_enable_clock_gate(struct hisi_qm *qm) 325 { 326 u32 val; 327 328 if (qm->ver < QM_HW_V3) 329 return; 330 331 val = readl(qm->io_base + HZIP_CLOCK_GATE_CTRL); 332 val |= HZIP_CLOCK_GATED_EN; 333 writel(val, qm->io_base + HZIP_CLOCK_GATE_CTRL); 334 335 val = readl(qm->io_base + HZIP_PEH_CFG_AUTO_GATE); 336 val |= HZIP_PEH_CFG_AUTO_GATE_EN; 337 writel(val, qm->io_base + HZIP_PEH_CFG_AUTO_GATE); 338 } 339 340 static int hisi_zip_set_user_domain_and_cache(struct hisi_qm *qm) 341 { 342 void __iomem *base = qm->io_base; 343 344 /* qm user domain */ 345 writel(AXUSER_BASE, base + QM_ARUSER_M_CFG_1); 346 writel(ARUSER_M_CFG_ENABLE, base + QM_ARUSER_M_CFG_ENABLE); 347 writel(AXUSER_BASE, base + QM_AWUSER_M_CFG_1); 348 writel(AWUSER_M_CFG_ENABLE, base + QM_AWUSER_M_CFG_ENABLE); 349 writel(WUSER_M_CFG_ENABLE, base + QM_WUSER_M_CFG_ENABLE); 350 351 /* qm cache */ 352 writel(AXI_M_CFG, base + QM_AXI_M_CFG); 353 writel(AXI_M_CFG_ENABLE, base + QM_AXI_M_CFG_ENABLE); 354 355 /* disable FLR triggered by BME(bus master enable) */ 356 writel(PEH_AXUSER_CFG, base + QM_PEH_AXUSER_CFG); 357 writel(PEH_AXUSER_CFG_ENABLE, base + QM_PEH_AXUSER_CFG_ENABLE); 358 359 /* cache */ 360 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_ARCA_CHE_0); 361 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_ARCA_CHE_1); 362 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_AWCA_CHE_0); 363 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_AWCA_CHE_1); 364 365 /* user domain configurations */ 366 writel(AXUSER_BASE, base + HZIP_BD_RUSER_32_63); 367 writel(AXUSER_BASE, base + HZIP_SGL_RUSER_32_63); 368 writel(AXUSER_BASE, base + HZIP_BD_WUSER_32_63); 369 370 if (qm->use_sva && qm->ver == QM_HW_V2) { 371 writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_DATA_RUSER_32_63); 372 writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_DATA_WUSER_32_63); 373 } else { 374 writel(AXUSER_BASE, base + HZIP_DATA_RUSER_32_63); 375 writel(AXUSER_BASE, base + HZIP_DATA_WUSER_32_63); 376 } 377 378 /* let's open all compression/decompression cores */ 379 writel(HZIP_DECOMP_CHECK_ENABLE | HZIP_ALL_COMP_DECOMP_EN, 380 base + HZIP_CLOCK_GATE_CTRL); 381 382 /* enable sqc,cqc writeback */ 383 writel(SQC_CACHE_ENABLE | CQC_CACHE_ENABLE | SQC_CACHE_WB_ENABLE | 384 CQC_CACHE_WB_ENABLE | FIELD_PREP(SQC_CACHE_WB_THRD, 1) | 385 FIELD_PREP(CQC_CACHE_WB_THRD, 1), base + QM_CACHE_CTL); 386 387 hisi_zip_enable_clock_gate(qm); 388 389 return 0; 390 } 391 392 static void hisi_zip_master_ooo_ctrl(struct hisi_qm *qm, bool enable) 393 { 394 u32 val1, val2; 395 396 val1 = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 397 if (enable) { 398 val1 |= HZIP_AXI_SHUTDOWN_ENABLE; 399 val2 = HZIP_CORE_INT_RAS_NFE_ENABLE; 400 } else { 401 val1 &= ~HZIP_AXI_SHUTDOWN_ENABLE; 402 val2 = 0x0; 403 } 404 405 if (qm->ver > QM_HW_V2) 406 writel(val2, qm->io_base + HZIP_OOO_SHUTDOWN_SEL); 407 408 writel(val1, qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 409 } 410 411 static void hisi_zip_hw_error_enable(struct hisi_qm *qm) 412 { 413 if (qm->ver == QM_HW_V1) { 414 writel(HZIP_CORE_INT_MASK_ALL, 415 qm->io_base + HZIP_CORE_INT_MASK_REG); 416 dev_info(&qm->pdev->dev, "Does not support hw error handle\n"); 417 return; 418 } 419 420 /* clear ZIP hw error source if having */ 421 writel(HZIP_CORE_INT_MASK_ALL, qm->io_base + HZIP_CORE_INT_SOURCE); 422 423 /* configure error type */ 424 writel(HZIP_CORE_INT_RAS_CE_ENABLE, 425 qm->io_base + HZIP_CORE_INT_RAS_CE_ENB); 426 writel(0x0, qm->io_base + HZIP_CORE_INT_RAS_FE_ENB); 427 writel(HZIP_CORE_INT_RAS_NFE_ENABLE, 428 qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 429 430 /* enable ZIP block master OOO when nfe occurs on Kunpeng930 */ 431 hisi_zip_master_ooo_ctrl(qm, true); 432 433 /* enable ZIP hw error interrupts */ 434 writel(0, qm->io_base + HZIP_CORE_INT_MASK_REG); 435 } 436 437 static void hisi_zip_hw_error_disable(struct hisi_qm *qm) 438 { 439 /* disable ZIP hw error interrupts */ 440 writel(HZIP_CORE_INT_MASK_ALL, qm->io_base + HZIP_CORE_INT_MASK_REG); 441 442 /* disable ZIP block master OOO when nfe occurs on Kunpeng930 */ 443 hisi_zip_master_ooo_ctrl(qm, false); 444 } 445 446 static inline struct hisi_qm *file_to_qm(struct ctrl_debug_file *file) 447 { 448 struct hisi_zip *hisi_zip = file->ctrl->hisi_zip; 449 450 return &hisi_zip->qm; 451 } 452 453 static u32 clear_enable_read(struct hisi_qm *qm) 454 { 455 return readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) & 456 HZIP_SOFT_CTRL_CNT_CLR_CE_BIT; 457 } 458 459 static int clear_enable_write(struct hisi_qm *qm, u32 val) 460 { 461 u32 tmp; 462 463 if (val != 1 && val != 0) 464 return -EINVAL; 465 466 tmp = (readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) & 467 ~HZIP_SOFT_CTRL_CNT_CLR_CE_BIT) | val; 468 writel(tmp, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE); 469 470 return 0; 471 } 472 473 static ssize_t hisi_zip_ctrl_debug_read(struct file *filp, char __user *buf, 474 size_t count, loff_t *pos) 475 { 476 struct ctrl_debug_file *file = filp->private_data; 477 struct hisi_qm *qm = file_to_qm(file); 478 char tbuf[HZIP_BUF_SIZE]; 479 u32 val; 480 int ret; 481 482 ret = hisi_qm_get_dfx_access(qm); 483 if (ret) 484 return ret; 485 486 spin_lock_irq(&file->lock); 487 switch (file->index) { 488 case HZIP_CLEAR_ENABLE: 489 val = clear_enable_read(qm); 490 break; 491 default: 492 goto err_input; 493 } 494 spin_unlock_irq(&file->lock); 495 496 hisi_qm_put_dfx_access(qm); 497 ret = scnprintf(tbuf, sizeof(tbuf), "%u\n", val); 498 return simple_read_from_buffer(buf, count, pos, tbuf, ret); 499 500 err_input: 501 spin_unlock_irq(&file->lock); 502 hisi_qm_put_dfx_access(qm); 503 return -EINVAL; 504 } 505 506 static ssize_t hisi_zip_ctrl_debug_write(struct file *filp, 507 const char __user *buf, 508 size_t count, loff_t *pos) 509 { 510 struct ctrl_debug_file *file = filp->private_data; 511 struct hisi_qm *qm = file_to_qm(file); 512 char tbuf[HZIP_BUF_SIZE]; 513 unsigned long val; 514 int len, ret; 515 516 if (*pos != 0) 517 return 0; 518 519 if (count >= HZIP_BUF_SIZE) 520 return -ENOSPC; 521 522 len = simple_write_to_buffer(tbuf, HZIP_BUF_SIZE - 1, pos, buf, count); 523 if (len < 0) 524 return len; 525 526 tbuf[len] = '\0'; 527 if (kstrtoul(tbuf, 0, &val)) 528 return -EFAULT; 529 530 ret = hisi_qm_get_dfx_access(qm); 531 if (ret) 532 return ret; 533 534 spin_lock_irq(&file->lock); 535 switch (file->index) { 536 case HZIP_CLEAR_ENABLE: 537 ret = clear_enable_write(qm, val); 538 if (ret) 539 goto err_input; 540 break; 541 default: 542 ret = -EINVAL; 543 goto err_input; 544 } 545 546 ret = count; 547 548 err_input: 549 spin_unlock_irq(&file->lock); 550 hisi_qm_put_dfx_access(qm); 551 return ret; 552 } 553 554 static const struct file_operations ctrl_debug_fops = { 555 .owner = THIS_MODULE, 556 .open = simple_open, 557 .read = hisi_zip_ctrl_debug_read, 558 .write = hisi_zip_ctrl_debug_write, 559 }; 560 561 static int zip_debugfs_atomic64_set(void *data, u64 val) 562 { 563 if (val) 564 return -EINVAL; 565 566 atomic64_set((atomic64_t *)data, 0); 567 568 return 0; 569 } 570 571 static int zip_debugfs_atomic64_get(void *data, u64 *val) 572 { 573 *val = atomic64_read((atomic64_t *)data); 574 575 return 0; 576 } 577 578 DEFINE_DEBUGFS_ATTRIBUTE(zip_atomic64_ops, zip_debugfs_atomic64_get, 579 zip_debugfs_atomic64_set, "%llu\n"); 580 581 static int hisi_zip_regs_show(struct seq_file *s, void *unused) 582 { 583 hisi_qm_regs_dump(s, s->private); 584 585 return 0; 586 } 587 588 DEFINE_SHOW_ATTRIBUTE(hisi_zip_regs); 589 590 static int hisi_zip_core_debug_init(struct hisi_qm *qm) 591 { 592 struct device *dev = &qm->pdev->dev; 593 struct debugfs_regset32 *regset; 594 struct dentry *tmp_d; 595 char buf[HZIP_BUF_SIZE]; 596 int i; 597 598 for (i = 0; i < HZIP_CORE_NUM; i++) { 599 if (i < HZIP_COMP_CORE_NUM) 600 scnprintf(buf, sizeof(buf), "comp_core%d", i); 601 else 602 scnprintf(buf, sizeof(buf), "decomp_core%d", 603 i - HZIP_COMP_CORE_NUM); 604 605 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 606 if (!regset) 607 return -ENOENT; 608 609 regset->regs = hzip_dfx_regs; 610 regset->nregs = ARRAY_SIZE(hzip_dfx_regs); 611 regset->base = qm->io_base + core_offsets[i]; 612 regset->dev = dev; 613 614 tmp_d = debugfs_create_dir(buf, qm->debug.debug_root); 615 debugfs_create_file("regs", 0444, tmp_d, regset, 616 &hisi_zip_regs_fops); 617 } 618 619 return 0; 620 } 621 622 static void hisi_zip_dfx_debug_init(struct hisi_qm *qm) 623 { 624 struct hisi_zip *zip = container_of(qm, struct hisi_zip, qm); 625 struct hisi_zip_dfx *dfx = &zip->dfx; 626 struct dentry *tmp_dir; 627 void *data; 628 int i; 629 630 tmp_dir = debugfs_create_dir("zip_dfx", qm->debug.debug_root); 631 for (i = 0; i < ARRAY_SIZE(zip_dfx_files); i++) { 632 data = (atomic64_t *)((uintptr_t)dfx + zip_dfx_files[i].offset); 633 debugfs_create_file(zip_dfx_files[i].name, 634 0644, tmp_dir, data, 635 &zip_atomic64_ops); 636 } 637 } 638 639 static int hisi_zip_ctrl_debug_init(struct hisi_qm *qm) 640 { 641 struct hisi_zip *zip = container_of(qm, struct hisi_zip, qm); 642 int i; 643 644 for (i = HZIP_CLEAR_ENABLE; i < HZIP_DEBUG_FILE_NUM; i++) { 645 spin_lock_init(&zip->ctrl->files[i].lock); 646 zip->ctrl->files[i].ctrl = zip->ctrl; 647 zip->ctrl->files[i].index = i; 648 649 debugfs_create_file(ctrl_debug_file_name[i], 0600, 650 qm->debug.debug_root, 651 zip->ctrl->files + i, 652 &ctrl_debug_fops); 653 } 654 655 return hisi_zip_core_debug_init(qm); 656 } 657 658 static int hisi_zip_debugfs_init(struct hisi_qm *qm) 659 { 660 struct device *dev = &qm->pdev->dev; 661 struct dentry *dev_d; 662 int ret; 663 664 dev_d = debugfs_create_dir(dev_name(dev), hzip_debugfs_root); 665 666 qm->debug.sqe_mask_offset = HZIP_SQE_MASK_OFFSET; 667 qm->debug.sqe_mask_len = HZIP_SQE_MASK_LEN; 668 qm->debug.debug_root = dev_d; 669 hisi_qm_debug_init(qm); 670 671 if (qm->fun_type == QM_HW_PF) { 672 ret = hisi_zip_ctrl_debug_init(qm); 673 if (ret) 674 goto failed_to_create; 675 } 676 677 hisi_zip_dfx_debug_init(qm); 678 679 return 0; 680 681 failed_to_create: 682 debugfs_remove_recursive(hzip_debugfs_root); 683 return ret; 684 } 685 686 /* hisi_zip_debug_regs_clear() - clear the zip debug regs */ 687 static void hisi_zip_debug_regs_clear(struct hisi_qm *qm) 688 { 689 int i, j; 690 691 /* enable register read_clear bit */ 692 writel(HZIP_RD_CNT_CLR_CE_EN, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE); 693 for (i = 0; i < ARRAY_SIZE(core_offsets); i++) 694 for (j = 0; j < ARRAY_SIZE(hzip_dfx_regs); j++) 695 readl(qm->io_base + core_offsets[i] + 696 hzip_dfx_regs[j].offset); 697 698 /* disable register read_clear bit */ 699 writel(0x0, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE); 700 701 hisi_qm_debug_regs_clear(qm); 702 } 703 704 static void hisi_zip_debugfs_exit(struct hisi_qm *qm) 705 { 706 debugfs_remove_recursive(qm->debug.debug_root); 707 708 if (qm->fun_type == QM_HW_PF) { 709 hisi_zip_debug_regs_clear(qm); 710 qm->debug.curr_qm_qp_num = 0; 711 } 712 } 713 714 static void hisi_zip_log_hw_error(struct hisi_qm *qm, u32 err_sts) 715 { 716 const struct hisi_zip_hw_error *err = zip_hw_error; 717 struct device *dev = &qm->pdev->dev; 718 u32 err_val; 719 720 while (err->msg) { 721 if (err->int_msk & err_sts) { 722 dev_err(dev, "%s [error status=0x%x] found\n", 723 err->msg, err->int_msk); 724 725 if (err->int_msk & HZIP_CORE_INT_STATUS_M_ECC) { 726 err_val = readl(qm->io_base + 727 HZIP_CORE_SRAM_ECC_ERR_INFO); 728 dev_err(dev, "hisi-zip multi ecc sram num=0x%x\n", 729 ((err_val >> 730 HZIP_SRAM_ECC_ERR_NUM_SHIFT) & 0xFF)); 731 } 732 } 733 err++; 734 } 735 } 736 737 static u32 hisi_zip_get_hw_err_status(struct hisi_qm *qm) 738 { 739 return readl(qm->io_base + HZIP_CORE_INT_STATUS); 740 } 741 742 static void hisi_zip_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts) 743 { 744 writel(err_sts, qm->io_base + HZIP_CORE_INT_SOURCE); 745 } 746 747 static void hisi_zip_open_axi_master_ooo(struct hisi_qm *qm) 748 { 749 u32 val; 750 751 val = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 752 753 writel(val & ~HZIP_AXI_SHUTDOWN_ENABLE, 754 qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 755 756 writel(val | HZIP_AXI_SHUTDOWN_ENABLE, 757 qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 758 } 759 760 static void hisi_zip_close_axi_master_ooo(struct hisi_qm *qm) 761 { 762 u32 nfe_enb; 763 764 /* Disable ECC Mbit error report. */ 765 nfe_enb = readl(qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 766 writel(nfe_enb & ~HZIP_CORE_INT_STATUS_M_ECC, 767 qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 768 769 /* Inject zip ECC Mbit error to block master ooo. */ 770 writel(HZIP_CORE_INT_STATUS_M_ECC, 771 qm->io_base + HZIP_CORE_INT_SET); 772 } 773 774 static void hisi_zip_err_info_init(struct hisi_qm *qm) 775 { 776 struct hisi_qm_err_info *err_info = &qm->err_info; 777 778 err_info->ce = QM_BASE_CE; 779 err_info->fe = 0; 780 err_info->ecc_2bits_mask = HZIP_CORE_INT_STATUS_M_ECC; 781 err_info->dev_ce_mask = HZIP_CORE_INT_RAS_CE_ENABLE; 782 err_info->msi_wr_port = HZIP_WR_PORT; 783 err_info->acpi_rst = "ZRST"; 784 err_info->nfe = QM_BASE_NFE | QM_ACC_WB_NOT_READY_TIMEOUT; 785 786 if (qm->ver >= QM_HW_V3) 787 err_info->nfe |= QM_ACC_DO_TASK_TIMEOUT; 788 } 789 790 static const struct hisi_qm_err_ini hisi_zip_err_ini = { 791 .hw_init = hisi_zip_set_user_domain_and_cache, 792 .hw_err_enable = hisi_zip_hw_error_enable, 793 .hw_err_disable = hisi_zip_hw_error_disable, 794 .get_dev_hw_err_status = hisi_zip_get_hw_err_status, 795 .clear_dev_hw_err_status = hisi_zip_clear_hw_err_status, 796 .log_dev_hw_err = hisi_zip_log_hw_error, 797 .open_axi_master_ooo = hisi_zip_open_axi_master_ooo, 798 .close_axi_master_ooo = hisi_zip_close_axi_master_ooo, 799 .open_sva_prefetch = hisi_zip_open_sva_prefetch, 800 .close_sva_prefetch = hisi_zip_close_sva_prefetch, 801 .err_info_init = hisi_zip_err_info_init, 802 }; 803 804 static int hisi_zip_pf_probe_init(struct hisi_zip *hisi_zip) 805 { 806 struct hisi_qm *qm = &hisi_zip->qm; 807 struct hisi_zip_ctrl *ctrl; 808 809 ctrl = devm_kzalloc(&qm->pdev->dev, sizeof(*ctrl), GFP_KERNEL); 810 if (!ctrl) 811 return -ENOMEM; 812 813 hisi_zip->ctrl = ctrl; 814 ctrl->hisi_zip = hisi_zip; 815 qm->err_ini = &hisi_zip_err_ini; 816 qm->err_ini->err_info_init(qm); 817 818 hisi_zip_set_user_domain_and_cache(qm); 819 hisi_zip_open_sva_prefetch(qm); 820 hisi_qm_dev_err_init(qm); 821 hisi_zip_debug_regs_clear(qm); 822 823 return 0; 824 } 825 826 static int hisi_zip_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) 827 { 828 int ret; 829 830 qm->pdev = pdev; 831 qm->ver = pdev->revision; 832 qm->algs = "zlib\ngzip"; 833 qm->mode = uacce_mode; 834 qm->sqe_size = HZIP_SQE_SIZE; 835 qm->dev_name = hisi_zip_name; 836 837 qm->fun_type = (pdev->device == PCI_DEVICE_ID_ZIP_PF) ? 838 QM_HW_PF : QM_HW_VF; 839 if (qm->fun_type == QM_HW_PF) { 840 qm->qp_base = HZIP_PF_DEF_Q_BASE; 841 qm->qp_num = pf_q_num; 842 qm->debug.curr_qm_qp_num = pf_q_num; 843 qm->qm_list = &zip_devices; 844 } else if (qm->fun_type == QM_HW_VF && qm->ver == QM_HW_V1) { 845 /* 846 * have no way to get qm configure in VM in v1 hardware, 847 * so currently force PF to uses HZIP_PF_DEF_Q_NUM, and force 848 * to trigger only one VF in v1 hardware. 849 * 850 * v2 hardware has no such problem. 851 */ 852 qm->qp_base = HZIP_PF_DEF_Q_NUM; 853 qm->qp_num = HZIP_QUEUE_NUM_V1 - HZIP_PF_DEF_Q_NUM; 854 } 855 856 qm->wq = alloc_workqueue("%s", WQ_HIGHPRI | WQ_MEM_RECLAIM | 857 WQ_UNBOUND, num_online_cpus(), 858 pci_name(qm->pdev)); 859 if (!qm->wq) { 860 pci_err(qm->pdev, "fail to alloc workqueue\n"); 861 return -ENOMEM; 862 } 863 864 ret = hisi_qm_init(qm); 865 if (ret) 866 destroy_workqueue(qm->wq); 867 868 return ret; 869 } 870 871 static void hisi_zip_qm_uninit(struct hisi_qm *qm) 872 { 873 hisi_qm_uninit(qm); 874 destroy_workqueue(qm->wq); 875 } 876 877 static int hisi_zip_probe_init(struct hisi_zip *hisi_zip) 878 { 879 u32 type_rate = HZIP_SHAPER_RATE_COMPRESS; 880 struct hisi_qm *qm = &hisi_zip->qm; 881 int ret; 882 883 if (qm->fun_type == QM_HW_PF) { 884 ret = hisi_zip_pf_probe_init(hisi_zip); 885 if (ret) 886 return ret; 887 /* enable shaper type 0 */ 888 if (qm->ver >= QM_HW_V3) { 889 type_rate |= QM_SHAPER_ENABLE; 890 891 /* ZIP need to enable shaper type 1 */ 892 type_rate |= HZIP_SHAPER_RATE_DECOMPRESS << QM_SHAPER_TYPE1_OFFSET; 893 qm->type_rate = type_rate; 894 } 895 } 896 897 return 0; 898 } 899 900 static int hisi_zip_probe(struct pci_dev *pdev, const struct pci_device_id *id) 901 { 902 struct hisi_zip *hisi_zip; 903 struct hisi_qm *qm; 904 int ret; 905 906 hisi_zip = devm_kzalloc(&pdev->dev, sizeof(*hisi_zip), GFP_KERNEL); 907 if (!hisi_zip) 908 return -ENOMEM; 909 910 qm = &hisi_zip->qm; 911 912 ret = hisi_zip_qm_init(qm, pdev); 913 if (ret) { 914 pci_err(pdev, "Failed to init ZIP QM (%d)!\n", ret); 915 return ret; 916 } 917 918 ret = hisi_zip_probe_init(hisi_zip); 919 if (ret) { 920 pci_err(pdev, "Failed to probe (%d)!\n", ret); 921 goto err_qm_uninit; 922 } 923 924 ret = hisi_qm_start(qm); 925 if (ret) 926 goto err_dev_err_uninit; 927 928 ret = hisi_zip_debugfs_init(qm); 929 if (ret) 930 pci_err(pdev, "failed to init debugfs (%d)!\n", ret); 931 932 ret = hisi_qm_alg_register(qm, &zip_devices); 933 if (ret < 0) { 934 pci_err(pdev, "failed to register driver to crypto!\n"); 935 goto err_qm_stop; 936 } 937 938 if (qm->uacce) { 939 ret = uacce_register(qm->uacce); 940 if (ret) { 941 pci_err(pdev, "failed to register uacce (%d)!\n", ret); 942 goto err_qm_alg_unregister; 943 } 944 } 945 946 if (qm->fun_type == QM_HW_PF && vfs_num > 0) { 947 ret = hisi_qm_sriov_enable(pdev, vfs_num); 948 if (ret < 0) 949 goto err_qm_alg_unregister; 950 } 951 952 hisi_qm_pm_init(qm); 953 954 return 0; 955 956 err_qm_alg_unregister: 957 hisi_qm_alg_unregister(qm, &zip_devices); 958 959 err_qm_stop: 960 hisi_zip_debugfs_exit(qm); 961 hisi_qm_stop(qm, QM_NORMAL); 962 963 err_dev_err_uninit: 964 hisi_qm_dev_err_uninit(qm); 965 966 err_qm_uninit: 967 hisi_zip_qm_uninit(qm); 968 969 return ret; 970 } 971 972 static void hisi_zip_remove(struct pci_dev *pdev) 973 { 974 struct hisi_qm *qm = pci_get_drvdata(pdev); 975 976 hisi_qm_pm_uninit(qm); 977 hisi_qm_wait_task_finish(qm, &zip_devices); 978 hisi_qm_alg_unregister(qm, &zip_devices); 979 980 if (qm->fun_type == QM_HW_PF && qm->vfs_num) 981 hisi_qm_sriov_disable(pdev, true); 982 983 hisi_zip_debugfs_exit(qm); 984 hisi_qm_stop(qm, QM_NORMAL); 985 hisi_qm_dev_err_uninit(qm); 986 hisi_zip_qm_uninit(qm); 987 } 988 989 static const struct dev_pm_ops hisi_zip_pm_ops = { 990 SET_RUNTIME_PM_OPS(hisi_qm_suspend, hisi_qm_resume, NULL) 991 }; 992 993 static const struct pci_error_handlers hisi_zip_err_handler = { 994 .error_detected = hisi_qm_dev_err_detected, 995 .slot_reset = hisi_qm_dev_slot_reset, 996 .reset_prepare = hisi_qm_reset_prepare, 997 .reset_done = hisi_qm_reset_done, 998 }; 999 1000 static struct pci_driver hisi_zip_pci_driver = { 1001 .name = "hisi_zip", 1002 .id_table = hisi_zip_dev_ids, 1003 .probe = hisi_zip_probe, 1004 .remove = hisi_zip_remove, 1005 .sriov_configure = IS_ENABLED(CONFIG_PCI_IOV) ? 1006 hisi_qm_sriov_configure : NULL, 1007 .err_handler = &hisi_zip_err_handler, 1008 .shutdown = hisi_qm_dev_shutdown, 1009 .driver.pm = &hisi_zip_pm_ops, 1010 }; 1011 1012 static void hisi_zip_register_debugfs(void) 1013 { 1014 if (!debugfs_initialized()) 1015 return; 1016 1017 hzip_debugfs_root = debugfs_create_dir("hisi_zip", NULL); 1018 } 1019 1020 static void hisi_zip_unregister_debugfs(void) 1021 { 1022 debugfs_remove_recursive(hzip_debugfs_root); 1023 } 1024 1025 static int __init hisi_zip_init(void) 1026 { 1027 int ret; 1028 1029 hisi_qm_init_list(&zip_devices); 1030 hisi_zip_register_debugfs(); 1031 1032 ret = pci_register_driver(&hisi_zip_pci_driver); 1033 if (ret < 0) { 1034 hisi_zip_unregister_debugfs(); 1035 pr_err("Failed to register pci driver.\n"); 1036 } 1037 1038 return ret; 1039 } 1040 1041 static void __exit hisi_zip_exit(void) 1042 { 1043 pci_unregister_driver(&hisi_zip_pci_driver); 1044 hisi_zip_unregister_debugfs(); 1045 } 1046 1047 module_init(hisi_zip_init); 1048 module_exit(hisi_zip_exit); 1049 1050 MODULE_LICENSE("GPL v2"); 1051 MODULE_AUTHOR("Zhou Wang <wangzhou1@hisilicon.com>"); 1052 MODULE_DESCRIPTION("Driver for HiSilicon ZIP accelerator"); 1053