1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2019 HiSilicon Limited. */
3 #include <linux/acpi.h>
4 #include <linux/aer.h>
5 #include <linux/bitops.h>
6 #include <linux/debugfs.h>
7 #include <linux/init.h>
8 #include <linux/io.h>
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/pci.h>
12 #include <linux/seq_file.h>
13 #include <linux/topology.h>
14 #include <linux/uacce.h>
15 #include "zip.h"
16 
17 #define PCI_DEVICE_ID_ZIP_PF		0xa250
18 #define PCI_DEVICE_ID_ZIP_VF		0xa251
19 
20 #define HZIP_VF_NUM			63
21 #define HZIP_QUEUE_NUM_V1		4096
22 #define HZIP_QUEUE_NUM_V2		1024
23 
24 #define HZIP_CLOCK_GATE_CTRL		0x301004
25 #define COMP0_ENABLE			BIT(0)
26 #define COMP1_ENABLE			BIT(1)
27 #define DECOMP0_ENABLE			BIT(2)
28 #define DECOMP1_ENABLE			BIT(3)
29 #define DECOMP2_ENABLE			BIT(4)
30 #define DECOMP3_ENABLE			BIT(5)
31 #define DECOMP4_ENABLE			BIT(6)
32 #define DECOMP5_ENABLE			BIT(7)
33 #define ALL_COMP_DECOMP_EN		(COMP0_ENABLE | COMP1_ENABLE |	\
34 					 DECOMP0_ENABLE | DECOMP1_ENABLE | \
35 					 DECOMP2_ENABLE | DECOMP3_ENABLE | \
36 					 DECOMP4_ENABLE | DECOMP5_ENABLE)
37 #define DECOMP_CHECK_ENABLE		BIT(16)
38 #define HZIP_FSM_MAX_CNT		0x301008
39 
40 #define HZIP_PORT_ARCA_CHE_0		0x301040
41 #define HZIP_PORT_ARCA_CHE_1		0x301044
42 #define HZIP_PORT_AWCA_CHE_0		0x301060
43 #define HZIP_PORT_AWCA_CHE_1		0x301064
44 #define CACHE_ALL_EN			0xffffffff
45 
46 #define HZIP_BD_RUSER_32_63		0x301110
47 #define HZIP_SGL_RUSER_32_63		0x30111c
48 #define HZIP_DATA_RUSER_32_63		0x301128
49 #define HZIP_DATA_WUSER_32_63		0x301134
50 #define HZIP_BD_WUSER_32_63		0x301140
51 
52 #define HZIP_QM_IDEL_STATUS		0x3040e4
53 
54 #define HZIP_CORE_DEBUG_COMP_0		0x302000
55 #define HZIP_CORE_DEBUG_COMP_1		0x303000
56 #define HZIP_CORE_DEBUG_DECOMP_0	0x304000
57 #define HZIP_CORE_DEBUG_DECOMP_1	0x305000
58 #define HZIP_CORE_DEBUG_DECOMP_2	0x306000
59 #define HZIP_CORE_DEBUG_DECOMP_3	0x307000
60 #define HZIP_CORE_DEBUG_DECOMP_4	0x308000
61 #define HZIP_CORE_DEBUG_DECOMP_5	0x309000
62 
63 #define HZIP_CORE_INT_SOURCE		0x3010A0
64 #define HZIP_CORE_INT_MASK_REG		0x3010A4
65 #define HZIP_CORE_INT_SET		0x3010A8
66 #define HZIP_CORE_INT_STATUS		0x3010AC
67 #define HZIP_CORE_INT_STATUS_M_ECC	BIT(1)
68 #define HZIP_CORE_SRAM_ECC_ERR_INFO	0x301148
69 #define HZIP_CORE_INT_RAS_CE_ENB	0x301160
70 #define HZIP_CORE_INT_RAS_NFE_ENB	0x301164
71 #define HZIP_CORE_INT_RAS_FE_ENB        0x301168
72 #define HZIP_CORE_INT_RAS_NFE_ENABLE	0x7FE
73 #define HZIP_SRAM_ECC_ERR_NUM_SHIFT	16
74 #define HZIP_SRAM_ECC_ERR_ADDR_SHIFT	24
75 #define HZIP_CORE_INT_MASK_ALL		GENMASK(10, 0)
76 #define HZIP_COMP_CORE_NUM		2
77 #define HZIP_DECOMP_CORE_NUM		6
78 #define HZIP_CORE_NUM			(HZIP_COMP_CORE_NUM + \
79 					 HZIP_DECOMP_CORE_NUM)
80 #define HZIP_SQE_SIZE			128
81 #define HZIP_SQ_SIZE			(HZIP_SQE_SIZE * QM_Q_DEPTH)
82 #define HZIP_PF_DEF_Q_NUM		64
83 #define HZIP_PF_DEF_Q_BASE		0
84 
85 #define HZIP_SOFT_CTRL_CNT_CLR_CE	0x301000
86 #define SOFT_CTRL_CNT_CLR_CE_BIT	BIT(0)
87 #define HZIP_SOFT_CTRL_ZIP_CONTROL	0x30100C
88 #define HZIP_AXI_SHUTDOWN_ENABLE	BIT(14)
89 #define HZIP_WR_PORT			BIT(11)
90 
91 #define HZIP_BUF_SIZE			22
92 #define HZIP_SQE_MASK_OFFSET		64
93 #define HZIP_SQE_MASK_LEN		48
94 
95 static const char hisi_zip_name[] = "hisi_zip";
96 static struct dentry *hzip_debugfs_root;
97 static struct hisi_qm_list zip_devices;
98 
99 struct hisi_zip_hw_error {
100 	u32 int_msk;
101 	const char *msg;
102 };
103 
104 struct zip_dfx_item {
105 	const char *name;
106 	u32 offset;
107 };
108 
109 static struct zip_dfx_item zip_dfx_files[] = {
110 	{"send_cnt", offsetof(struct hisi_zip_dfx, send_cnt)},
111 	{"recv_cnt", offsetof(struct hisi_zip_dfx, recv_cnt)},
112 	{"send_busy_cnt", offsetof(struct hisi_zip_dfx, send_busy_cnt)},
113 	{"err_bd_cnt", offsetof(struct hisi_zip_dfx, err_bd_cnt)},
114 };
115 
116 static const struct hisi_zip_hw_error zip_hw_error[] = {
117 	{ .int_msk = BIT(0), .msg = "zip_ecc_1bitt_err" },
118 	{ .int_msk = BIT(1), .msg = "zip_ecc_2bit_err" },
119 	{ .int_msk = BIT(2), .msg = "zip_axi_rresp_err" },
120 	{ .int_msk = BIT(3), .msg = "zip_axi_bresp_err" },
121 	{ .int_msk = BIT(4), .msg = "zip_src_addr_parse_err" },
122 	{ .int_msk = BIT(5), .msg = "zip_dst_addr_parse_err" },
123 	{ .int_msk = BIT(6), .msg = "zip_pre_in_addr_err" },
124 	{ .int_msk = BIT(7), .msg = "zip_pre_in_data_err" },
125 	{ .int_msk = BIT(8), .msg = "zip_com_inf_err" },
126 	{ .int_msk = BIT(9), .msg = "zip_enc_inf_err" },
127 	{ .int_msk = BIT(10), .msg = "zip_pre_out_err" },
128 	{ /* sentinel */ }
129 };
130 
131 enum ctrl_debug_file_index {
132 	HZIP_CURRENT_QM,
133 	HZIP_CLEAR_ENABLE,
134 	HZIP_DEBUG_FILE_NUM,
135 };
136 
137 static const char * const ctrl_debug_file_name[] = {
138 	[HZIP_CURRENT_QM]   = "current_qm",
139 	[HZIP_CLEAR_ENABLE] = "clear_enable",
140 };
141 
142 struct ctrl_debug_file {
143 	enum ctrl_debug_file_index index;
144 	spinlock_t lock;
145 	struct hisi_zip_ctrl *ctrl;
146 };
147 
148 /*
149  * One ZIP controller has one PF and multiple VFs, some global configurations
150  * which PF has need this structure.
151  *
152  * Just relevant for PF.
153  */
154 struct hisi_zip_ctrl {
155 	struct hisi_zip *hisi_zip;
156 	struct dentry *debug_root;
157 	struct ctrl_debug_file files[HZIP_DEBUG_FILE_NUM];
158 };
159 
160 enum {
161 	HZIP_COMP_CORE0,
162 	HZIP_COMP_CORE1,
163 	HZIP_DECOMP_CORE0,
164 	HZIP_DECOMP_CORE1,
165 	HZIP_DECOMP_CORE2,
166 	HZIP_DECOMP_CORE3,
167 	HZIP_DECOMP_CORE4,
168 	HZIP_DECOMP_CORE5,
169 };
170 
171 static const u64 core_offsets[] = {
172 	[HZIP_COMP_CORE0]   = 0x302000,
173 	[HZIP_COMP_CORE1]   = 0x303000,
174 	[HZIP_DECOMP_CORE0] = 0x304000,
175 	[HZIP_DECOMP_CORE1] = 0x305000,
176 	[HZIP_DECOMP_CORE2] = 0x306000,
177 	[HZIP_DECOMP_CORE3] = 0x307000,
178 	[HZIP_DECOMP_CORE4] = 0x308000,
179 	[HZIP_DECOMP_CORE5] = 0x309000,
180 };
181 
182 static const struct debugfs_reg32 hzip_dfx_regs[] = {
183 	{"HZIP_GET_BD_NUM                ",  0x00ull},
184 	{"HZIP_GET_RIGHT_BD              ",  0x04ull},
185 	{"HZIP_GET_ERROR_BD              ",  0x08ull},
186 	{"HZIP_DONE_BD_NUM               ",  0x0cull},
187 	{"HZIP_WORK_CYCLE                ",  0x10ull},
188 	{"HZIP_IDLE_CYCLE                ",  0x18ull},
189 	{"HZIP_MAX_DELAY                 ",  0x20ull},
190 	{"HZIP_MIN_DELAY                 ",  0x24ull},
191 	{"HZIP_AVG_DELAY                 ",  0x28ull},
192 	{"HZIP_MEM_VISIBLE_DATA          ",  0x30ull},
193 	{"HZIP_MEM_VISIBLE_ADDR          ",  0x34ull},
194 	{"HZIP_COMSUMED_BYTE             ",  0x38ull},
195 	{"HZIP_PRODUCED_BYTE             ",  0x40ull},
196 	{"HZIP_COMP_INF                  ",  0x70ull},
197 	{"HZIP_PRE_OUT                   ",  0x78ull},
198 	{"HZIP_BD_RD                     ",  0x7cull},
199 	{"HZIP_BD_WR                     ",  0x80ull},
200 	{"HZIP_GET_BD_AXI_ERR_NUM        ",  0x84ull},
201 	{"HZIP_GET_BD_PARSE_ERR_NUM      ",  0x88ull},
202 	{"HZIP_ADD_BD_AXI_ERR_NUM        ",  0x8cull},
203 	{"HZIP_DECOMP_STF_RELOAD_CURR_ST ",  0x94ull},
204 	{"HZIP_DECOMP_LZ77_CURR_ST       ",  0x9cull},
205 };
206 
207 static int pf_q_num_set(const char *val, const struct kernel_param *kp)
208 {
209 	return q_num_set(val, kp, PCI_DEVICE_ID_ZIP_PF);
210 }
211 
212 static const struct kernel_param_ops pf_q_num_ops = {
213 	.set = pf_q_num_set,
214 	.get = param_get_int,
215 };
216 
217 static u32 pf_q_num = HZIP_PF_DEF_Q_NUM;
218 module_param_cb(pf_q_num, &pf_q_num_ops, &pf_q_num, 0444);
219 MODULE_PARM_DESC(pf_q_num, "Number of queues in PF(v1 1-4096, v2 1-1024)");
220 
221 static const struct kernel_param_ops vfs_num_ops = {
222 	.set = vfs_num_set,
223 	.get = param_get_int,
224 };
225 
226 static u32 vfs_num;
227 module_param_cb(vfs_num, &vfs_num_ops, &vfs_num, 0444);
228 MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)");
229 
230 static const struct pci_device_id hisi_zip_dev_ids[] = {
231 	{ PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_ZIP_PF) },
232 	{ PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_ZIP_VF) },
233 	{ 0, }
234 };
235 MODULE_DEVICE_TABLE(pci, hisi_zip_dev_ids);
236 
237 int zip_create_qps(struct hisi_qp **qps, int qp_num)
238 {
239 	int node = cpu_to_node(smp_processor_id());
240 
241 	return hisi_qm_alloc_qps_node(&zip_devices, qp_num, 0, node, qps);
242 }
243 
244 static int hisi_zip_set_user_domain_and_cache(struct hisi_qm *qm)
245 {
246 	void __iomem *base = qm->io_base;
247 
248 	/* qm user domain */
249 	writel(AXUSER_BASE, base + QM_ARUSER_M_CFG_1);
250 	writel(ARUSER_M_CFG_ENABLE, base + QM_ARUSER_M_CFG_ENABLE);
251 	writel(AXUSER_BASE, base + QM_AWUSER_M_CFG_1);
252 	writel(AWUSER_M_CFG_ENABLE, base + QM_AWUSER_M_CFG_ENABLE);
253 	writel(WUSER_M_CFG_ENABLE, base + QM_WUSER_M_CFG_ENABLE);
254 
255 	/* qm cache */
256 	writel(AXI_M_CFG, base + QM_AXI_M_CFG);
257 	writel(AXI_M_CFG_ENABLE, base + QM_AXI_M_CFG_ENABLE);
258 	/* disable FLR triggered by BME(bus master enable) */
259 	writel(PEH_AXUSER_CFG, base + QM_PEH_AXUSER_CFG);
260 	writel(PEH_AXUSER_CFG_ENABLE, base + QM_PEH_AXUSER_CFG_ENABLE);
261 
262 	/* cache */
263 	writel(CACHE_ALL_EN, base + HZIP_PORT_ARCA_CHE_0);
264 	writel(CACHE_ALL_EN, base + HZIP_PORT_ARCA_CHE_1);
265 	writel(CACHE_ALL_EN, base + HZIP_PORT_AWCA_CHE_0);
266 	writel(CACHE_ALL_EN, base + HZIP_PORT_AWCA_CHE_1);
267 
268 	/* user domain configurations */
269 	writel(AXUSER_BASE, base + HZIP_BD_RUSER_32_63);
270 	writel(AXUSER_BASE, base + HZIP_SGL_RUSER_32_63);
271 	writel(AXUSER_BASE, base + HZIP_BD_WUSER_32_63);
272 
273 	if (qm->use_sva) {
274 		writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_DATA_RUSER_32_63);
275 		writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_DATA_WUSER_32_63);
276 	} else {
277 		writel(AXUSER_BASE, base + HZIP_DATA_RUSER_32_63);
278 		writel(AXUSER_BASE, base + HZIP_DATA_WUSER_32_63);
279 	}
280 
281 	/* let's open all compression/decompression cores */
282 	writel(DECOMP_CHECK_ENABLE | ALL_COMP_DECOMP_EN,
283 	       base + HZIP_CLOCK_GATE_CTRL);
284 
285 	/* enable sqc writeback */
286 	writel(SQC_CACHE_ENABLE | CQC_CACHE_ENABLE | SQC_CACHE_WB_ENABLE |
287 	       CQC_CACHE_WB_ENABLE | FIELD_PREP(SQC_CACHE_WB_THRD, 1) |
288 	       FIELD_PREP(CQC_CACHE_WB_THRD, 1), base + QM_CACHE_CTL);
289 
290 	return 0;
291 }
292 
293 static void hisi_zip_hw_error_enable(struct hisi_qm *qm)
294 {
295 	u32 val;
296 
297 	if (qm->ver == QM_HW_V1) {
298 		writel(HZIP_CORE_INT_MASK_ALL,
299 		       qm->io_base + HZIP_CORE_INT_MASK_REG);
300 		dev_info(&qm->pdev->dev, "Does not support hw error handle\n");
301 		return;
302 	}
303 
304 	/* clear ZIP hw error source if having */
305 	writel(HZIP_CORE_INT_MASK_ALL, qm->io_base + HZIP_CORE_INT_SOURCE);
306 
307 	/* configure error type */
308 	writel(0x1, qm->io_base + HZIP_CORE_INT_RAS_CE_ENB);
309 	writel(0x0, qm->io_base + HZIP_CORE_INT_RAS_FE_ENB);
310 	writel(HZIP_CORE_INT_RAS_NFE_ENABLE,
311 		qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB);
312 
313 	/* enable ZIP hw error interrupts */
314 	writel(0, qm->io_base + HZIP_CORE_INT_MASK_REG);
315 
316 	/* enable ZIP block master OOO when m-bit error occur */
317 	val = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);
318 	val = val | HZIP_AXI_SHUTDOWN_ENABLE;
319 	writel(val, qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);
320 }
321 
322 static void hisi_zip_hw_error_disable(struct hisi_qm *qm)
323 {
324 	u32 val;
325 
326 	/* disable ZIP hw error interrupts */
327 	writel(HZIP_CORE_INT_MASK_ALL, qm->io_base + HZIP_CORE_INT_MASK_REG);
328 
329 	/* disable ZIP block master OOO when m-bit error occur */
330 	val = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);
331 	val = val & ~HZIP_AXI_SHUTDOWN_ENABLE;
332 	writel(val, qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);
333 }
334 
335 static inline struct hisi_qm *file_to_qm(struct ctrl_debug_file *file)
336 {
337 	struct hisi_zip *hisi_zip = file->ctrl->hisi_zip;
338 
339 	return &hisi_zip->qm;
340 }
341 
342 static u32 current_qm_read(struct ctrl_debug_file *file)
343 {
344 	struct hisi_qm *qm = file_to_qm(file);
345 
346 	return readl(qm->io_base + QM_DFX_MB_CNT_VF);
347 }
348 
349 static int current_qm_write(struct ctrl_debug_file *file, u32 val)
350 {
351 	struct hisi_qm *qm = file_to_qm(file);
352 	u32 vfq_num;
353 	u32 tmp;
354 
355 	if (val > qm->vfs_num)
356 		return -EINVAL;
357 
358 	/* Calculate curr_qm_qp_num and store */
359 	if (val == 0) {
360 		qm->debug.curr_qm_qp_num = qm->qp_num;
361 	} else {
362 		vfq_num = (qm->ctrl_qp_num - qm->qp_num) / qm->vfs_num;
363 		if (val == qm->vfs_num)
364 			qm->debug.curr_qm_qp_num = qm->ctrl_qp_num -
365 				qm->qp_num - (qm->vfs_num - 1) * vfq_num;
366 		else
367 			qm->debug.curr_qm_qp_num = vfq_num;
368 	}
369 
370 	writel(val, qm->io_base + QM_DFX_MB_CNT_VF);
371 	writel(val, qm->io_base + QM_DFX_DB_CNT_VF);
372 
373 	tmp = val |
374 	      (readl(qm->io_base + QM_DFX_SQE_CNT_VF_SQN) & CURRENT_Q_MASK);
375 	writel(tmp, qm->io_base + QM_DFX_SQE_CNT_VF_SQN);
376 
377 	tmp = val |
378 	      (readl(qm->io_base + QM_DFX_CQE_CNT_VF_CQN) & CURRENT_Q_MASK);
379 	writel(tmp, qm->io_base + QM_DFX_CQE_CNT_VF_CQN);
380 
381 	return  0;
382 }
383 
384 static u32 clear_enable_read(struct ctrl_debug_file *file)
385 {
386 	struct hisi_qm *qm = file_to_qm(file);
387 
388 	return readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) &
389 	       SOFT_CTRL_CNT_CLR_CE_BIT;
390 }
391 
392 static int clear_enable_write(struct ctrl_debug_file *file, u32 val)
393 {
394 	struct hisi_qm *qm = file_to_qm(file);
395 	u32 tmp;
396 
397 	if (val != 1 && val != 0)
398 		return -EINVAL;
399 
400 	tmp = (readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) &
401 	       ~SOFT_CTRL_CNT_CLR_CE_BIT) | val;
402 	writel(tmp, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE);
403 
404 	return  0;
405 }
406 
407 static ssize_t ctrl_debug_read(struct file *filp, char __user *buf,
408 			       size_t count, loff_t *pos)
409 {
410 	struct ctrl_debug_file *file = filp->private_data;
411 	char tbuf[HZIP_BUF_SIZE];
412 	u32 val;
413 	int ret;
414 
415 	spin_lock_irq(&file->lock);
416 	switch (file->index) {
417 	case HZIP_CURRENT_QM:
418 		val = current_qm_read(file);
419 		break;
420 	case HZIP_CLEAR_ENABLE:
421 		val = clear_enable_read(file);
422 		break;
423 	default:
424 		spin_unlock_irq(&file->lock);
425 		return -EINVAL;
426 	}
427 	spin_unlock_irq(&file->lock);
428 	ret = sprintf(tbuf, "%u\n", val);
429 	return simple_read_from_buffer(buf, count, pos, tbuf, ret);
430 }
431 
432 static ssize_t ctrl_debug_write(struct file *filp, const char __user *buf,
433 				size_t count, loff_t *pos)
434 {
435 	struct ctrl_debug_file *file = filp->private_data;
436 	char tbuf[HZIP_BUF_SIZE];
437 	unsigned long val;
438 	int len, ret;
439 
440 	if (*pos != 0)
441 		return 0;
442 
443 	if (count >= HZIP_BUF_SIZE)
444 		return -ENOSPC;
445 
446 	len = simple_write_to_buffer(tbuf, HZIP_BUF_SIZE - 1, pos, buf, count);
447 	if (len < 0)
448 		return len;
449 
450 	tbuf[len] = '\0';
451 	if (kstrtoul(tbuf, 0, &val))
452 		return -EFAULT;
453 
454 	spin_lock_irq(&file->lock);
455 	switch (file->index) {
456 	case HZIP_CURRENT_QM:
457 		ret = current_qm_write(file, val);
458 		if (ret)
459 			goto err_input;
460 		break;
461 	case HZIP_CLEAR_ENABLE:
462 		ret = clear_enable_write(file, val);
463 		if (ret)
464 			goto err_input;
465 		break;
466 	default:
467 		ret = -EINVAL;
468 		goto err_input;
469 	}
470 	spin_unlock_irq(&file->lock);
471 
472 	return count;
473 
474 err_input:
475 	spin_unlock_irq(&file->lock);
476 	return ret;
477 }
478 
479 static const struct file_operations ctrl_debug_fops = {
480 	.owner = THIS_MODULE,
481 	.open = simple_open,
482 	.read = ctrl_debug_read,
483 	.write = ctrl_debug_write,
484 };
485 
486 
487 static int zip_debugfs_atomic64_set(void *data, u64 val)
488 {
489 	if (val)
490 		return -EINVAL;
491 
492 	atomic64_set((atomic64_t *)data, 0);
493 
494 	return 0;
495 }
496 
497 static int zip_debugfs_atomic64_get(void *data, u64 *val)
498 {
499 	*val = atomic64_read((atomic64_t *)data);
500 
501 	return 0;
502 }
503 
504 DEFINE_DEBUGFS_ATTRIBUTE(zip_atomic64_ops, zip_debugfs_atomic64_get,
505 			 zip_debugfs_atomic64_set, "%llu\n");
506 
507 static int hisi_zip_core_debug_init(struct hisi_zip_ctrl *ctrl)
508 {
509 	struct hisi_zip *hisi_zip = ctrl->hisi_zip;
510 	struct hisi_qm *qm = &hisi_zip->qm;
511 	struct device *dev = &qm->pdev->dev;
512 	struct debugfs_regset32 *regset;
513 	struct dentry *tmp_d;
514 	char buf[HZIP_BUF_SIZE];
515 	int i;
516 
517 	for (i = 0; i < HZIP_CORE_NUM; i++) {
518 		if (i < HZIP_COMP_CORE_NUM)
519 			sprintf(buf, "comp_core%d", i);
520 		else
521 			sprintf(buf, "decomp_core%d", i - HZIP_COMP_CORE_NUM);
522 
523 		regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL);
524 		if (!regset)
525 			return -ENOENT;
526 
527 		regset->regs = hzip_dfx_regs;
528 		regset->nregs = ARRAY_SIZE(hzip_dfx_regs);
529 		regset->base = qm->io_base + core_offsets[i];
530 
531 		tmp_d = debugfs_create_dir(buf, ctrl->debug_root);
532 		debugfs_create_regset32("regs", 0444, tmp_d, regset);
533 	}
534 
535 	return 0;
536 }
537 
538 static void hisi_zip_dfx_debug_init(struct hisi_qm *qm)
539 {
540 	struct hisi_zip *zip = container_of(qm, struct hisi_zip, qm);
541 	struct hisi_zip_dfx *dfx = &zip->dfx;
542 	struct dentry *tmp_dir;
543 	void *data;
544 	int i;
545 
546 	tmp_dir = debugfs_create_dir("zip_dfx", qm->debug.debug_root);
547 	for (i = 0; i < ARRAY_SIZE(zip_dfx_files); i++) {
548 		data = (atomic64_t *)((uintptr_t)dfx + zip_dfx_files[i].offset);
549 		debugfs_create_file(zip_dfx_files[i].name,
550 			0644,
551 			tmp_dir,
552 			data,
553 			&zip_atomic64_ops);
554 	}
555 }
556 
557 static int hisi_zip_ctrl_debug_init(struct hisi_zip_ctrl *ctrl)
558 {
559 	int i;
560 
561 	for (i = HZIP_CURRENT_QM; i < HZIP_DEBUG_FILE_NUM; i++) {
562 		spin_lock_init(&ctrl->files[i].lock);
563 		ctrl->files[i].ctrl = ctrl;
564 		ctrl->files[i].index = i;
565 
566 		debugfs_create_file(ctrl_debug_file_name[i], 0600,
567 				    ctrl->debug_root, ctrl->files + i,
568 				    &ctrl_debug_fops);
569 	}
570 
571 	return hisi_zip_core_debug_init(ctrl);
572 }
573 
574 static int hisi_zip_debugfs_init(struct hisi_zip *hisi_zip)
575 {
576 	struct hisi_qm *qm = &hisi_zip->qm;
577 	struct device *dev = &qm->pdev->dev;
578 	struct dentry *dev_d;
579 	int ret;
580 
581 	dev_d = debugfs_create_dir(dev_name(dev), hzip_debugfs_root);
582 
583 	qm->debug.sqe_mask_offset = HZIP_SQE_MASK_OFFSET;
584 	qm->debug.sqe_mask_len = HZIP_SQE_MASK_LEN;
585 	qm->debug.debug_root = dev_d;
586 	ret = hisi_qm_debug_init(qm);
587 	if (ret)
588 		goto failed_to_create;
589 
590 	if (qm->fun_type == QM_HW_PF) {
591 		hisi_zip->ctrl->debug_root = dev_d;
592 		ret = hisi_zip_ctrl_debug_init(hisi_zip->ctrl);
593 		if (ret)
594 			goto failed_to_create;
595 	}
596 
597 	hisi_zip_dfx_debug_init(qm);
598 
599 	return 0;
600 
601 failed_to_create:
602 	debugfs_remove_recursive(hzip_debugfs_root);
603 	return ret;
604 }
605 
606 static void hisi_zip_debug_regs_clear(struct hisi_zip *hisi_zip)
607 {
608 	struct hisi_qm *qm = &hisi_zip->qm;
609 
610 	writel(0x0, qm->io_base + QM_DFX_MB_CNT_VF);
611 	writel(0x0, qm->io_base + QM_DFX_DB_CNT_VF);
612 	writel(0x0, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE);
613 
614 	hisi_qm_debug_regs_clear(qm);
615 }
616 
617 static void hisi_zip_debugfs_exit(struct hisi_zip *hisi_zip)
618 {
619 	struct hisi_qm *qm = &hisi_zip->qm;
620 
621 	debugfs_remove_recursive(qm->debug.debug_root);
622 
623 	if (qm->fun_type == QM_HW_PF)
624 		hisi_zip_debug_regs_clear(hisi_zip);
625 }
626 
627 static void hisi_zip_log_hw_error(struct hisi_qm *qm, u32 err_sts)
628 {
629 	const struct hisi_zip_hw_error *err = zip_hw_error;
630 	struct device *dev = &qm->pdev->dev;
631 	u32 err_val;
632 
633 	while (err->msg) {
634 		if (err->int_msk & err_sts) {
635 			dev_err(dev, "%s [error status=0x%x] found\n",
636 				 err->msg, err->int_msk);
637 
638 			if (err->int_msk & HZIP_CORE_INT_STATUS_M_ECC) {
639 				err_val = readl(qm->io_base +
640 						HZIP_CORE_SRAM_ECC_ERR_INFO);
641 				dev_err(dev, "hisi-zip multi ecc sram num=0x%x\n",
642 					((err_val >>
643 					HZIP_SRAM_ECC_ERR_NUM_SHIFT) & 0xFF));
644 				dev_err(dev, "hisi-zip multi ecc sram addr=0x%x\n",
645 					(err_val >>
646 					HZIP_SRAM_ECC_ERR_ADDR_SHIFT));
647 			}
648 		}
649 		err++;
650 	}
651 }
652 
653 static u32 hisi_zip_get_hw_err_status(struct hisi_qm *qm)
654 {
655 	return readl(qm->io_base + HZIP_CORE_INT_STATUS);
656 }
657 
658 static void hisi_zip_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts)
659 {
660 	writel(err_sts, qm->io_base + HZIP_CORE_INT_SOURCE);
661 }
662 
663 static void hisi_zip_open_axi_master_ooo(struct hisi_qm *qm)
664 {
665 	u32 val;
666 
667 	val = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);
668 
669 	writel(val & ~HZIP_AXI_SHUTDOWN_ENABLE,
670 	       qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);
671 
672 	writel(val | HZIP_AXI_SHUTDOWN_ENABLE,
673 	       qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);
674 }
675 
676 static void hisi_zip_close_axi_master_ooo(struct hisi_qm *qm)
677 {
678 	u32 nfe_enb;
679 
680 	/* Disable ECC Mbit error report. */
681 	nfe_enb = readl(qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB);
682 	writel(nfe_enb & ~HZIP_CORE_INT_STATUS_M_ECC,
683 	       qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB);
684 
685 	/* Inject zip ECC Mbit error to block master ooo. */
686 	writel(HZIP_CORE_INT_STATUS_M_ECC,
687 	       qm->io_base + HZIP_CORE_INT_SET);
688 }
689 
690 static const struct hisi_qm_err_ini hisi_zip_err_ini = {
691 	.hw_init		= hisi_zip_set_user_domain_and_cache,
692 	.hw_err_enable		= hisi_zip_hw_error_enable,
693 	.hw_err_disable		= hisi_zip_hw_error_disable,
694 	.get_dev_hw_err_status	= hisi_zip_get_hw_err_status,
695 	.clear_dev_hw_err_status = hisi_zip_clear_hw_err_status,
696 	.log_dev_hw_err		= hisi_zip_log_hw_error,
697 	.open_axi_master_ooo	= hisi_zip_open_axi_master_ooo,
698 	.close_axi_master_ooo	= hisi_zip_close_axi_master_ooo,
699 	.err_info		= {
700 		.ce			= QM_BASE_CE,
701 		.nfe			= QM_BASE_NFE |
702 					  QM_ACC_WB_NOT_READY_TIMEOUT,
703 		.fe			= 0,
704 		.ecc_2bits_mask		= HZIP_CORE_INT_STATUS_M_ECC,
705 		.msi_wr_port		= HZIP_WR_PORT,
706 		.acpi_rst		= "ZRST",
707 	}
708 };
709 
710 static int hisi_zip_pf_probe_init(struct hisi_zip *hisi_zip)
711 {
712 	struct hisi_qm *qm = &hisi_zip->qm;
713 	struct hisi_zip_ctrl *ctrl;
714 
715 	ctrl = devm_kzalloc(&qm->pdev->dev, sizeof(*ctrl), GFP_KERNEL);
716 	if (!ctrl)
717 		return -ENOMEM;
718 
719 	hisi_zip->ctrl = ctrl;
720 	ctrl->hisi_zip = hisi_zip;
721 
722 	if (qm->ver == QM_HW_V1)
723 		qm->ctrl_qp_num = HZIP_QUEUE_NUM_V1;
724 	else
725 		qm->ctrl_qp_num = HZIP_QUEUE_NUM_V2;
726 
727 	qm->err_ini = &hisi_zip_err_ini;
728 
729 	hisi_zip_set_user_domain_and_cache(qm);
730 	hisi_qm_dev_err_init(qm);
731 	hisi_zip_debug_regs_clear(hisi_zip);
732 
733 	return 0;
734 }
735 
736 static int hisi_zip_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)
737 {
738 	qm->pdev = pdev;
739 	qm->ver = pdev->revision;
740 	qm->algs = "zlib\ngzip";
741 	qm->sqe_size = HZIP_SQE_SIZE;
742 	qm->dev_name = hisi_zip_name;
743 
744 	qm->fun_type = (pdev->device == PCI_DEVICE_ID_ZIP_PF) ?
745 			QM_HW_PF : QM_HW_VF;
746 	if (qm->fun_type == QM_HW_PF) {
747 		qm->qp_base = HZIP_PF_DEF_Q_BASE;
748 		qm->qp_num = pf_q_num;
749 		qm->qm_list = &zip_devices;
750 	} else if (qm->fun_type == QM_HW_VF && qm->ver == QM_HW_V1) {
751 		/*
752 		 * have no way to get qm configure in VM in v1 hardware,
753 		 * so currently force PF to uses HZIP_PF_DEF_Q_NUM, and force
754 		 * to trigger only one VF in v1 hardware.
755 		 *
756 		 * v2 hardware has no such problem.
757 		 */
758 		qm->qp_base = HZIP_PF_DEF_Q_NUM;
759 		qm->qp_num = HZIP_QUEUE_NUM_V1 - HZIP_PF_DEF_Q_NUM;
760 	}
761 
762 	return hisi_qm_init(qm);
763 }
764 
765 static int hisi_zip_probe_init(struct hisi_zip *hisi_zip)
766 {
767 	struct hisi_qm *qm = &hisi_zip->qm;
768 	int ret;
769 
770 	if (qm->fun_type == QM_HW_PF) {
771 		ret = hisi_zip_pf_probe_init(hisi_zip);
772 		if (ret)
773 			return ret;
774 	}
775 
776 	return 0;
777 }
778 
779 static int hisi_zip_probe(struct pci_dev *pdev, const struct pci_device_id *id)
780 {
781 	struct hisi_zip *hisi_zip;
782 	struct hisi_qm *qm;
783 	int ret;
784 
785 	hisi_zip = devm_kzalloc(&pdev->dev, sizeof(*hisi_zip), GFP_KERNEL);
786 	if (!hisi_zip)
787 		return -ENOMEM;
788 
789 	qm = &hisi_zip->qm;
790 
791 	ret = hisi_zip_qm_init(qm, pdev);
792 	if (ret) {
793 		pci_err(pdev, "Failed to init ZIP QM (%d)!\n", ret);
794 		return ret;
795 	}
796 
797 	ret = hisi_zip_probe_init(hisi_zip);
798 	if (ret) {
799 		pci_err(pdev, "Failed to probe (%d)!\n", ret);
800 		goto err_qm_uninit;
801 	}
802 
803 	ret = hisi_qm_start(qm);
804 	if (ret)
805 		goto err_qm_uninit;
806 
807 	ret = hisi_zip_debugfs_init(hisi_zip);
808 	if (ret)
809 		dev_err(&pdev->dev, "Failed to init debugfs (%d)!\n", ret);
810 
811 	hisi_qm_add_to_list(qm, &zip_devices);
812 
813 	if (qm->uacce) {
814 		ret = uacce_register(qm->uacce);
815 		if (ret)
816 			goto err_qm_uninit;
817 	}
818 
819 	if (qm->fun_type == QM_HW_PF && vfs_num > 0) {
820 		ret = hisi_qm_sriov_enable(pdev, vfs_num);
821 		if (ret < 0)
822 			goto err_remove_from_list;
823 	}
824 
825 	return 0;
826 
827 err_remove_from_list:
828 	hisi_qm_del_from_list(qm, &zip_devices);
829 	hisi_zip_debugfs_exit(hisi_zip);
830 	hisi_qm_stop(qm);
831 err_qm_uninit:
832 	hisi_qm_uninit(qm);
833 
834 	return ret;
835 }
836 
837 static void hisi_zip_remove(struct pci_dev *pdev)
838 {
839 	struct hisi_zip *hisi_zip = pci_get_drvdata(pdev);
840 	struct hisi_qm *qm = &hisi_zip->qm;
841 
842 	if (qm->fun_type == QM_HW_PF && qm->vfs_num)
843 		hisi_qm_sriov_disable(pdev);
844 
845 	hisi_zip_debugfs_exit(hisi_zip);
846 	hisi_qm_stop(qm);
847 
848 	hisi_qm_dev_err_uninit(qm);
849 	hisi_qm_uninit(qm);
850 	hisi_qm_del_from_list(qm, &zip_devices);
851 }
852 
853 static const struct pci_error_handlers hisi_zip_err_handler = {
854 	.error_detected	= hisi_qm_dev_err_detected,
855 	.slot_reset	= hisi_qm_dev_slot_reset,
856 	.reset_prepare	= hisi_qm_reset_prepare,
857 	.reset_done	= hisi_qm_reset_done,
858 };
859 
860 static struct pci_driver hisi_zip_pci_driver = {
861 	.name			= "hisi_zip",
862 	.id_table		= hisi_zip_dev_ids,
863 	.probe			= hisi_zip_probe,
864 	.remove			= hisi_zip_remove,
865 	.sriov_configure	= IS_ENABLED(CONFIG_PCI_IOV) ?
866 					hisi_qm_sriov_configure : NULL,
867 	.err_handler		= &hisi_zip_err_handler,
868 };
869 
870 static void hisi_zip_register_debugfs(void)
871 {
872 	if (!debugfs_initialized())
873 		return;
874 
875 	hzip_debugfs_root = debugfs_create_dir("hisi_zip", NULL);
876 }
877 
878 static void hisi_zip_unregister_debugfs(void)
879 {
880 	debugfs_remove_recursive(hzip_debugfs_root);
881 }
882 
883 static int __init hisi_zip_init(void)
884 {
885 	int ret;
886 
887 	hisi_qm_init_list(&zip_devices);
888 	hisi_zip_register_debugfs();
889 
890 	ret = pci_register_driver(&hisi_zip_pci_driver);
891 	if (ret < 0) {
892 		pr_err("Failed to register pci driver.\n");
893 		goto err_pci;
894 	}
895 
896 	ret = hisi_zip_register_to_crypto();
897 	if (ret < 0) {
898 		pr_err("Failed to register driver to crypto.\n");
899 		goto err_crypto;
900 	}
901 
902 	return 0;
903 
904 err_crypto:
905 	pci_unregister_driver(&hisi_zip_pci_driver);
906 err_pci:
907 	hisi_zip_unregister_debugfs();
908 
909 	return ret;
910 }
911 
912 static void __exit hisi_zip_exit(void)
913 {
914 	hisi_zip_unregister_from_crypto();
915 	pci_unregister_driver(&hisi_zip_pci_driver);
916 	hisi_zip_unregister_debugfs();
917 }
918 
919 module_init(hisi_zip_init);
920 module_exit(hisi_zip_exit);
921 
922 MODULE_LICENSE("GPL v2");
923 MODULE_AUTHOR("Zhou Wang <wangzhou1@hisilicon.com>");
924 MODULE_DESCRIPTION("Driver for HiSilicon ZIP accelerator");
925