1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2019 HiSilicon Limited. */ 3 #include <linux/acpi.h> 4 #include <linux/bitops.h> 5 #include <linux/debugfs.h> 6 #include <linux/init.h> 7 #include <linux/io.h> 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/pci.h> 11 #include <linux/pm_runtime.h> 12 #include <linux/seq_file.h> 13 #include <linux/topology.h> 14 #include <linux/uacce.h> 15 #include "zip.h" 16 17 #define PCI_DEVICE_ID_HUAWEI_ZIP_PF 0xa250 18 19 #define HZIP_QUEUE_NUM_V1 4096 20 21 #define HZIP_CLOCK_GATE_CTRL 0x301004 22 #define HZIP_DECOMP_CHECK_ENABLE BIT(16) 23 #define HZIP_FSM_MAX_CNT 0x301008 24 25 #define HZIP_PORT_ARCA_CHE_0 0x301040 26 #define HZIP_PORT_ARCA_CHE_1 0x301044 27 #define HZIP_PORT_AWCA_CHE_0 0x301060 28 #define HZIP_PORT_AWCA_CHE_1 0x301064 29 #define HZIP_CACHE_ALL_EN 0xffffffff 30 31 #define HZIP_BD_RUSER_32_63 0x301110 32 #define HZIP_SGL_RUSER_32_63 0x30111c 33 #define HZIP_DATA_RUSER_32_63 0x301128 34 #define HZIP_DATA_WUSER_32_63 0x301134 35 #define HZIP_BD_WUSER_32_63 0x301140 36 37 #define HZIP_QM_IDEL_STATUS 0x3040e4 38 39 #define HZIP_CORE_DFX_BASE 0x301000 40 #define HZIP_CLOCK_GATED_CONTL 0X301004 41 #define HZIP_CORE_DFX_COMP_0 0x302000 42 #define HZIP_CORE_DFX_COMP_1 0x303000 43 #define HZIP_CORE_DFX_DECOMP_0 0x304000 44 #define HZIP_CORE_DFX_DECOMP_1 0x305000 45 #define HZIP_CORE_DFX_DECOMP_2 0x306000 46 #define HZIP_CORE_DFX_DECOMP_3 0x307000 47 #define HZIP_CORE_DFX_DECOMP_4 0x308000 48 #define HZIP_CORE_DFX_DECOMP_5 0x309000 49 #define HZIP_CORE_REGS_BASE_LEN 0xB0 50 #define HZIP_CORE_REGS_DFX_LEN 0x28 51 52 #define HZIP_CORE_INT_SOURCE 0x3010A0 53 #define HZIP_CORE_INT_MASK_REG 0x3010A4 54 #define HZIP_CORE_INT_SET 0x3010A8 55 #define HZIP_CORE_INT_STATUS 0x3010AC 56 #define HZIP_CORE_INT_STATUS_M_ECC BIT(1) 57 #define HZIP_CORE_SRAM_ECC_ERR_INFO 0x301148 58 #define HZIP_CORE_INT_RAS_CE_ENB 0x301160 59 #define HZIP_CORE_INT_RAS_NFE_ENB 0x301164 60 #define HZIP_CORE_INT_RAS_FE_ENB 0x301168 61 #define HZIP_CORE_INT_RAS_FE_ENB_MASK 0x0 62 #define HZIP_OOO_SHUTDOWN_SEL 0x30120C 63 #define HZIP_SRAM_ECC_ERR_NUM_SHIFT 16 64 #define HZIP_SRAM_ECC_ERR_ADDR_SHIFT 24 65 #define HZIP_CORE_INT_MASK_ALL GENMASK(12, 0) 66 #define HZIP_SQE_SIZE 128 67 #define HZIP_PF_DEF_Q_NUM 64 68 #define HZIP_PF_DEF_Q_BASE 0 69 70 #define HZIP_SOFT_CTRL_CNT_CLR_CE 0x301000 71 #define HZIP_SOFT_CTRL_CNT_CLR_CE_BIT BIT(0) 72 #define HZIP_SOFT_CTRL_ZIP_CONTROL 0x30100C 73 #define HZIP_AXI_SHUTDOWN_ENABLE BIT(14) 74 #define HZIP_WR_PORT BIT(11) 75 76 #define HZIP_DEV_ALG_MAX_LEN 256 77 #define HZIP_ALG_ZLIB_BIT GENMASK(1, 0) 78 #define HZIP_ALG_GZIP_BIT GENMASK(3, 2) 79 #define HZIP_ALG_DEFLATE_BIT GENMASK(5, 4) 80 #define HZIP_ALG_LZ77_BIT GENMASK(7, 6) 81 82 #define HZIP_BUF_SIZE 22 83 #define HZIP_SQE_MASK_OFFSET 64 84 #define HZIP_SQE_MASK_LEN 48 85 86 #define HZIP_CNT_CLR_CE_EN BIT(0) 87 #define HZIP_RO_CNT_CLR_CE_EN BIT(2) 88 #define HZIP_RD_CNT_CLR_CE_EN (HZIP_CNT_CLR_CE_EN | \ 89 HZIP_RO_CNT_CLR_CE_EN) 90 91 #define HZIP_PREFETCH_CFG 0x3011B0 92 #define HZIP_SVA_TRANS 0x3011C4 93 #define HZIP_PREFETCH_ENABLE (~(BIT(26) | BIT(17) | BIT(0))) 94 #define HZIP_SVA_PREFETCH_DISABLE BIT(26) 95 #define HZIP_SVA_DISABLE_READY (BIT(26) | BIT(30)) 96 #define HZIP_SHAPER_RATE_COMPRESS 750 97 #define HZIP_SHAPER_RATE_DECOMPRESS 140 98 #define HZIP_DELAY_1_US 1 99 #define HZIP_POLL_TIMEOUT_US 1000 100 101 /* clock gating */ 102 #define HZIP_PEH_CFG_AUTO_GATE 0x3011A8 103 #define HZIP_PEH_CFG_AUTO_GATE_EN BIT(0) 104 #define HZIP_CORE_GATED_EN GENMASK(15, 8) 105 #define HZIP_CORE_GATED_OOO_EN BIT(29) 106 #define HZIP_CLOCK_GATED_EN (HZIP_CORE_GATED_EN | \ 107 HZIP_CORE_GATED_OOO_EN) 108 109 static const char hisi_zip_name[] = "hisi_zip"; 110 static struct dentry *hzip_debugfs_root; 111 112 struct hisi_zip_hw_error { 113 u32 int_msk; 114 const char *msg; 115 }; 116 117 struct zip_dfx_item { 118 const char *name; 119 u32 offset; 120 }; 121 122 struct zip_dev_alg { 123 u32 alg_msk; 124 const char *algs; 125 }; 126 127 static const struct zip_dev_alg zip_dev_algs[] = { { 128 .alg_msk = HZIP_ALG_ZLIB_BIT, 129 .algs = "zlib\n", 130 }, { 131 .alg_msk = HZIP_ALG_GZIP_BIT, 132 .algs = "gzip\n", 133 }, { 134 .alg_msk = HZIP_ALG_DEFLATE_BIT, 135 .algs = "deflate\n", 136 }, { 137 .alg_msk = HZIP_ALG_LZ77_BIT, 138 .algs = "lz77_zstd\n", 139 }, 140 }; 141 142 static struct hisi_qm_list zip_devices = { 143 .register_to_crypto = hisi_zip_register_to_crypto, 144 .unregister_from_crypto = hisi_zip_unregister_from_crypto, 145 }; 146 147 static struct zip_dfx_item zip_dfx_files[] = { 148 {"send_cnt", offsetof(struct hisi_zip_dfx, send_cnt)}, 149 {"recv_cnt", offsetof(struct hisi_zip_dfx, recv_cnt)}, 150 {"send_busy_cnt", offsetof(struct hisi_zip_dfx, send_busy_cnt)}, 151 {"err_bd_cnt", offsetof(struct hisi_zip_dfx, err_bd_cnt)}, 152 }; 153 154 static const struct hisi_zip_hw_error zip_hw_error[] = { 155 { .int_msk = BIT(0), .msg = "zip_ecc_1bitt_err" }, 156 { .int_msk = BIT(1), .msg = "zip_ecc_2bit_err" }, 157 { .int_msk = BIT(2), .msg = "zip_axi_rresp_err" }, 158 { .int_msk = BIT(3), .msg = "zip_axi_bresp_err" }, 159 { .int_msk = BIT(4), .msg = "zip_src_addr_parse_err" }, 160 { .int_msk = BIT(5), .msg = "zip_dst_addr_parse_err" }, 161 { .int_msk = BIT(6), .msg = "zip_pre_in_addr_err" }, 162 { .int_msk = BIT(7), .msg = "zip_pre_in_data_err" }, 163 { .int_msk = BIT(8), .msg = "zip_com_inf_err" }, 164 { .int_msk = BIT(9), .msg = "zip_enc_inf_err" }, 165 { .int_msk = BIT(10), .msg = "zip_pre_out_err" }, 166 { .int_msk = BIT(11), .msg = "zip_axi_poison_err" }, 167 { .int_msk = BIT(12), .msg = "zip_sva_err" }, 168 { /* sentinel */ } 169 }; 170 171 enum ctrl_debug_file_index { 172 HZIP_CLEAR_ENABLE, 173 HZIP_DEBUG_FILE_NUM, 174 }; 175 176 static const char * const ctrl_debug_file_name[] = { 177 [HZIP_CLEAR_ENABLE] = "clear_enable", 178 }; 179 180 struct ctrl_debug_file { 181 enum ctrl_debug_file_index index; 182 spinlock_t lock; 183 struct hisi_zip_ctrl *ctrl; 184 }; 185 186 /* 187 * One ZIP controller has one PF and multiple VFs, some global configurations 188 * which PF has need this structure. 189 * 190 * Just relevant for PF. 191 */ 192 struct hisi_zip_ctrl { 193 struct hisi_zip *hisi_zip; 194 struct ctrl_debug_file files[HZIP_DEBUG_FILE_NUM]; 195 }; 196 197 enum zip_cap_type { 198 ZIP_QM_NFE_MASK_CAP = 0x0, 199 ZIP_QM_RESET_MASK_CAP, 200 ZIP_QM_OOO_SHUTDOWN_MASK_CAP, 201 ZIP_QM_CE_MASK_CAP, 202 ZIP_NFE_MASK_CAP, 203 ZIP_RESET_MASK_CAP, 204 ZIP_OOO_SHUTDOWN_MASK_CAP, 205 ZIP_CE_MASK_CAP, 206 ZIP_CLUSTER_NUM_CAP, 207 ZIP_CORE_TYPE_NUM_CAP, 208 ZIP_CORE_NUM_CAP, 209 ZIP_CLUSTER_COMP_NUM_CAP, 210 ZIP_CLUSTER_DECOMP_NUM_CAP, 211 ZIP_DECOMP_ENABLE_BITMAP, 212 ZIP_COMP_ENABLE_BITMAP, 213 ZIP_DRV_ALG_BITMAP, 214 ZIP_DEV_ALG_BITMAP, 215 ZIP_CORE1_ALG_BITMAP, 216 ZIP_CORE2_ALG_BITMAP, 217 ZIP_CORE3_ALG_BITMAP, 218 ZIP_CORE4_ALG_BITMAP, 219 ZIP_CORE5_ALG_BITMAP, 220 ZIP_CAP_MAX 221 }; 222 223 static struct hisi_qm_cap_info zip_basic_cap_info[] = { 224 {ZIP_QM_NFE_MASK_CAP, 0x3124, 0, GENMASK(31, 0), 0x0, 0x1C57, 0x7C77}, 225 {ZIP_QM_RESET_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0xC57, 0x6C77}, 226 {ZIP_QM_OOO_SHUTDOWN_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0x4, 0x6C77}, 227 {ZIP_QM_CE_MASK_CAP, 0x312C, 0, GENMASK(31, 0), 0x0, 0x8, 0x8}, 228 {ZIP_NFE_MASK_CAP, 0x3130, 0, GENMASK(31, 0), 0x0, 0x7FE, 0x1FFE}, 229 {ZIP_RESET_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x7FE, 0x7FE}, 230 {ZIP_OOO_SHUTDOWN_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x2, 0x7FE}, 231 {ZIP_CE_MASK_CAP, 0x3138, 0, GENMASK(31, 0), 0x0, 0x1, 0x1}, 232 {ZIP_CLUSTER_NUM_CAP, 0x313C, 28, GENMASK(3, 0), 0x1, 0x1, 0x1}, 233 {ZIP_CORE_TYPE_NUM_CAP, 0x313C, 24, GENMASK(3, 0), 0x2, 0x2, 0x2}, 234 {ZIP_CORE_NUM_CAP, 0x313C, 16, GENMASK(7, 0), 0x8, 0x8, 0x5}, 235 {ZIP_CLUSTER_COMP_NUM_CAP, 0x313C, 8, GENMASK(7, 0), 0x2, 0x2, 0x2}, 236 {ZIP_CLUSTER_DECOMP_NUM_CAP, 0x313C, 0, GENMASK(7, 0), 0x6, 0x6, 0x3}, 237 {ZIP_DECOMP_ENABLE_BITMAP, 0x3140, 16, GENMASK(15, 0), 0xFC, 0xFC, 0x1C}, 238 {ZIP_COMP_ENABLE_BITMAP, 0x3140, 0, GENMASK(15, 0), 0x3, 0x3, 0x3}, 239 {ZIP_DRV_ALG_BITMAP, 0x3144, 0, GENMASK(31, 0), 0xF, 0xF, 0xF}, 240 {ZIP_DEV_ALG_BITMAP, 0x3148, 0, GENMASK(31, 0), 0xF, 0xF, 0xFF}, 241 {ZIP_CORE1_ALG_BITMAP, 0x314C, 0, GENMASK(31, 0), 0x5, 0x5, 0xD5}, 242 {ZIP_CORE2_ALG_BITMAP, 0x3150, 0, GENMASK(31, 0), 0x5, 0x5, 0xD5}, 243 {ZIP_CORE3_ALG_BITMAP, 0x3154, 0, GENMASK(31, 0), 0xA, 0xA, 0x2A}, 244 {ZIP_CORE4_ALG_BITMAP, 0x3158, 0, GENMASK(31, 0), 0xA, 0xA, 0x2A}, 245 {ZIP_CORE5_ALG_BITMAP, 0x315C, 0, GENMASK(31, 0), 0xA, 0xA, 0x2A}, 246 {ZIP_CAP_MAX, 0x317c, 0, GENMASK(0, 0), 0x0, 0x0, 0x0} 247 }; 248 249 enum { 250 HZIP_COMP_CORE0, 251 HZIP_COMP_CORE1, 252 HZIP_DECOMP_CORE0, 253 HZIP_DECOMP_CORE1, 254 HZIP_DECOMP_CORE2, 255 HZIP_DECOMP_CORE3, 256 HZIP_DECOMP_CORE4, 257 HZIP_DECOMP_CORE5, 258 }; 259 260 static const u64 core_offsets[] = { 261 [HZIP_COMP_CORE0] = 0x302000, 262 [HZIP_COMP_CORE1] = 0x303000, 263 [HZIP_DECOMP_CORE0] = 0x304000, 264 [HZIP_DECOMP_CORE1] = 0x305000, 265 [HZIP_DECOMP_CORE2] = 0x306000, 266 [HZIP_DECOMP_CORE3] = 0x307000, 267 [HZIP_DECOMP_CORE4] = 0x308000, 268 [HZIP_DECOMP_CORE5] = 0x309000, 269 }; 270 271 static const struct debugfs_reg32 hzip_dfx_regs[] = { 272 {"HZIP_GET_BD_NUM ", 0x00ull}, 273 {"HZIP_GET_RIGHT_BD ", 0x04ull}, 274 {"HZIP_GET_ERROR_BD ", 0x08ull}, 275 {"HZIP_DONE_BD_NUM ", 0x0cull}, 276 {"HZIP_WORK_CYCLE ", 0x10ull}, 277 {"HZIP_IDLE_CYCLE ", 0x18ull}, 278 {"HZIP_MAX_DELAY ", 0x20ull}, 279 {"HZIP_MIN_DELAY ", 0x24ull}, 280 {"HZIP_AVG_DELAY ", 0x28ull}, 281 {"HZIP_MEM_VISIBLE_DATA ", 0x30ull}, 282 {"HZIP_MEM_VISIBLE_ADDR ", 0x34ull}, 283 {"HZIP_CONSUMED_BYTE ", 0x38ull}, 284 {"HZIP_PRODUCED_BYTE ", 0x40ull}, 285 {"HZIP_COMP_INF ", 0x70ull}, 286 {"HZIP_PRE_OUT ", 0x78ull}, 287 {"HZIP_BD_RD ", 0x7cull}, 288 {"HZIP_BD_WR ", 0x80ull}, 289 {"HZIP_GET_BD_AXI_ERR_NUM ", 0x84ull}, 290 {"HZIP_GET_BD_PARSE_ERR_NUM ", 0x88ull}, 291 {"HZIP_ADD_BD_AXI_ERR_NUM ", 0x8cull}, 292 {"HZIP_DECOMP_STF_RELOAD_CURR_ST ", 0x94ull}, 293 {"HZIP_DECOMP_LZ77_CURR_ST ", 0x9cull}, 294 }; 295 296 static const struct debugfs_reg32 hzip_com_dfx_regs[] = { 297 {"HZIP_CLOCK_GATE_CTRL ", 0x301004}, 298 {"HZIP_CORE_INT_RAS_CE_ENB ", 0x301160}, 299 {"HZIP_CORE_INT_RAS_NFE_ENB ", 0x301164}, 300 {"HZIP_CORE_INT_RAS_FE_ENB ", 0x301168}, 301 {"HZIP_UNCOM_ERR_RAS_CTRL ", 0x30116C}, 302 }; 303 304 static const struct debugfs_reg32 hzip_dump_dfx_regs[] = { 305 {"HZIP_GET_BD_NUM ", 0x00ull}, 306 {"HZIP_GET_RIGHT_BD ", 0x04ull}, 307 {"HZIP_GET_ERROR_BD ", 0x08ull}, 308 {"HZIP_DONE_BD_NUM ", 0x0cull}, 309 {"HZIP_MAX_DELAY ", 0x20ull}, 310 }; 311 312 /* define the ZIP's dfx regs region and region length */ 313 static struct dfx_diff_registers hzip_diff_regs[] = { 314 { 315 .reg_offset = HZIP_CORE_DFX_BASE, 316 .reg_len = HZIP_CORE_REGS_BASE_LEN, 317 }, { 318 .reg_offset = HZIP_CORE_DFX_COMP_0, 319 .reg_len = HZIP_CORE_REGS_DFX_LEN, 320 }, { 321 .reg_offset = HZIP_CORE_DFX_COMP_1, 322 .reg_len = HZIP_CORE_REGS_DFX_LEN, 323 }, { 324 .reg_offset = HZIP_CORE_DFX_DECOMP_0, 325 .reg_len = HZIP_CORE_REGS_DFX_LEN, 326 }, { 327 .reg_offset = HZIP_CORE_DFX_DECOMP_1, 328 .reg_len = HZIP_CORE_REGS_DFX_LEN, 329 }, { 330 .reg_offset = HZIP_CORE_DFX_DECOMP_2, 331 .reg_len = HZIP_CORE_REGS_DFX_LEN, 332 }, { 333 .reg_offset = HZIP_CORE_DFX_DECOMP_3, 334 .reg_len = HZIP_CORE_REGS_DFX_LEN, 335 }, { 336 .reg_offset = HZIP_CORE_DFX_DECOMP_4, 337 .reg_len = HZIP_CORE_REGS_DFX_LEN, 338 }, { 339 .reg_offset = HZIP_CORE_DFX_DECOMP_5, 340 .reg_len = HZIP_CORE_REGS_DFX_LEN, 341 }, 342 }; 343 344 static int hzip_diff_regs_show(struct seq_file *s, void *unused) 345 { 346 struct hisi_qm *qm = s->private; 347 348 hisi_qm_acc_diff_regs_dump(qm, s, qm->debug.acc_diff_regs, 349 ARRAY_SIZE(hzip_diff_regs)); 350 351 return 0; 352 } 353 DEFINE_SHOW_ATTRIBUTE(hzip_diff_regs); 354 static const struct kernel_param_ops zip_uacce_mode_ops = { 355 .set = uacce_mode_set, 356 .get = param_get_int, 357 }; 358 359 /* 360 * uacce_mode = 0 means zip only register to crypto, 361 * uacce_mode = 1 means zip both register to crypto and uacce. 362 */ 363 static u32 uacce_mode = UACCE_MODE_NOUACCE; 364 module_param_cb(uacce_mode, &zip_uacce_mode_ops, &uacce_mode, 0444); 365 MODULE_PARM_DESC(uacce_mode, UACCE_MODE_DESC); 366 367 static bool pf_q_num_flag; 368 static int pf_q_num_set(const char *val, const struct kernel_param *kp) 369 { 370 pf_q_num_flag = true; 371 372 return q_num_set(val, kp, PCI_DEVICE_ID_HUAWEI_ZIP_PF); 373 } 374 375 static const struct kernel_param_ops pf_q_num_ops = { 376 .set = pf_q_num_set, 377 .get = param_get_int, 378 }; 379 380 static u32 pf_q_num = HZIP_PF_DEF_Q_NUM; 381 module_param_cb(pf_q_num, &pf_q_num_ops, &pf_q_num, 0444); 382 MODULE_PARM_DESC(pf_q_num, "Number of queues in PF(v1 2-4096, v2 2-1024)"); 383 384 static const struct kernel_param_ops vfs_num_ops = { 385 .set = vfs_num_set, 386 .get = param_get_int, 387 }; 388 389 static u32 vfs_num; 390 module_param_cb(vfs_num, &vfs_num_ops, &vfs_num, 0444); 391 MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)"); 392 393 static const struct pci_device_id hisi_zip_dev_ids[] = { 394 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_ZIP_PF) }, 395 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_ZIP_VF) }, 396 { 0, } 397 }; 398 MODULE_DEVICE_TABLE(pci, hisi_zip_dev_ids); 399 400 int zip_create_qps(struct hisi_qp **qps, int qp_num, int node) 401 { 402 if (node == NUMA_NO_NODE) 403 node = cpu_to_node(smp_processor_id()); 404 405 return hisi_qm_alloc_qps_node(&zip_devices, qp_num, 0, node, qps); 406 } 407 408 bool hisi_zip_alg_support(struct hisi_qm *qm, u32 alg) 409 { 410 u32 cap_val; 411 412 cap_val = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_DRV_ALG_BITMAP, qm->cap_ver); 413 if ((alg & cap_val) == alg) 414 return true; 415 416 return false; 417 } 418 419 static int hisi_zip_set_qm_algs(struct hisi_qm *qm) 420 { 421 struct device *dev = &qm->pdev->dev; 422 char *algs, *ptr; 423 u32 alg_mask; 424 int i; 425 426 if (!qm->use_sva) 427 return 0; 428 429 algs = devm_kzalloc(dev, HZIP_DEV_ALG_MAX_LEN * sizeof(char), GFP_KERNEL); 430 if (!algs) 431 return -ENOMEM; 432 433 alg_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_DEV_ALG_BITMAP, qm->cap_ver); 434 435 for (i = 0; i < ARRAY_SIZE(zip_dev_algs); i++) 436 if (alg_mask & zip_dev_algs[i].alg_msk) 437 strcat(algs, zip_dev_algs[i].algs); 438 439 ptr = strrchr(algs, '\n'); 440 if (ptr) 441 *ptr = '\0'; 442 443 qm->uacce->algs = algs; 444 445 return 0; 446 } 447 448 static void hisi_zip_open_sva_prefetch(struct hisi_qm *qm) 449 { 450 u32 val; 451 int ret; 452 453 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) 454 return; 455 456 /* Enable prefetch */ 457 val = readl_relaxed(qm->io_base + HZIP_PREFETCH_CFG); 458 val &= HZIP_PREFETCH_ENABLE; 459 writel(val, qm->io_base + HZIP_PREFETCH_CFG); 460 461 ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_PREFETCH_CFG, 462 val, !(val & HZIP_SVA_PREFETCH_DISABLE), 463 HZIP_DELAY_1_US, HZIP_POLL_TIMEOUT_US); 464 if (ret) 465 pci_err(qm->pdev, "failed to open sva prefetch\n"); 466 } 467 468 static void hisi_zip_close_sva_prefetch(struct hisi_qm *qm) 469 { 470 u32 val; 471 int ret; 472 473 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) 474 return; 475 476 val = readl_relaxed(qm->io_base + HZIP_PREFETCH_CFG); 477 val |= HZIP_SVA_PREFETCH_DISABLE; 478 writel(val, qm->io_base + HZIP_PREFETCH_CFG); 479 480 ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_SVA_TRANS, 481 val, !(val & HZIP_SVA_DISABLE_READY), 482 HZIP_DELAY_1_US, HZIP_POLL_TIMEOUT_US); 483 if (ret) 484 pci_err(qm->pdev, "failed to close sva prefetch\n"); 485 } 486 487 static void hisi_zip_enable_clock_gate(struct hisi_qm *qm) 488 { 489 u32 val; 490 491 if (qm->ver < QM_HW_V3) 492 return; 493 494 val = readl(qm->io_base + HZIP_CLOCK_GATE_CTRL); 495 val |= HZIP_CLOCK_GATED_EN; 496 writel(val, qm->io_base + HZIP_CLOCK_GATE_CTRL); 497 498 val = readl(qm->io_base + HZIP_PEH_CFG_AUTO_GATE); 499 val |= HZIP_PEH_CFG_AUTO_GATE_EN; 500 writel(val, qm->io_base + HZIP_PEH_CFG_AUTO_GATE); 501 } 502 503 static int hisi_zip_set_user_domain_and_cache(struct hisi_qm *qm) 504 { 505 void __iomem *base = qm->io_base; 506 u32 dcomp_bm, comp_bm; 507 508 /* qm user domain */ 509 writel(AXUSER_BASE, base + QM_ARUSER_M_CFG_1); 510 writel(ARUSER_M_CFG_ENABLE, base + QM_ARUSER_M_CFG_ENABLE); 511 writel(AXUSER_BASE, base + QM_AWUSER_M_CFG_1); 512 writel(AWUSER_M_CFG_ENABLE, base + QM_AWUSER_M_CFG_ENABLE); 513 writel(WUSER_M_CFG_ENABLE, base + QM_WUSER_M_CFG_ENABLE); 514 515 /* qm cache */ 516 writel(AXI_M_CFG, base + QM_AXI_M_CFG); 517 writel(AXI_M_CFG_ENABLE, base + QM_AXI_M_CFG_ENABLE); 518 519 /* disable FLR triggered by BME(bus master enable) */ 520 writel(PEH_AXUSER_CFG, base + QM_PEH_AXUSER_CFG); 521 writel(PEH_AXUSER_CFG_ENABLE, base + QM_PEH_AXUSER_CFG_ENABLE); 522 523 /* cache */ 524 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_ARCA_CHE_0); 525 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_ARCA_CHE_1); 526 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_AWCA_CHE_0); 527 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_AWCA_CHE_1); 528 529 /* user domain configurations */ 530 writel(AXUSER_BASE, base + HZIP_BD_RUSER_32_63); 531 writel(AXUSER_BASE, base + HZIP_BD_WUSER_32_63); 532 533 if (qm->use_sva && qm->ver == QM_HW_V2) { 534 writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_DATA_RUSER_32_63); 535 writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_DATA_WUSER_32_63); 536 writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_SGL_RUSER_32_63); 537 } else { 538 writel(AXUSER_BASE, base + HZIP_DATA_RUSER_32_63); 539 writel(AXUSER_BASE, base + HZIP_DATA_WUSER_32_63); 540 writel(AXUSER_BASE, base + HZIP_SGL_RUSER_32_63); 541 } 542 543 /* let's open all compression/decompression cores */ 544 dcomp_bm = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 545 ZIP_DECOMP_ENABLE_BITMAP, qm->cap_ver); 546 comp_bm = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 547 ZIP_COMP_ENABLE_BITMAP, qm->cap_ver); 548 writel(HZIP_DECOMP_CHECK_ENABLE | dcomp_bm | comp_bm, base + HZIP_CLOCK_GATE_CTRL); 549 550 /* enable sqc,cqc writeback */ 551 writel(SQC_CACHE_ENABLE | CQC_CACHE_ENABLE | SQC_CACHE_WB_ENABLE | 552 CQC_CACHE_WB_ENABLE | FIELD_PREP(SQC_CACHE_WB_THRD, 1) | 553 FIELD_PREP(CQC_CACHE_WB_THRD, 1), base + QM_CACHE_CTL); 554 555 hisi_zip_enable_clock_gate(qm); 556 557 return 0; 558 } 559 560 static void hisi_zip_master_ooo_ctrl(struct hisi_qm *qm, bool enable) 561 { 562 u32 val1, val2; 563 564 val1 = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 565 if (enable) { 566 val1 |= HZIP_AXI_SHUTDOWN_ENABLE; 567 val2 = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 568 ZIP_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 569 } else { 570 val1 &= ~HZIP_AXI_SHUTDOWN_ENABLE; 571 val2 = 0x0; 572 } 573 574 if (qm->ver > QM_HW_V2) 575 writel(val2, qm->io_base + HZIP_OOO_SHUTDOWN_SEL); 576 577 writel(val1, qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 578 } 579 580 static void hisi_zip_hw_error_enable(struct hisi_qm *qm) 581 { 582 u32 nfe, ce; 583 584 if (qm->ver == QM_HW_V1) { 585 writel(HZIP_CORE_INT_MASK_ALL, 586 qm->io_base + HZIP_CORE_INT_MASK_REG); 587 dev_info(&qm->pdev->dev, "Does not support hw error handle\n"); 588 return; 589 } 590 591 nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_NFE_MASK_CAP, qm->cap_ver); 592 ce = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CE_MASK_CAP, qm->cap_ver); 593 594 /* clear ZIP hw error source if having */ 595 writel(ce | nfe | HZIP_CORE_INT_RAS_FE_ENB_MASK, qm->io_base + HZIP_CORE_INT_SOURCE); 596 597 /* configure error type */ 598 writel(ce, qm->io_base + HZIP_CORE_INT_RAS_CE_ENB); 599 writel(HZIP_CORE_INT_RAS_FE_ENB_MASK, qm->io_base + HZIP_CORE_INT_RAS_FE_ENB); 600 writel(nfe, qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 601 602 hisi_zip_master_ooo_ctrl(qm, true); 603 604 /* enable ZIP hw error interrupts */ 605 writel(0, qm->io_base + HZIP_CORE_INT_MASK_REG); 606 } 607 608 static void hisi_zip_hw_error_disable(struct hisi_qm *qm) 609 { 610 u32 nfe, ce; 611 612 /* disable ZIP hw error interrupts */ 613 nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_NFE_MASK_CAP, qm->cap_ver); 614 ce = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CE_MASK_CAP, qm->cap_ver); 615 writel(ce | nfe | HZIP_CORE_INT_RAS_FE_ENB_MASK, qm->io_base + HZIP_CORE_INT_MASK_REG); 616 617 hisi_zip_master_ooo_ctrl(qm, false); 618 } 619 620 static inline struct hisi_qm *file_to_qm(struct ctrl_debug_file *file) 621 { 622 struct hisi_zip *hisi_zip = file->ctrl->hisi_zip; 623 624 return &hisi_zip->qm; 625 } 626 627 static u32 clear_enable_read(struct hisi_qm *qm) 628 { 629 return readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) & 630 HZIP_SOFT_CTRL_CNT_CLR_CE_BIT; 631 } 632 633 static int clear_enable_write(struct hisi_qm *qm, u32 val) 634 { 635 u32 tmp; 636 637 if (val != 1 && val != 0) 638 return -EINVAL; 639 640 tmp = (readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) & 641 ~HZIP_SOFT_CTRL_CNT_CLR_CE_BIT) | val; 642 writel(tmp, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE); 643 644 return 0; 645 } 646 647 static ssize_t hisi_zip_ctrl_debug_read(struct file *filp, char __user *buf, 648 size_t count, loff_t *pos) 649 { 650 struct ctrl_debug_file *file = filp->private_data; 651 struct hisi_qm *qm = file_to_qm(file); 652 char tbuf[HZIP_BUF_SIZE]; 653 u32 val; 654 int ret; 655 656 ret = hisi_qm_get_dfx_access(qm); 657 if (ret) 658 return ret; 659 660 spin_lock_irq(&file->lock); 661 switch (file->index) { 662 case HZIP_CLEAR_ENABLE: 663 val = clear_enable_read(qm); 664 break; 665 default: 666 goto err_input; 667 } 668 spin_unlock_irq(&file->lock); 669 670 hisi_qm_put_dfx_access(qm); 671 ret = scnprintf(tbuf, sizeof(tbuf), "%u\n", val); 672 return simple_read_from_buffer(buf, count, pos, tbuf, ret); 673 674 err_input: 675 spin_unlock_irq(&file->lock); 676 hisi_qm_put_dfx_access(qm); 677 return -EINVAL; 678 } 679 680 static ssize_t hisi_zip_ctrl_debug_write(struct file *filp, 681 const char __user *buf, 682 size_t count, loff_t *pos) 683 { 684 struct ctrl_debug_file *file = filp->private_data; 685 struct hisi_qm *qm = file_to_qm(file); 686 char tbuf[HZIP_BUF_SIZE]; 687 unsigned long val; 688 int len, ret; 689 690 if (*pos != 0) 691 return 0; 692 693 if (count >= HZIP_BUF_SIZE) 694 return -ENOSPC; 695 696 len = simple_write_to_buffer(tbuf, HZIP_BUF_SIZE - 1, pos, buf, count); 697 if (len < 0) 698 return len; 699 700 tbuf[len] = '\0'; 701 ret = kstrtoul(tbuf, 0, &val); 702 if (ret) 703 return ret; 704 705 ret = hisi_qm_get_dfx_access(qm); 706 if (ret) 707 return ret; 708 709 spin_lock_irq(&file->lock); 710 switch (file->index) { 711 case HZIP_CLEAR_ENABLE: 712 ret = clear_enable_write(qm, val); 713 if (ret) 714 goto err_input; 715 break; 716 default: 717 ret = -EINVAL; 718 goto err_input; 719 } 720 721 ret = count; 722 723 err_input: 724 spin_unlock_irq(&file->lock); 725 hisi_qm_put_dfx_access(qm); 726 return ret; 727 } 728 729 static const struct file_operations ctrl_debug_fops = { 730 .owner = THIS_MODULE, 731 .open = simple_open, 732 .read = hisi_zip_ctrl_debug_read, 733 .write = hisi_zip_ctrl_debug_write, 734 }; 735 736 static int zip_debugfs_atomic64_set(void *data, u64 val) 737 { 738 if (val) 739 return -EINVAL; 740 741 atomic64_set((atomic64_t *)data, 0); 742 743 return 0; 744 } 745 746 static int zip_debugfs_atomic64_get(void *data, u64 *val) 747 { 748 *val = atomic64_read((atomic64_t *)data); 749 750 return 0; 751 } 752 753 DEFINE_DEBUGFS_ATTRIBUTE(zip_atomic64_ops, zip_debugfs_atomic64_get, 754 zip_debugfs_atomic64_set, "%llu\n"); 755 756 static int hisi_zip_regs_show(struct seq_file *s, void *unused) 757 { 758 hisi_qm_regs_dump(s, s->private); 759 760 return 0; 761 } 762 763 DEFINE_SHOW_ATTRIBUTE(hisi_zip_regs); 764 765 static int hisi_zip_core_debug_init(struct hisi_qm *qm) 766 { 767 u32 zip_core_num, zip_comp_core_num; 768 struct device *dev = &qm->pdev->dev; 769 struct debugfs_regset32 *regset; 770 struct dentry *tmp_d; 771 char buf[HZIP_BUF_SIZE]; 772 int i; 773 774 zip_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CORE_NUM_CAP, qm->cap_ver); 775 zip_comp_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CLUSTER_COMP_NUM_CAP, 776 qm->cap_ver); 777 778 for (i = 0; i < zip_core_num; i++) { 779 if (i < zip_comp_core_num) 780 scnprintf(buf, sizeof(buf), "comp_core%d", i); 781 else 782 scnprintf(buf, sizeof(buf), "decomp_core%d", 783 i - zip_comp_core_num); 784 785 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 786 if (!regset) 787 return -ENOENT; 788 789 regset->regs = hzip_dfx_regs; 790 regset->nregs = ARRAY_SIZE(hzip_dfx_regs); 791 regset->base = qm->io_base + core_offsets[i]; 792 regset->dev = dev; 793 794 tmp_d = debugfs_create_dir(buf, qm->debug.debug_root); 795 debugfs_create_file("regs", 0444, tmp_d, regset, 796 &hisi_zip_regs_fops); 797 } 798 799 return 0; 800 } 801 802 static void hisi_zip_dfx_debug_init(struct hisi_qm *qm) 803 { 804 struct dfx_diff_registers *hzip_regs = qm->debug.acc_diff_regs; 805 struct hisi_zip *zip = container_of(qm, struct hisi_zip, qm); 806 struct hisi_zip_dfx *dfx = &zip->dfx; 807 struct dentry *tmp_dir; 808 void *data; 809 int i; 810 811 tmp_dir = debugfs_create_dir("zip_dfx", qm->debug.debug_root); 812 for (i = 0; i < ARRAY_SIZE(zip_dfx_files); i++) { 813 data = (atomic64_t *)((uintptr_t)dfx + zip_dfx_files[i].offset); 814 debugfs_create_file(zip_dfx_files[i].name, 815 0644, tmp_dir, data, 816 &zip_atomic64_ops); 817 } 818 819 if (qm->fun_type == QM_HW_PF && hzip_regs) 820 debugfs_create_file("diff_regs", 0444, tmp_dir, 821 qm, &hzip_diff_regs_fops); 822 } 823 824 static int hisi_zip_ctrl_debug_init(struct hisi_qm *qm) 825 { 826 struct hisi_zip *zip = container_of(qm, struct hisi_zip, qm); 827 int i; 828 829 for (i = HZIP_CLEAR_ENABLE; i < HZIP_DEBUG_FILE_NUM; i++) { 830 spin_lock_init(&zip->ctrl->files[i].lock); 831 zip->ctrl->files[i].ctrl = zip->ctrl; 832 zip->ctrl->files[i].index = i; 833 834 debugfs_create_file(ctrl_debug_file_name[i], 0600, 835 qm->debug.debug_root, 836 zip->ctrl->files + i, 837 &ctrl_debug_fops); 838 } 839 840 return hisi_zip_core_debug_init(qm); 841 } 842 843 static int hisi_zip_debugfs_init(struct hisi_qm *qm) 844 { 845 struct device *dev = &qm->pdev->dev; 846 struct dentry *dev_d; 847 int ret; 848 849 dev_d = debugfs_create_dir(dev_name(dev), hzip_debugfs_root); 850 851 qm->debug.sqe_mask_offset = HZIP_SQE_MASK_OFFSET; 852 qm->debug.sqe_mask_len = HZIP_SQE_MASK_LEN; 853 qm->debug.debug_root = dev_d; 854 ret = hisi_qm_regs_debugfs_init(qm, hzip_diff_regs, ARRAY_SIZE(hzip_diff_regs)); 855 if (ret) { 856 dev_warn(dev, "Failed to init ZIP diff regs!\n"); 857 goto debugfs_remove; 858 } 859 860 hisi_qm_debug_init(qm); 861 862 if (qm->fun_type == QM_HW_PF) { 863 ret = hisi_zip_ctrl_debug_init(qm); 864 if (ret) 865 goto failed_to_create; 866 } 867 868 hisi_zip_dfx_debug_init(qm); 869 870 return 0; 871 872 failed_to_create: 873 hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(hzip_diff_regs)); 874 debugfs_remove: 875 debugfs_remove_recursive(hzip_debugfs_root); 876 return ret; 877 } 878 879 /* hisi_zip_debug_regs_clear() - clear the zip debug regs */ 880 static void hisi_zip_debug_regs_clear(struct hisi_qm *qm) 881 { 882 int i, j; 883 884 /* enable register read_clear bit */ 885 writel(HZIP_RD_CNT_CLR_CE_EN, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE); 886 for (i = 0; i < ARRAY_SIZE(core_offsets); i++) 887 for (j = 0; j < ARRAY_SIZE(hzip_dfx_regs); j++) 888 readl(qm->io_base + core_offsets[i] + 889 hzip_dfx_regs[j].offset); 890 891 /* disable register read_clear bit */ 892 writel(0x0, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE); 893 894 hisi_qm_debug_regs_clear(qm); 895 } 896 897 static void hisi_zip_debugfs_exit(struct hisi_qm *qm) 898 { 899 hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(hzip_diff_regs)); 900 901 debugfs_remove_recursive(qm->debug.debug_root); 902 903 if (qm->fun_type == QM_HW_PF) { 904 hisi_zip_debug_regs_clear(qm); 905 qm->debug.curr_qm_qp_num = 0; 906 } 907 } 908 909 static int hisi_zip_show_last_regs_init(struct hisi_qm *qm) 910 { 911 int core_dfx_regs_num = ARRAY_SIZE(hzip_dump_dfx_regs); 912 int com_dfx_regs_num = ARRAY_SIZE(hzip_com_dfx_regs); 913 struct qm_debug *debug = &qm->debug; 914 void __iomem *io_base; 915 u32 zip_core_num; 916 int i, j, idx; 917 918 zip_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CORE_NUM_CAP, qm->cap_ver); 919 920 debug->last_words = kcalloc(core_dfx_regs_num * zip_core_num + com_dfx_regs_num, 921 sizeof(unsigned int), GFP_KERNEL); 922 if (!debug->last_words) 923 return -ENOMEM; 924 925 for (i = 0; i < com_dfx_regs_num; i++) { 926 io_base = qm->io_base + hzip_com_dfx_regs[i].offset; 927 debug->last_words[i] = readl_relaxed(io_base); 928 } 929 930 for (i = 0; i < zip_core_num; i++) { 931 io_base = qm->io_base + core_offsets[i]; 932 for (j = 0; j < core_dfx_regs_num; j++) { 933 idx = com_dfx_regs_num + i * core_dfx_regs_num + j; 934 debug->last_words[idx] = readl_relaxed( 935 io_base + hzip_dump_dfx_regs[j].offset); 936 } 937 } 938 939 return 0; 940 } 941 942 static void hisi_zip_show_last_regs_uninit(struct hisi_qm *qm) 943 { 944 struct qm_debug *debug = &qm->debug; 945 946 if (qm->fun_type == QM_HW_VF || !debug->last_words) 947 return; 948 949 kfree(debug->last_words); 950 debug->last_words = NULL; 951 } 952 953 static void hisi_zip_show_last_dfx_regs(struct hisi_qm *qm) 954 { 955 int core_dfx_regs_num = ARRAY_SIZE(hzip_dump_dfx_regs); 956 int com_dfx_regs_num = ARRAY_SIZE(hzip_com_dfx_regs); 957 u32 zip_core_num, zip_comp_core_num; 958 struct qm_debug *debug = &qm->debug; 959 char buf[HZIP_BUF_SIZE]; 960 void __iomem *base; 961 int i, j, idx; 962 u32 val; 963 964 if (qm->fun_type == QM_HW_VF || !debug->last_words) 965 return; 966 967 for (i = 0; i < com_dfx_regs_num; i++) { 968 val = readl_relaxed(qm->io_base + hzip_com_dfx_regs[i].offset); 969 if (debug->last_words[i] != val) 970 pci_info(qm->pdev, "com_dfx: %s \t= 0x%08x => 0x%08x\n", 971 hzip_com_dfx_regs[i].name, debug->last_words[i], val); 972 } 973 974 zip_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CORE_NUM_CAP, qm->cap_ver); 975 zip_comp_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CLUSTER_COMP_NUM_CAP, 976 qm->cap_ver); 977 for (i = 0; i < zip_core_num; i++) { 978 if (i < zip_comp_core_num) 979 scnprintf(buf, sizeof(buf), "Comp_core-%d", i); 980 else 981 scnprintf(buf, sizeof(buf), "Decomp_core-%d", 982 i - zip_comp_core_num); 983 base = qm->io_base + core_offsets[i]; 984 985 pci_info(qm->pdev, "==>%s:\n", buf); 986 /* dump last word for dfx regs during control resetting */ 987 for (j = 0; j < core_dfx_regs_num; j++) { 988 idx = com_dfx_regs_num + i * core_dfx_regs_num + j; 989 val = readl_relaxed(base + hzip_dump_dfx_regs[j].offset); 990 if (debug->last_words[idx] != val) 991 pci_info(qm->pdev, "%s \t= 0x%08x => 0x%08x\n", 992 hzip_dump_dfx_regs[j].name, 993 debug->last_words[idx], val); 994 } 995 } 996 } 997 998 static void hisi_zip_log_hw_error(struct hisi_qm *qm, u32 err_sts) 999 { 1000 const struct hisi_zip_hw_error *err = zip_hw_error; 1001 struct device *dev = &qm->pdev->dev; 1002 u32 err_val; 1003 1004 while (err->msg) { 1005 if (err->int_msk & err_sts) { 1006 dev_err(dev, "%s [error status=0x%x] found\n", 1007 err->msg, err->int_msk); 1008 1009 if (err->int_msk & HZIP_CORE_INT_STATUS_M_ECC) { 1010 err_val = readl(qm->io_base + 1011 HZIP_CORE_SRAM_ECC_ERR_INFO); 1012 dev_err(dev, "hisi-zip multi ecc sram num=0x%x\n", 1013 ((err_val >> 1014 HZIP_SRAM_ECC_ERR_NUM_SHIFT) & 0xFF)); 1015 } 1016 } 1017 err++; 1018 } 1019 } 1020 1021 static u32 hisi_zip_get_hw_err_status(struct hisi_qm *qm) 1022 { 1023 return readl(qm->io_base + HZIP_CORE_INT_STATUS); 1024 } 1025 1026 static void hisi_zip_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts) 1027 { 1028 u32 nfe; 1029 1030 writel(err_sts, qm->io_base + HZIP_CORE_INT_SOURCE); 1031 nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_NFE_MASK_CAP, qm->cap_ver); 1032 writel(nfe, qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 1033 } 1034 1035 static void hisi_zip_open_axi_master_ooo(struct hisi_qm *qm) 1036 { 1037 u32 val; 1038 1039 val = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 1040 1041 writel(val & ~HZIP_AXI_SHUTDOWN_ENABLE, 1042 qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 1043 1044 writel(val | HZIP_AXI_SHUTDOWN_ENABLE, 1045 qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 1046 } 1047 1048 static void hisi_zip_close_axi_master_ooo(struct hisi_qm *qm) 1049 { 1050 u32 nfe_enb; 1051 1052 /* Disable ECC Mbit error report. */ 1053 nfe_enb = readl(qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 1054 writel(nfe_enb & ~HZIP_CORE_INT_STATUS_M_ECC, 1055 qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 1056 1057 /* Inject zip ECC Mbit error to block master ooo. */ 1058 writel(HZIP_CORE_INT_STATUS_M_ECC, 1059 qm->io_base + HZIP_CORE_INT_SET); 1060 } 1061 1062 static void hisi_zip_err_info_init(struct hisi_qm *qm) 1063 { 1064 struct hisi_qm_err_info *err_info = &qm->err_info; 1065 1066 err_info->fe = HZIP_CORE_INT_RAS_FE_ENB_MASK; 1067 err_info->ce = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_QM_CE_MASK_CAP, qm->cap_ver); 1068 err_info->nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1069 ZIP_QM_NFE_MASK_CAP, qm->cap_ver); 1070 err_info->ecc_2bits_mask = HZIP_CORE_INT_STATUS_M_ECC; 1071 err_info->qm_shutdown_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1072 ZIP_QM_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 1073 err_info->dev_shutdown_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1074 ZIP_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 1075 err_info->qm_reset_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1076 ZIP_QM_RESET_MASK_CAP, qm->cap_ver); 1077 err_info->dev_reset_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1078 ZIP_RESET_MASK_CAP, qm->cap_ver); 1079 err_info->msi_wr_port = HZIP_WR_PORT; 1080 err_info->acpi_rst = "ZRST"; 1081 } 1082 1083 static const struct hisi_qm_err_ini hisi_zip_err_ini = { 1084 .hw_init = hisi_zip_set_user_domain_and_cache, 1085 .hw_err_enable = hisi_zip_hw_error_enable, 1086 .hw_err_disable = hisi_zip_hw_error_disable, 1087 .get_dev_hw_err_status = hisi_zip_get_hw_err_status, 1088 .clear_dev_hw_err_status = hisi_zip_clear_hw_err_status, 1089 .log_dev_hw_err = hisi_zip_log_hw_error, 1090 .open_axi_master_ooo = hisi_zip_open_axi_master_ooo, 1091 .close_axi_master_ooo = hisi_zip_close_axi_master_ooo, 1092 .open_sva_prefetch = hisi_zip_open_sva_prefetch, 1093 .close_sva_prefetch = hisi_zip_close_sva_prefetch, 1094 .show_last_dfx_regs = hisi_zip_show_last_dfx_regs, 1095 .err_info_init = hisi_zip_err_info_init, 1096 }; 1097 1098 static int hisi_zip_pf_probe_init(struct hisi_zip *hisi_zip) 1099 { 1100 struct hisi_qm *qm = &hisi_zip->qm; 1101 struct hisi_zip_ctrl *ctrl; 1102 int ret; 1103 1104 ctrl = devm_kzalloc(&qm->pdev->dev, sizeof(*ctrl), GFP_KERNEL); 1105 if (!ctrl) 1106 return -ENOMEM; 1107 1108 hisi_zip->ctrl = ctrl; 1109 ctrl->hisi_zip = hisi_zip; 1110 qm->err_ini = &hisi_zip_err_ini; 1111 qm->err_ini->err_info_init(qm); 1112 1113 ret = hisi_zip_set_user_domain_and_cache(qm); 1114 if (ret) 1115 return ret; 1116 1117 hisi_zip_open_sva_prefetch(qm); 1118 hisi_qm_dev_err_init(qm); 1119 hisi_zip_debug_regs_clear(qm); 1120 1121 ret = hisi_zip_show_last_regs_init(qm); 1122 if (ret) 1123 pci_err(qm->pdev, "Failed to init last word regs!\n"); 1124 1125 return ret; 1126 } 1127 1128 static int hisi_zip_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) 1129 { 1130 int ret; 1131 1132 qm->pdev = pdev; 1133 qm->ver = pdev->revision; 1134 qm->mode = uacce_mode; 1135 qm->sqe_size = HZIP_SQE_SIZE; 1136 qm->dev_name = hisi_zip_name; 1137 1138 qm->fun_type = (pdev->device == PCI_DEVICE_ID_HUAWEI_ZIP_PF) ? 1139 QM_HW_PF : QM_HW_VF; 1140 if (qm->fun_type == QM_HW_PF) { 1141 qm->qp_base = HZIP_PF_DEF_Q_BASE; 1142 qm->qp_num = pf_q_num; 1143 qm->debug.curr_qm_qp_num = pf_q_num; 1144 qm->qm_list = &zip_devices; 1145 if (pf_q_num_flag) 1146 set_bit(QM_MODULE_PARAM, &qm->misc_ctl); 1147 } else if (qm->fun_type == QM_HW_VF && qm->ver == QM_HW_V1) { 1148 /* 1149 * have no way to get qm configure in VM in v1 hardware, 1150 * so currently force PF to uses HZIP_PF_DEF_Q_NUM, and force 1151 * to trigger only one VF in v1 hardware. 1152 * 1153 * v2 hardware has no such problem. 1154 */ 1155 qm->qp_base = HZIP_PF_DEF_Q_NUM; 1156 qm->qp_num = HZIP_QUEUE_NUM_V1 - HZIP_PF_DEF_Q_NUM; 1157 } 1158 1159 ret = hisi_qm_init(qm); 1160 if (ret) { 1161 pci_err(qm->pdev, "Failed to init zip qm configures!\n"); 1162 return ret; 1163 } 1164 1165 ret = hisi_zip_set_qm_algs(qm); 1166 if (ret) { 1167 pci_err(qm->pdev, "Failed to set zip algs!\n"); 1168 hisi_qm_uninit(qm); 1169 } 1170 1171 return ret; 1172 } 1173 1174 static void hisi_zip_qm_uninit(struct hisi_qm *qm) 1175 { 1176 hisi_qm_uninit(qm); 1177 } 1178 1179 static int hisi_zip_probe_init(struct hisi_zip *hisi_zip) 1180 { 1181 u32 type_rate = HZIP_SHAPER_RATE_COMPRESS; 1182 struct hisi_qm *qm = &hisi_zip->qm; 1183 int ret; 1184 1185 if (qm->fun_type == QM_HW_PF) { 1186 ret = hisi_zip_pf_probe_init(hisi_zip); 1187 if (ret) 1188 return ret; 1189 /* enable shaper type 0 */ 1190 if (qm->ver >= QM_HW_V3) { 1191 type_rate |= QM_SHAPER_ENABLE; 1192 1193 /* ZIP need to enable shaper type 1 */ 1194 type_rate |= HZIP_SHAPER_RATE_DECOMPRESS << QM_SHAPER_TYPE1_OFFSET; 1195 qm->type_rate = type_rate; 1196 } 1197 } 1198 1199 return 0; 1200 } 1201 1202 static int hisi_zip_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1203 { 1204 struct hisi_zip *hisi_zip; 1205 struct hisi_qm *qm; 1206 int ret; 1207 1208 hisi_zip = devm_kzalloc(&pdev->dev, sizeof(*hisi_zip), GFP_KERNEL); 1209 if (!hisi_zip) 1210 return -ENOMEM; 1211 1212 qm = &hisi_zip->qm; 1213 1214 ret = hisi_zip_qm_init(qm, pdev); 1215 if (ret) { 1216 pci_err(pdev, "Failed to init ZIP QM (%d)!\n", ret); 1217 return ret; 1218 } 1219 1220 ret = hisi_zip_probe_init(hisi_zip); 1221 if (ret) { 1222 pci_err(pdev, "Failed to probe (%d)!\n", ret); 1223 goto err_qm_uninit; 1224 } 1225 1226 ret = hisi_qm_start(qm); 1227 if (ret) 1228 goto err_dev_err_uninit; 1229 1230 ret = hisi_zip_debugfs_init(qm); 1231 if (ret) 1232 pci_err(pdev, "failed to init debugfs (%d)!\n", ret); 1233 1234 ret = hisi_qm_alg_register(qm, &zip_devices); 1235 if (ret < 0) { 1236 pci_err(pdev, "failed to register driver to crypto!\n"); 1237 goto err_qm_stop; 1238 } 1239 1240 if (qm->uacce) { 1241 ret = uacce_register(qm->uacce); 1242 if (ret) { 1243 pci_err(pdev, "failed to register uacce (%d)!\n", ret); 1244 goto err_qm_alg_unregister; 1245 } 1246 } 1247 1248 if (qm->fun_type == QM_HW_PF && vfs_num > 0) { 1249 ret = hisi_qm_sriov_enable(pdev, vfs_num); 1250 if (ret < 0) 1251 goto err_qm_alg_unregister; 1252 } 1253 1254 hisi_qm_pm_init(qm); 1255 1256 return 0; 1257 1258 err_qm_alg_unregister: 1259 hisi_qm_alg_unregister(qm, &zip_devices); 1260 1261 err_qm_stop: 1262 hisi_zip_debugfs_exit(qm); 1263 hisi_qm_stop(qm, QM_NORMAL); 1264 1265 err_dev_err_uninit: 1266 hisi_zip_show_last_regs_uninit(qm); 1267 hisi_qm_dev_err_uninit(qm); 1268 1269 err_qm_uninit: 1270 hisi_zip_qm_uninit(qm); 1271 1272 return ret; 1273 } 1274 1275 static void hisi_zip_remove(struct pci_dev *pdev) 1276 { 1277 struct hisi_qm *qm = pci_get_drvdata(pdev); 1278 1279 hisi_qm_pm_uninit(qm); 1280 hisi_qm_wait_task_finish(qm, &zip_devices); 1281 hisi_qm_alg_unregister(qm, &zip_devices); 1282 1283 if (qm->fun_type == QM_HW_PF && qm->vfs_num) 1284 hisi_qm_sriov_disable(pdev, true); 1285 1286 hisi_zip_debugfs_exit(qm); 1287 hisi_qm_stop(qm, QM_NORMAL); 1288 hisi_zip_show_last_regs_uninit(qm); 1289 hisi_qm_dev_err_uninit(qm); 1290 hisi_zip_qm_uninit(qm); 1291 } 1292 1293 static const struct dev_pm_ops hisi_zip_pm_ops = { 1294 SET_RUNTIME_PM_OPS(hisi_qm_suspend, hisi_qm_resume, NULL) 1295 }; 1296 1297 static const struct pci_error_handlers hisi_zip_err_handler = { 1298 .error_detected = hisi_qm_dev_err_detected, 1299 .slot_reset = hisi_qm_dev_slot_reset, 1300 .reset_prepare = hisi_qm_reset_prepare, 1301 .reset_done = hisi_qm_reset_done, 1302 }; 1303 1304 static struct pci_driver hisi_zip_pci_driver = { 1305 .name = "hisi_zip", 1306 .id_table = hisi_zip_dev_ids, 1307 .probe = hisi_zip_probe, 1308 .remove = hisi_zip_remove, 1309 .sriov_configure = IS_ENABLED(CONFIG_PCI_IOV) ? 1310 hisi_qm_sriov_configure : NULL, 1311 .err_handler = &hisi_zip_err_handler, 1312 .shutdown = hisi_qm_dev_shutdown, 1313 .driver.pm = &hisi_zip_pm_ops, 1314 }; 1315 1316 struct pci_driver *hisi_zip_get_pf_driver(void) 1317 { 1318 return &hisi_zip_pci_driver; 1319 } 1320 EXPORT_SYMBOL_GPL(hisi_zip_get_pf_driver); 1321 1322 static void hisi_zip_register_debugfs(void) 1323 { 1324 if (!debugfs_initialized()) 1325 return; 1326 1327 hzip_debugfs_root = debugfs_create_dir("hisi_zip", NULL); 1328 } 1329 1330 static void hisi_zip_unregister_debugfs(void) 1331 { 1332 debugfs_remove_recursive(hzip_debugfs_root); 1333 } 1334 1335 static int __init hisi_zip_init(void) 1336 { 1337 int ret; 1338 1339 hisi_qm_init_list(&zip_devices); 1340 hisi_zip_register_debugfs(); 1341 1342 ret = pci_register_driver(&hisi_zip_pci_driver); 1343 if (ret < 0) { 1344 hisi_zip_unregister_debugfs(); 1345 pr_err("Failed to register pci driver.\n"); 1346 } 1347 1348 return ret; 1349 } 1350 1351 static void __exit hisi_zip_exit(void) 1352 { 1353 pci_unregister_driver(&hisi_zip_pci_driver); 1354 hisi_zip_unregister_debugfs(); 1355 } 1356 1357 module_init(hisi_zip_init); 1358 module_exit(hisi_zip_exit); 1359 1360 MODULE_LICENSE("GPL v2"); 1361 MODULE_AUTHOR("Zhou Wang <wangzhou1@hisilicon.com>"); 1362 MODULE_DESCRIPTION("Driver for HiSilicon ZIP accelerator"); 1363