1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2019 HiSilicon Limited. */
3 #include <linux/acpi.h>
4 #include <linux/aer.h>
5 #include <linux/bitops.h>
6 #include <linux/debugfs.h>
7 #include <linux/init.h>
8 #include <linux/io.h>
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/pci.h>
12 #include <linux/seq_file.h>
13 #include <linux/topology.h>
14 #include <linux/uacce.h>
15 #include "zip.h"
16 
17 #define PCI_DEVICE_ID_ZIP_PF		0xa250
18 #define PCI_DEVICE_ID_ZIP_VF		0xa251
19 
20 #define HZIP_QUEUE_NUM_V1		4096
21 #define HZIP_QUEUE_NUM_V2		1024
22 
23 #define HZIP_CLOCK_GATE_CTRL		0x301004
24 #define COMP0_ENABLE			BIT(0)
25 #define COMP1_ENABLE			BIT(1)
26 #define DECOMP0_ENABLE			BIT(2)
27 #define DECOMP1_ENABLE			BIT(3)
28 #define DECOMP2_ENABLE			BIT(4)
29 #define DECOMP3_ENABLE			BIT(5)
30 #define DECOMP4_ENABLE			BIT(6)
31 #define DECOMP5_ENABLE			BIT(7)
32 #define HZIP_ALL_COMP_DECOMP_EN		(COMP0_ENABLE | COMP1_ENABLE | \
33 					 DECOMP0_ENABLE | DECOMP1_ENABLE | \
34 					 DECOMP2_ENABLE | DECOMP3_ENABLE | \
35 					 DECOMP4_ENABLE | DECOMP5_ENABLE)
36 #define HZIP_DECOMP_CHECK_ENABLE	BIT(16)
37 #define HZIP_FSM_MAX_CNT		0x301008
38 
39 #define HZIP_PORT_ARCA_CHE_0		0x301040
40 #define HZIP_PORT_ARCA_CHE_1		0x301044
41 #define HZIP_PORT_AWCA_CHE_0		0x301060
42 #define HZIP_PORT_AWCA_CHE_1		0x301064
43 #define HZIP_CACHE_ALL_EN		0xffffffff
44 
45 #define HZIP_BD_RUSER_32_63		0x301110
46 #define HZIP_SGL_RUSER_32_63		0x30111c
47 #define HZIP_DATA_RUSER_32_63		0x301128
48 #define HZIP_DATA_WUSER_32_63		0x301134
49 #define HZIP_BD_WUSER_32_63		0x301140
50 
51 #define HZIP_QM_IDEL_STATUS		0x3040e4
52 
53 #define HZIP_CORE_DEBUG_COMP_0		0x302000
54 #define HZIP_CORE_DEBUG_COMP_1		0x303000
55 #define HZIP_CORE_DEBUG_DECOMP_0	0x304000
56 #define HZIP_CORE_DEBUG_DECOMP_1	0x305000
57 #define HZIP_CORE_DEBUG_DECOMP_2	0x306000
58 #define HZIP_CORE_DEBUG_DECOMP_3	0x307000
59 #define HZIP_CORE_DEBUG_DECOMP_4	0x308000
60 #define HZIP_CORE_DEBUG_DECOMP_5	0x309000
61 
62 #define HZIP_CORE_INT_SOURCE		0x3010A0
63 #define HZIP_CORE_INT_MASK_REG		0x3010A4
64 #define HZIP_CORE_INT_SET		0x3010A8
65 #define HZIP_CORE_INT_STATUS		0x3010AC
66 #define HZIP_CORE_INT_STATUS_M_ECC	BIT(1)
67 #define HZIP_CORE_SRAM_ECC_ERR_INFO	0x301148
68 #define HZIP_CORE_INT_RAS_CE_ENB	0x301160
69 #define HZIP_CORE_INT_RAS_CE_ENABLE	0x1
70 #define HZIP_CORE_INT_RAS_NFE_ENB	0x301164
71 #define HZIP_CORE_INT_RAS_FE_ENB        0x301168
72 #define HZIP_CORE_INT_RAS_NFE_ENABLE	0x7FE
73 #define HZIP_SRAM_ECC_ERR_NUM_SHIFT	16
74 #define HZIP_SRAM_ECC_ERR_ADDR_SHIFT	24
75 #define HZIP_CORE_INT_MASK_ALL		GENMASK(10, 0)
76 #define HZIP_COMP_CORE_NUM		2
77 #define HZIP_DECOMP_CORE_NUM		6
78 #define HZIP_CORE_NUM			(HZIP_COMP_CORE_NUM + \
79 					 HZIP_DECOMP_CORE_NUM)
80 #define HZIP_SQE_SIZE			128
81 #define HZIP_SQ_SIZE			(HZIP_SQE_SIZE * QM_Q_DEPTH)
82 #define HZIP_PF_DEF_Q_NUM		64
83 #define HZIP_PF_DEF_Q_BASE		0
84 
85 #define HZIP_SOFT_CTRL_CNT_CLR_CE	0x301000
86 #define HZIP_SOFT_CTRL_CNT_CLR_CE_BIT	BIT(0)
87 #define HZIP_SOFT_CTRL_ZIP_CONTROL	0x30100C
88 #define HZIP_AXI_SHUTDOWN_ENABLE	BIT(14)
89 #define HZIP_WR_PORT			BIT(11)
90 
91 #define HZIP_BUF_SIZE			22
92 #define HZIP_SQE_MASK_OFFSET		64
93 #define HZIP_SQE_MASK_LEN		48
94 
95 #define HZIP_CNT_CLR_CE_EN		BIT(0)
96 #define HZIP_RO_CNT_CLR_CE_EN		BIT(2)
97 #define HZIP_RD_CNT_CLR_CE_EN		(HZIP_CNT_CLR_CE_EN | \
98 					 HZIP_RO_CNT_CLR_CE_EN)
99 
100 static const char hisi_zip_name[] = "hisi_zip";
101 static struct dentry *hzip_debugfs_root;
102 
103 struct hisi_zip_hw_error {
104 	u32 int_msk;
105 	const char *msg;
106 };
107 
108 struct zip_dfx_item {
109 	const char *name;
110 	u32 offset;
111 };
112 
113 static struct hisi_qm_list zip_devices = {
114 	.register_to_crypto	= hisi_zip_register_to_crypto,
115 	.unregister_from_crypto	= hisi_zip_unregister_from_crypto,
116 };
117 
118 static struct zip_dfx_item zip_dfx_files[] = {
119 	{"send_cnt", offsetof(struct hisi_zip_dfx, send_cnt)},
120 	{"recv_cnt", offsetof(struct hisi_zip_dfx, recv_cnt)},
121 	{"send_busy_cnt", offsetof(struct hisi_zip_dfx, send_busy_cnt)},
122 	{"err_bd_cnt", offsetof(struct hisi_zip_dfx, err_bd_cnt)},
123 };
124 
125 static const struct hisi_zip_hw_error zip_hw_error[] = {
126 	{ .int_msk = BIT(0), .msg = "zip_ecc_1bitt_err" },
127 	{ .int_msk = BIT(1), .msg = "zip_ecc_2bit_err" },
128 	{ .int_msk = BIT(2), .msg = "zip_axi_rresp_err" },
129 	{ .int_msk = BIT(3), .msg = "zip_axi_bresp_err" },
130 	{ .int_msk = BIT(4), .msg = "zip_src_addr_parse_err" },
131 	{ .int_msk = BIT(5), .msg = "zip_dst_addr_parse_err" },
132 	{ .int_msk = BIT(6), .msg = "zip_pre_in_addr_err" },
133 	{ .int_msk = BIT(7), .msg = "zip_pre_in_data_err" },
134 	{ .int_msk = BIT(8), .msg = "zip_com_inf_err" },
135 	{ .int_msk = BIT(9), .msg = "zip_enc_inf_err" },
136 	{ .int_msk = BIT(10), .msg = "zip_pre_out_err" },
137 	{ /* sentinel */ }
138 };
139 
140 enum ctrl_debug_file_index {
141 	HZIP_CURRENT_QM,
142 	HZIP_CLEAR_ENABLE,
143 	HZIP_DEBUG_FILE_NUM,
144 };
145 
146 static const char * const ctrl_debug_file_name[] = {
147 	[HZIP_CURRENT_QM]   = "current_qm",
148 	[HZIP_CLEAR_ENABLE] = "clear_enable",
149 };
150 
151 struct ctrl_debug_file {
152 	enum ctrl_debug_file_index index;
153 	spinlock_t lock;
154 	struct hisi_zip_ctrl *ctrl;
155 };
156 
157 /*
158  * One ZIP controller has one PF and multiple VFs, some global configurations
159  * which PF has need this structure.
160  *
161  * Just relevant for PF.
162  */
163 struct hisi_zip_ctrl {
164 	struct hisi_zip *hisi_zip;
165 	struct ctrl_debug_file files[HZIP_DEBUG_FILE_NUM];
166 };
167 
168 enum {
169 	HZIP_COMP_CORE0,
170 	HZIP_COMP_CORE1,
171 	HZIP_DECOMP_CORE0,
172 	HZIP_DECOMP_CORE1,
173 	HZIP_DECOMP_CORE2,
174 	HZIP_DECOMP_CORE3,
175 	HZIP_DECOMP_CORE4,
176 	HZIP_DECOMP_CORE5,
177 };
178 
179 static const u64 core_offsets[] = {
180 	[HZIP_COMP_CORE0]   = 0x302000,
181 	[HZIP_COMP_CORE1]   = 0x303000,
182 	[HZIP_DECOMP_CORE0] = 0x304000,
183 	[HZIP_DECOMP_CORE1] = 0x305000,
184 	[HZIP_DECOMP_CORE2] = 0x306000,
185 	[HZIP_DECOMP_CORE3] = 0x307000,
186 	[HZIP_DECOMP_CORE4] = 0x308000,
187 	[HZIP_DECOMP_CORE5] = 0x309000,
188 };
189 
190 static const struct debugfs_reg32 hzip_dfx_regs[] = {
191 	{"HZIP_GET_BD_NUM                ",  0x00ull},
192 	{"HZIP_GET_RIGHT_BD              ",  0x04ull},
193 	{"HZIP_GET_ERROR_BD              ",  0x08ull},
194 	{"HZIP_DONE_BD_NUM               ",  0x0cull},
195 	{"HZIP_WORK_CYCLE                ",  0x10ull},
196 	{"HZIP_IDLE_CYCLE                ",  0x18ull},
197 	{"HZIP_MAX_DELAY                 ",  0x20ull},
198 	{"HZIP_MIN_DELAY                 ",  0x24ull},
199 	{"HZIP_AVG_DELAY                 ",  0x28ull},
200 	{"HZIP_MEM_VISIBLE_DATA          ",  0x30ull},
201 	{"HZIP_MEM_VISIBLE_ADDR          ",  0x34ull},
202 	{"HZIP_COMSUMED_BYTE             ",  0x38ull},
203 	{"HZIP_PRODUCED_BYTE             ",  0x40ull},
204 	{"HZIP_COMP_INF                  ",  0x70ull},
205 	{"HZIP_PRE_OUT                   ",  0x78ull},
206 	{"HZIP_BD_RD                     ",  0x7cull},
207 	{"HZIP_BD_WR                     ",  0x80ull},
208 	{"HZIP_GET_BD_AXI_ERR_NUM        ",  0x84ull},
209 	{"HZIP_GET_BD_PARSE_ERR_NUM      ",  0x88ull},
210 	{"HZIP_ADD_BD_AXI_ERR_NUM        ",  0x8cull},
211 	{"HZIP_DECOMP_STF_RELOAD_CURR_ST ",  0x94ull},
212 	{"HZIP_DECOMP_LZ77_CURR_ST       ",  0x9cull},
213 };
214 
215 static const struct kernel_param_ops zip_uacce_mode_ops = {
216 	.set = uacce_mode_set,
217 	.get = param_get_int,
218 };
219 
220 /*
221  * uacce_mode = 0 means zip only register to crypto,
222  * uacce_mode = 1 means zip both register to crypto and uacce.
223  */
224 static u32 uacce_mode = UACCE_MODE_NOUACCE;
225 module_param_cb(uacce_mode, &zip_uacce_mode_ops, &uacce_mode, 0444);
226 MODULE_PARM_DESC(uacce_mode, UACCE_MODE_DESC);
227 
228 static int pf_q_num_set(const char *val, const struct kernel_param *kp)
229 {
230 	return q_num_set(val, kp, PCI_DEVICE_ID_ZIP_PF);
231 }
232 
233 static const struct kernel_param_ops pf_q_num_ops = {
234 	.set = pf_q_num_set,
235 	.get = param_get_int,
236 };
237 
238 static u32 pf_q_num = HZIP_PF_DEF_Q_NUM;
239 module_param_cb(pf_q_num, &pf_q_num_ops, &pf_q_num, 0444);
240 MODULE_PARM_DESC(pf_q_num, "Number of queues in PF(v1 2-4096, v2 2-1024)");
241 
242 static const struct kernel_param_ops vfs_num_ops = {
243 	.set = vfs_num_set,
244 	.get = param_get_int,
245 };
246 
247 static u32 vfs_num;
248 module_param_cb(vfs_num, &vfs_num_ops, &vfs_num, 0444);
249 MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)");
250 
251 static const struct pci_device_id hisi_zip_dev_ids[] = {
252 	{ PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_ZIP_PF) },
253 	{ PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_ZIP_VF) },
254 	{ 0, }
255 };
256 MODULE_DEVICE_TABLE(pci, hisi_zip_dev_ids);
257 
258 int zip_create_qps(struct hisi_qp **qps, int qp_num, int node)
259 {
260 	if (node == NUMA_NO_NODE)
261 		node = cpu_to_node(smp_processor_id());
262 
263 	return hisi_qm_alloc_qps_node(&zip_devices, qp_num, 0, node, qps);
264 }
265 
266 static int hisi_zip_set_user_domain_and_cache(struct hisi_qm *qm)
267 {
268 	void __iomem *base = qm->io_base;
269 
270 	/* qm user domain */
271 	writel(AXUSER_BASE, base + QM_ARUSER_M_CFG_1);
272 	writel(ARUSER_M_CFG_ENABLE, base + QM_ARUSER_M_CFG_ENABLE);
273 	writel(AXUSER_BASE, base + QM_AWUSER_M_CFG_1);
274 	writel(AWUSER_M_CFG_ENABLE, base + QM_AWUSER_M_CFG_ENABLE);
275 	writel(WUSER_M_CFG_ENABLE, base + QM_WUSER_M_CFG_ENABLE);
276 
277 	/* qm cache */
278 	writel(AXI_M_CFG, base + QM_AXI_M_CFG);
279 	writel(AXI_M_CFG_ENABLE, base + QM_AXI_M_CFG_ENABLE);
280 
281 	/* disable FLR triggered by BME(bus master enable) */
282 	writel(PEH_AXUSER_CFG, base + QM_PEH_AXUSER_CFG);
283 	writel(PEH_AXUSER_CFG_ENABLE, base + QM_PEH_AXUSER_CFG_ENABLE);
284 
285 	/* cache */
286 	writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_ARCA_CHE_0);
287 	writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_ARCA_CHE_1);
288 	writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_AWCA_CHE_0);
289 	writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_AWCA_CHE_1);
290 
291 	/* user domain configurations */
292 	writel(AXUSER_BASE, base + HZIP_BD_RUSER_32_63);
293 	writel(AXUSER_BASE, base + HZIP_SGL_RUSER_32_63);
294 	writel(AXUSER_BASE, base + HZIP_BD_WUSER_32_63);
295 
296 	if (qm->use_sva && qm->ver == QM_HW_V2) {
297 		writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_DATA_RUSER_32_63);
298 		writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_DATA_WUSER_32_63);
299 	} else {
300 		writel(AXUSER_BASE, base + HZIP_DATA_RUSER_32_63);
301 		writel(AXUSER_BASE, base + HZIP_DATA_WUSER_32_63);
302 	}
303 
304 	/* let's open all compression/decompression cores */
305 	writel(HZIP_DECOMP_CHECK_ENABLE | HZIP_ALL_COMP_DECOMP_EN,
306 	       base + HZIP_CLOCK_GATE_CTRL);
307 
308 	/* enable sqc,cqc writeback */
309 	writel(SQC_CACHE_ENABLE | CQC_CACHE_ENABLE | SQC_CACHE_WB_ENABLE |
310 	       CQC_CACHE_WB_ENABLE | FIELD_PREP(SQC_CACHE_WB_THRD, 1) |
311 	       FIELD_PREP(CQC_CACHE_WB_THRD, 1), base + QM_CACHE_CTL);
312 
313 	return 0;
314 }
315 
316 static void hisi_zip_hw_error_enable(struct hisi_qm *qm)
317 {
318 	u32 val;
319 
320 	if (qm->ver == QM_HW_V1) {
321 		writel(HZIP_CORE_INT_MASK_ALL,
322 		       qm->io_base + HZIP_CORE_INT_MASK_REG);
323 		dev_info(&qm->pdev->dev, "Does not support hw error handle\n");
324 		return;
325 	}
326 
327 	/* clear ZIP hw error source if having */
328 	writel(HZIP_CORE_INT_MASK_ALL, qm->io_base + HZIP_CORE_INT_SOURCE);
329 
330 	/* configure error type */
331 	writel(HZIP_CORE_INT_RAS_CE_ENABLE,
332 	       qm->io_base + HZIP_CORE_INT_RAS_CE_ENB);
333 	writel(0x0, qm->io_base + HZIP_CORE_INT_RAS_FE_ENB);
334 	writel(HZIP_CORE_INT_RAS_NFE_ENABLE,
335 	       qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB);
336 
337 	/* enable ZIP hw error interrupts */
338 	writel(0, qm->io_base + HZIP_CORE_INT_MASK_REG);
339 
340 	/* enable ZIP block master OOO when m-bit error occur */
341 	val = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);
342 	val = val | HZIP_AXI_SHUTDOWN_ENABLE;
343 	writel(val, qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);
344 }
345 
346 static void hisi_zip_hw_error_disable(struct hisi_qm *qm)
347 {
348 	u32 val;
349 
350 	/* disable ZIP hw error interrupts */
351 	writel(HZIP_CORE_INT_MASK_ALL, qm->io_base + HZIP_CORE_INT_MASK_REG);
352 
353 	/* disable ZIP block master OOO when m-bit error occur */
354 	val = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);
355 	val = val & ~HZIP_AXI_SHUTDOWN_ENABLE;
356 	writel(val, qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);
357 }
358 
359 static inline struct hisi_qm *file_to_qm(struct ctrl_debug_file *file)
360 {
361 	struct hisi_zip *hisi_zip = file->ctrl->hisi_zip;
362 
363 	return &hisi_zip->qm;
364 }
365 
366 static u32 current_qm_read(struct ctrl_debug_file *file)
367 {
368 	struct hisi_qm *qm = file_to_qm(file);
369 
370 	return readl(qm->io_base + QM_DFX_MB_CNT_VF);
371 }
372 
373 static int current_qm_write(struct ctrl_debug_file *file, u32 val)
374 {
375 	struct hisi_qm *qm = file_to_qm(file);
376 	u32 vfq_num;
377 	u32 tmp;
378 
379 	if (val > qm->vfs_num)
380 		return -EINVAL;
381 
382 	/* According PF or VF Dev ID to calculation curr_qm_qp_num and store */
383 	if (val == 0) {
384 		qm->debug.curr_qm_qp_num = qm->qp_num;
385 	} else {
386 		vfq_num = (qm->ctrl_qp_num - qm->qp_num) / qm->vfs_num;
387 		if (val == qm->vfs_num)
388 			qm->debug.curr_qm_qp_num = qm->ctrl_qp_num -
389 				qm->qp_num - (qm->vfs_num - 1) * vfq_num;
390 		else
391 			qm->debug.curr_qm_qp_num = vfq_num;
392 	}
393 
394 	writel(val, qm->io_base + QM_DFX_MB_CNT_VF);
395 	writel(val, qm->io_base + QM_DFX_DB_CNT_VF);
396 
397 	tmp = val |
398 	      (readl(qm->io_base + QM_DFX_SQE_CNT_VF_SQN) & CURRENT_Q_MASK);
399 	writel(tmp, qm->io_base + QM_DFX_SQE_CNT_VF_SQN);
400 
401 	tmp = val |
402 	      (readl(qm->io_base + QM_DFX_CQE_CNT_VF_CQN) & CURRENT_Q_MASK);
403 	writel(tmp, qm->io_base + QM_DFX_CQE_CNT_VF_CQN);
404 
405 	return  0;
406 }
407 
408 static u32 clear_enable_read(struct ctrl_debug_file *file)
409 {
410 	struct hisi_qm *qm = file_to_qm(file);
411 
412 	return readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) &
413 		     HZIP_SOFT_CTRL_CNT_CLR_CE_BIT;
414 }
415 
416 static int clear_enable_write(struct ctrl_debug_file *file, u32 val)
417 {
418 	struct hisi_qm *qm = file_to_qm(file);
419 	u32 tmp;
420 
421 	if (val != 1 && val != 0)
422 		return -EINVAL;
423 
424 	tmp = (readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) &
425 	       ~HZIP_SOFT_CTRL_CNT_CLR_CE_BIT) | val;
426 	writel(tmp, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE);
427 
428 	return  0;
429 }
430 
431 static ssize_t hisi_zip_ctrl_debug_read(struct file *filp, char __user *buf,
432 					size_t count, loff_t *pos)
433 {
434 	struct ctrl_debug_file *file = filp->private_data;
435 	char tbuf[HZIP_BUF_SIZE];
436 	u32 val;
437 	int ret;
438 
439 	spin_lock_irq(&file->lock);
440 	switch (file->index) {
441 	case HZIP_CURRENT_QM:
442 		val = current_qm_read(file);
443 		break;
444 	case HZIP_CLEAR_ENABLE:
445 		val = clear_enable_read(file);
446 		break;
447 	default:
448 		spin_unlock_irq(&file->lock);
449 		return -EINVAL;
450 	}
451 	spin_unlock_irq(&file->lock);
452 	ret = scnprintf(tbuf, sizeof(tbuf), "%u\n", val);
453 	return simple_read_from_buffer(buf, count, pos, tbuf, ret);
454 }
455 
456 static ssize_t hisi_zip_ctrl_debug_write(struct file *filp,
457 					 const char __user *buf,
458 					 size_t count, loff_t *pos)
459 {
460 	struct ctrl_debug_file *file = filp->private_data;
461 	char tbuf[HZIP_BUF_SIZE];
462 	unsigned long val;
463 	int len, ret;
464 
465 	if (*pos != 0)
466 		return 0;
467 
468 	if (count >= HZIP_BUF_SIZE)
469 		return -ENOSPC;
470 
471 	len = simple_write_to_buffer(tbuf, HZIP_BUF_SIZE - 1, pos, buf, count);
472 	if (len < 0)
473 		return len;
474 
475 	tbuf[len] = '\0';
476 	if (kstrtoul(tbuf, 0, &val))
477 		return -EFAULT;
478 
479 	spin_lock_irq(&file->lock);
480 	switch (file->index) {
481 	case HZIP_CURRENT_QM:
482 		ret = current_qm_write(file, val);
483 		if (ret)
484 			goto err_input;
485 		break;
486 	case HZIP_CLEAR_ENABLE:
487 		ret = clear_enable_write(file, val);
488 		if (ret)
489 			goto err_input;
490 		break;
491 	default:
492 		ret = -EINVAL;
493 		goto err_input;
494 	}
495 	spin_unlock_irq(&file->lock);
496 
497 	return count;
498 
499 err_input:
500 	spin_unlock_irq(&file->lock);
501 	return ret;
502 }
503 
504 static const struct file_operations ctrl_debug_fops = {
505 	.owner = THIS_MODULE,
506 	.open = simple_open,
507 	.read = hisi_zip_ctrl_debug_read,
508 	.write = hisi_zip_ctrl_debug_write,
509 };
510 
511 static int zip_debugfs_atomic64_set(void *data, u64 val)
512 {
513 	if (val)
514 		return -EINVAL;
515 
516 	atomic64_set((atomic64_t *)data, 0);
517 
518 	return 0;
519 }
520 
521 static int zip_debugfs_atomic64_get(void *data, u64 *val)
522 {
523 	*val = atomic64_read((atomic64_t *)data);
524 
525 	return 0;
526 }
527 
528 DEFINE_DEBUGFS_ATTRIBUTE(zip_atomic64_ops, zip_debugfs_atomic64_get,
529 			 zip_debugfs_atomic64_set, "%llu\n");
530 
531 static int hisi_zip_core_debug_init(struct hisi_qm *qm)
532 {
533 	struct device *dev = &qm->pdev->dev;
534 	struct debugfs_regset32 *regset;
535 	struct dentry *tmp_d;
536 	char buf[HZIP_BUF_SIZE];
537 	int i;
538 
539 	for (i = 0; i < HZIP_CORE_NUM; i++) {
540 		if (i < HZIP_COMP_CORE_NUM)
541 			scnprintf(buf, sizeof(buf), "comp_core%d", i);
542 		else
543 			scnprintf(buf, sizeof(buf), "decomp_core%d",
544 				  i - HZIP_COMP_CORE_NUM);
545 
546 		regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL);
547 		if (!regset)
548 			return -ENOENT;
549 
550 		regset->regs = hzip_dfx_regs;
551 		regset->nregs = ARRAY_SIZE(hzip_dfx_regs);
552 		regset->base = qm->io_base + core_offsets[i];
553 
554 		tmp_d = debugfs_create_dir(buf, qm->debug.debug_root);
555 		debugfs_create_regset32("regs", 0444, tmp_d, regset);
556 	}
557 
558 	return 0;
559 }
560 
561 static void hisi_zip_dfx_debug_init(struct hisi_qm *qm)
562 {
563 	struct hisi_zip *zip = container_of(qm, struct hisi_zip, qm);
564 	struct hisi_zip_dfx *dfx = &zip->dfx;
565 	struct dentry *tmp_dir;
566 	void *data;
567 	int i;
568 
569 	tmp_dir = debugfs_create_dir("zip_dfx", qm->debug.debug_root);
570 	for (i = 0; i < ARRAY_SIZE(zip_dfx_files); i++) {
571 		data = (atomic64_t *)((uintptr_t)dfx + zip_dfx_files[i].offset);
572 		debugfs_create_file(zip_dfx_files[i].name,
573 				    0644, tmp_dir, data,
574 				    &zip_atomic64_ops);
575 	}
576 }
577 
578 static int hisi_zip_ctrl_debug_init(struct hisi_qm *qm)
579 {
580 	struct hisi_zip *zip = container_of(qm, struct hisi_zip, qm);
581 	int i;
582 
583 	for (i = HZIP_CURRENT_QM; i < HZIP_DEBUG_FILE_NUM; i++) {
584 		spin_lock_init(&zip->ctrl->files[i].lock);
585 		zip->ctrl->files[i].ctrl = zip->ctrl;
586 		zip->ctrl->files[i].index = i;
587 
588 		debugfs_create_file(ctrl_debug_file_name[i], 0600,
589 				    qm->debug.debug_root,
590 				    zip->ctrl->files + i,
591 				    &ctrl_debug_fops);
592 	}
593 
594 	return hisi_zip_core_debug_init(qm);
595 }
596 
597 static int hisi_zip_debugfs_init(struct hisi_qm *qm)
598 {
599 	struct device *dev = &qm->pdev->dev;
600 	struct dentry *dev_d;
601 	int ret;
602 
603 	dev_d = debugfs_create_dir(dev_name(dev), hzip_debugfs_root);
604 
605 	qm->debug.sqe_mask_offset = HZIP_SQE_MASK_OFFSET;
606 	qm->debug.sqe_mask_len = HZIP_SQE_MASK_LEN;
607 	qm->debug.debug_root = dev_d;
608 	hisi_qm_debug_init(qm);
609 
610 	if (qm->fun_type == QM_HW_PF) {
611 		ret = hisi_zip_ctrl_debug_init(qm);
612 		if (ret)
613 			goto failed_to_create;
614 	}
615 
616 	hisi_zip_dfx_debug_init(qm);
617 
618 	return 0;
619 
620 failed_to_create:
621 	debugfs_remove_recursive(hzip_debugfs_root);
622 	return ret;
623 }
624 
625 /* hisi_zip_debug_regs_clear() - clear the zip debug regs */
626 static void hisi_zip_debug_regs_clear(struct hisi_qm *qm)
627 {
628 	int i, j;
629 
630 	/* clear current_qm */
631 	writel(0x0, qm->io_base + QM_DFX_MB_CNT_VF);
632 	writel(0x0, qm->io_base + QM_DFX_DB_CNT_VF);
633 
634 	/* enable register read_clear bit */
635 	writel(HZIP_RD_CNT_CLR_CE_EN, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE);
636 	for (i = 0; i < ARRAY_SIZE(core_offsets); i++)
637 		for (j = 0; j < ARRAY_SIZE(hzip_dfx_regs); j++)
638 			readl(qm->io_base + core_offsets[i] +
639 			      hzip_dfx_regs[j].offset);
640 
641 	/* disable register read_clear bit */
642 	writel(0x0, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE);
643 
644 	hisi_qm_debug_regs_clear(qm);
645 }
646 
647 static void hisi_zip_debugfs_exit(struct hisi_qm *qm)
648 {
649 	debugfs_remove_recursive(qm->debug.debug_root);
650 
651 	if (qm->fun_type == QM_HW_PF) {
652 		hisi_zip_debug_regs_clear(qm);
653 		qm->debug.curr_qm_qp_num = 0;
654 	}
655 }
656 
657 static void hisi_zip_log_hw_error(struct hisi_qm *qm, u32 err_sts)
658 {
659 	const struct hisi_zip_hw_error *err = zip_hw_error;
660 	struct device *dev = &qm->pdev->dev;
661 	u32 err_val;
662 
663 	while (err->msg) {
664 		if (err->int_msk & err_sts) {
665 			dev_err(dev, "%s [error status=0x%x] found\n",
666 				err->msg, err->int_msk);
667 
668 			if (err->int_msk & HZIP_CORE_INT_STATUS_M_ECC) {
669 				err_val = readl(qm->io_base +
670 						HZIP_CORE_SRAM_ECC_ERR_INFO);
671 				dev_err(dev, "hisi-zip multi ecc sram num=0x%x\n",
672 					((err_val >>
673 					HZIP_SRAM_ECC_ERR_NUM_SHIFT) & 0xFF));
674 			}
675 		}
676 		err++;
677 	}
678 }
679 
680 static u32 hisi_zip_get_hw_err_status(struct hisi_qm *qm)
681 {
682 	return readl(qm->io_base + HZIP_CORE_INT_STATUS);
683 }
684 
685 static void hisi_zip_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts)
686 {
687 	writel(err_sts, qm->io_base + HZIP_CORE_INT_SOURCE);
688 }
689 
690 static void hisi_zip_open_axi_master_ooo(struct hisi_qm *qm)
691 {
692 	u32 val;
693 
694 	val = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);
695 
696 	writel(val & ~HZIP_AXI_SHUTDOWN_ENABLE,
697 	       qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);
698 
699 	writel(val | HZIP_AXI_SHUTDOWN_ENABLE,
700 	       qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);
701 }
702 
703 static void hisi_zip_close_axi_master_ooo(struct hisi_qm *qm)
704 {
705 	u32 nfe_enb;
706 
707 	/* Disable ECC Mbit error report. */
708 	nfe_enb = readl(qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB);
709 	writel(nfe_enb & ~HZIP_CORE_INT_STATUS_M_ECC,
710 	       qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB);
711 
712 	/* Inject zip ECC Mbit error to block master ooo. */
713 	writel(HZIP_CORE_INT_STATUS_M_ECC,
714 	       qm->io_base + HZIP_CORE_INT_SET);
715 }
716 
717 static const struct hisi_qm_err_ini hisi_zip_err_ini = {
718 	.hw_init		= hisi_zip_set_user_domain_and_cache,
719 	.hw_err_enable		= hisi_zip_hw_error_enable,
720 	.hw_err_disable		= hisi_zip_hw_error_disable,
721 	.get_dev_hw_err_status	= hisi_zip_get_hw_err_status,
722 	.clear_dev_hw_err_status = hisi_zip_clear_hw_err_status,
723 	.log_dev_hw_err		= hisi_zip_log_hw_error,
724 	.open_axi_master_ooo	= hisi_zip_open_axi_master_ooo,
725 	.close_axi_master_ooo	= hisi_zip_close_axi_master_ooo,
726 	.err_info		= {
727 		.ce			= QM_BASE_CE,
728 		.nfe			= QM_BASE_NFE |
729 					  QM_ACC_WB_NOT_READY_TIMEOUT,
730 		.fe			= 0,
731 		.ecc_2bits_mask		= HZIP_CORE_INT_STATUS_M_ECC,
732 		.dev_ce_mask		= HZIP_CORE_INT_RAS_CE_ENABLE,
733 		.msi_wr_port		= HZIP_WR_PORT,
734 		.acpi_rst		= "ZRST",
735 	}
736 };
737 
738 static int hisi_zip_pf_probe_init(struct hisi_zip *hisi_zip)
739 {
740 	struct hisi_qm *qm = &hisi_zip->qm;
741 	struct hisi_zip_ctrl *ctrl;
742 
743 	ctrl = devm_kzalloc(&qm->pdev->dev, sizeof(*ctrl), GFP_KERNEL);
744 	if (!ctrl)
745 		return -ENOMEM;
746 
747 	hisi_zip->ctrl = ctrl;
748 	ctrl->hisi_zip = hisi_zip;
749 
750 	if (qm->ver == QM_HW_V1)
751 		qm->ctrl_qp_num = HZIP_QUEUE_NUM_V1;
752 	else
753 		qm->ctrl_qp_num = HZIP_QUEUE_NUM_V2;
754 
755 	qm->err_ini = &hisi_zip_err_ini;
756 
757 	hisi_zip_set_user_domain_and_cache(qm);
758 	hisi_qm_dev_err_init(qm);
759 	hisi_zip_debug_regs_clear(qm);
760 
761 	return 0;
762 }
763 
764 static int hisi_zip_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)
765 {
766 	int ret;
767 
768 	qm->pdev = pdev;
769 	qm->ver = pdev->revision;
770 	qm->algs = "zlib\ngzip";
771 	qm->mode = uacce_mode;
772 	qm->sqe_size = HZIP_SQE_SIZE;
773 	qm->dev_name = hisi_zip_name;
774 
775 	qm->fun_type = (pdev->device == PCI_DEVICE_ID_ZIP_PF) ?
776 			QM_HW_PF : QM_HW_VF;
777 	if (qm->fun_type == QM_HW_PF) {
778 		qm->qp_base = HZIP_PF_DEF_Q_BASE;
779 		qm->qp_num = pf_q_num;
780 		qm->debug.curr_qm_qp_num = pf_q_num;
781 		qm->qm_list = &zip_devices;
782 	} else if (qm->fun_type == QM_HW_VF && qm->ver == QM_HW_V1) {
783 		/*
784 		 * have no way to get qm configure in VM in v1 hardware,
785 		 * so currently force PF to uses HZIP_PF_DEF_Q_NUM, and force
786 		 * to trigger only one VF in v1 hardware.
787 		 *
788 		 * v2 hardware has no such problem.
789 		 */
790 		qm->qp_base = HZIP_PF_DEF_Q_NUM;
791 		qm->qp_num = HZIP_QUEUE_NUM_V1 - HZIP_PF_DEF_Q_NUM;
792 	}
793 
794 	qm->wq = alloc_workqueue("%s", WQ_HIGHPRI | WQ_MEM_RECLAIM |
795 				 WQ_UNBOUND, num_online_cpus(),
796 				 pci_name(qm->pdev));
797 	if (!qm->wq) {
798 		pci_err(qm->pdev, "fail to alloc workqueue\n");
799 		return -ENOMEM;
800 	}
801 
802 	ret = hisi_qm_init(qm);
803 	if (ret)
804 		destroy_workqueue(qm->wq);
805 
806 	return ret;
807 }
808 
809 static void hisi_zip_qm_uninit(struct hisi_qm *qm)
810 {
811 	hisi_qm_uninit(qm);
812 	destroy_workqueue(qm->wq);
813 }
814 
815 static int hisi_zip_probe_init(struct hisi_zip *hisi_zip)
816 {
817 	struct hisi_qm *qm = &hisi_zip->qm;
818 	int ret;
819 
820 	if (qm->fun_type == QM_HW_PF) {
821 		ret = hisi_zip_pf_probe_init(hisi_zip);
822 		if (ret)
823 			return ret;
824 	}
825 
826 	return 0;
827 }
828 
829 static int hisi_zip_probe(struct pci_dev *pdev, const struct pci_device_id *id)
830 {
831 	struct hisi_zip *hisi_zip;
832 	struct hisi_qm *qm;
833 	int ret;
834 
835 	hisi_zip = devm_kzalloc(&pdev->dev, sizeof(*hisi_zip), GFP_KERNEL);
836 	if (!hisi_zip)
837 		return -ENOMEM;
838 
839 	qm = &hisi_zip->qm;
840 
841 	ret = hisi_zip_qm_init(qm, pdev);
842 	if (ret) {
843 		pci_err(pdev, "Failed to init ZIP QM (%d)!\n", ret);
844 		return ret;
845 	}
846 
847 	ret = hisi_zip_probe_init(hisi_zip);
848 	if (ret) {
849 		pci_err(pdev, "Failed to probe (%d)!\n", ret);
850 		goto err_qm_uninit;
851 	}
852 
853 	ret = hisi_qm_start(qm);
854 	if (ret)
855 		goto err_dev_err_uninit;
856 
857 	ret = hisi_zip_debugfs_init(qm);
858 	if (ret)
859 		pci_err(pdev, "failed to init debugfs (%d)!\n", ret);
860 
861 	ret = hisi_qm_alg_register(qm, &zip_devices);
862 	if (ret < 0) {
863 		pci_err(pdev, "failed to register driver to crypto!\n");
864 		goto err_qm_stop;
865 	}
866 
867 	if (qm->uacce) {
868 		ret = uacce_register(qm->uacce);
869 		if (ret) {
870 			pci_err(pdev, "failed to register uacce (%d)!\n", ret);
871 			goto err_qm_alg_unregister;
872 		}
873 	}
874 
875 	if (qm->fun_type == QM_HW_PF && vfs_num > 0) {
876 		ret = hisi_qm_sriov_enable(pdev, vfs_num);
877 		if (ret < 0)
878 			goto err_qm_alg_unregister;
879 	}
880 
881 	return 0;
882 
883 err_qm_alg_unregister:
884 	hisi_qm_alg_unregister(qm, &zip_devices);
885 
886 err_qm_stop:
887 	hisi_zip_debugfs_exit(qm);
888 	hisi_qm_stop(qm, QM_NORMAL);
889 
890 err_dev_err_uninit:
891 	hisi_qm_dev_err_uninit(qm);
892 
893 err_qm_uninit:
894 	hisi_zip_qm_uninit(qm);
895 
896 	return ret;
897 }
898 
899 static void hisi_zip_remove(struct pci_dev *pdev)
900 {
901 	struct hisi_qm *qm = pci_get_drvdata(pdev);
902 
903 	hisi_qm_wait_task_finish(qm, &zip_devices);
904 	hisi_qm_alg_unregister(qm, &zip_devices);
905 
906 	if (qm->fun_type == QM_HW_PF && qm->vfs_num)
907 		hisi_qm_sriov_disable(pdev, true);
908 
909 	hisi_zip_debugfs_exit(qm);
910 	hisi_qm_stop(qm, QM_NORMAL);
911 	hisi_qm_dev_err_uninit(qm);
912 	hisi_zip_qm_uninit(qm);
913 }
914 
915 static const struct pci_error_handlers hisi_zip_err_handler = {
916 	.error_detected	= hisi_qm_dev_err_detected,
917 	.slot_reset	= hisi_qm_dev_slot_reset,
918 	.reset_prepare	= hisi_qm_reset_prepare,
919 	.reset_done	= hisi_qm_reset_done,
920 };
921 
922 static struct pci_driver hisi_zip_pci_driver = {
923 	.name			= "hisi_zip",
924 	.id_table		= hisi_zip_dev_ids,
925 	.probe			= hisi_zip_probe,
926 	.remove			= hisi_zip_remove,
927 	.sriov_configure	= IS_ENABLED(CONFIG_PCI_IOV) ?
928 					hisi_qm_sriov_configure : NULL,
929 	.err_handler		= &hisi_zip_err_handler,
930 	.shutdown		= hisi_qm_dev_shutdown,
931 };
932 
933 static void hisi_zip_register_debugfs(void)
934 {
935 	if (!debugfs_initialized())
936 		return;
937 
938 	hzip_debugfs_root = debugfs_create_dir("hisi_zip", NULL);
939 }
940 
941 static void hisi_zip_unregister_debugfs(void)
942 {
943 	debugfs_remove_recursive(hzip_debugfs_root);
944 }
945 
946 static int __init hisi_zip_init(void)
947 {
948 	int ret;
949 
950 	hisi_qm_init_list(&zip_devices);
951 	hisi_zip_register_debugfs();
952 
953 	ret = pci_register_driver(&hisi_zip_pci_driver);
954 	if (ret < 0) {
955 		hisi_zip_unregister_debugfs();
956 		pr_err("Failed to register pci driver.\n");
957 	}
958 
959 	return ret;
960 }
961 
962 static void __exit hisi_zip_exit(void)
963 {
964 	pci_unregister_driver(&hisi_zip_pci_driver);
965 	hisi_zip_unregister_debugfs();
966 }
967 
968 module_init(hisi_zip_init);
969 module_exit(hisi_zip_exit);
970 
971 MODULE_LICENSE("GPL v2");
972 MODULE_AUTHOR("Zhou Wang <wangzhou1@hisilicon.com>");
973 MODULE_DESCRIPTION("Driver for HiSilicon ZIP accelerator");
974