1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2019 HiSilicon Limited. */ 3 #include <linux/acpi.h> 4 #include <linux/aer.h> 5 #include <linux/bitops.h> 6 #include <linux/debugfs.h> 7 #include <linux/init.h> 8 #include <linux/io.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/seq_file.h> 13 #include <linux/topology.h> 14 #include <linux/uacce.h> 15 #include "zip.h" 16 17 #define PCI_DEVICE_ID_ZIP_PF 0xa250 18 #define PCI_DEVICE_ID_ZIP_VF 0xa251 19 20 #define HZIP_QUEUE_NUM_V1 4096 21 22 #define HZIP_CLOCK_GATE_CTRL 0x301004 23 #define COMP0_ENABLE BIT(0) 24 #define COMP1_ENABLE BIT(1) 25 #define DECOMP0_ENABLE BIT(2) 26 #define DECOMP1_ENABLE BIT(3) 27 #define DECOMP2_ENABLE BIT(4) 28 #define DECOMP3_ENABLE BIT(5) 29 #define DECOMP4_ENABLE BIT(6) 30 #define DECOMP5_ENABLE BIT(7) 31 #define HZIP_ALL_COMP_DECOMP_EN (COMP0_ENABLE | COMP1_ENABLE | \ 32 DECOMP0_ENABLE | DECOMP1_ENABLE | \ 33 DECOMP2_ENABLE | DECOMP3_ENABLE | \ 34 DECOMP4_ENABLE | DECOMP5_ENABLE) 35 #define HZIP_DECOMP_CHECK_ENABLE BIT(16) 36 #define HZIP_FSM_MAX_CNT 0x301008 37 38 #define HZIP_PORT_ARCA_CHE_0 0x301040 39 #define HZIP_PORT_ARCA_CHE_1 0x301044 40 #define HZIP_PORT_AWCA_CHE_0 0x301060 41 #define HZIP_PORT_AWCA_CHE_1 0x301064 42 #define HZIP_CACHE_ALL_EN 0xffffffff 43 44 #define HZIP_BD_RUSER_32_63 0x301110 45 #define HZIP_SGL_RUSER_32_63 0x30111c 46 #define HZIP_DATA_RUSER_32_63 0x301128 47 #define HZIP_DATA_WUSER_32_63 0x301134 48 #define HZIP_BD_WUSER_32_63 0x301140 49 50 #define HZIP_QM_IDEL_STATUS 0x3040e4 51 52 #define HZIP_CORE_DEBUG_COMP_0 0x302000 53 #define HZIP_CORE_DEBUG_COMP_1 0x303000 54 #define HZIP_CORE_DEBUG_DECOMP_0 0x304000 55 #define HZIP_CORE_DEBUG_DECOMP_1 0x305000 56 #define HZIP_CORE_DEBUG_DECOMP_2 0x306000 57 #define HZIP_CORE_DEBUG_DECOMP_3 0x307000 58 #define HZIP_CORE_DEBUG_DECOMP_4 0x308000 59 #define HZIP_CORE_DEBUG_DECOMP_5 0x309000 60 61 #define HZIP_CORE_INT_SOURCE 0x3010A0 62 #define HZIP_CORE_INT_MASK_REG 0x3010A4 63 #define HZIP_CORE_INT_SET 0x3010A8 64 #define HZIP_CORE_INT_STATUS 0x3010AC 65 #define HZIP_CORE_INT_STATUS_M_ECC BIT(1) 66 #define HZIP_CORE_SRAM_ECC_ERR_INFO 0x301148 67 #define HZIP_CORE_INT_RAS_CE_ENB 0x301160 68 #define HZIP_CORE_INT_RAS_CE_ENABLE 0x1 69 #define HZIP_CORE_INT_RAS_NFE_ENB 0x301164 70 #define HZIP_CORE_INT_RAS_FE_ENB 0x301168 71 #define HZIP_CORE_INT_RAS_NFE_ENABLE 0x1FFE 72 #define HZIP_SRAM_ECC_ERR_NUM_SHIFT 16 73 #define HZIP_SRAM_ECC_ERR_ADDR_SHIFT 24 74 #define HZIP_CORE_INT_MASK_ALL GENMASK(12, 0) 75 #define HZIP_COMP_CORE_NUM 2 76 #define HZIP_DECOMP_CORE_NUM 6 77 #define HZIP_CORE_NUM (HZIP_COMP_CORE_NUM + \ 78 HZIP_DECOMP_CORE_NUM) 79 #define HZIP_SQE_SIZE 128 80 #define HZIP_SQ_SIZE (HZIP_SQE_SIZE * QM_Q_DEPTH) 81 #define HZIP_PF_DEF_Q_NUM 64 82 #define HZIP_PF_DEF_Q_BASE 0 83 84 #define HZIP_SOFT_CTRL_CNT_CLR_CE 0x301000 85 #define HZIP_SOFT_CTRL_CNT_CLR_CE_BIT BIT(0) 86 #define HZIP_SOFT_CTRL_ZIP_CONTROL 0x30100C 87 #define HZIP_AXI_SHUTDOWN_ENABLE BIT(14) 88 #define HZIP_WR_PORT BIT(11) 89 90 #define HZIP_BUF_SIZE 22 91 #define HZIP_SQE_MASK_OFFSET 64 92 #define HZIP_SQE_MASK_LEN 48 93 94 #define HZIP_CNT_CLR_CE_EN BIT(0) 95 #define HZIP_RO_CNT_CLR_CE_EN BIT(2) 96 #define HZIP_RD_CNT_CLR_CE_EN (HZIP_CNT_CLR_CE_EN | \ 97 HZIP_RO_CNT_CLR_CE_EN) 98 99 static const char hisi_zip_name[] = "hisi_zip"; 100 static struct dentry *hzip_debugfs_root; 101 102 struct hisi_zip_hw_error { 103 u32 int_msk; 104 const char *msg; 105 }; 106 107 struct zip_dfx_item { 108 const char *name; 109 u32 offset; 110 }; 111 112 static struct hisi_qm_list zip_devices = { 113 .register_to_crypto = hisi_zip_register_to_crypto, 114 .unregister_from_crypto = hisi_zip_unregister_from_crypto, 115 }; 116 117 static struct zip_dfx_item zip_dfx_files[] = { 118 {"send_cnt", offsetof(struct hisi_zip_dfx, send_cnt)}, 119 {"recv_cnt", offsetof(struct hisi_zip_dfx, recv_cnt)}, 120 {"send_busy_cnt", offsetof(struct hisi_zip_dfx, send_busy_cnt)}, 121 {"err_bd_cnt", offsetof(struct hisi_zip_dfx, err_bd_cnt)}, 122 }; 123 124 static const struct hisi_zip_hw_error zip_hw_error[] = { 125 { .int_msk = BIT(0), .msg = "zip_ecc_1bitt_err" }, 126 { .int_msk = BIT(1), .msg = "zip_ecc_2bit_err" }, 127 { .int_msk = BIT(2), .msg = "zip_axi_rresp_err" }, 128 { .int_msk = BIT(3), .msg = "zip_axi_bresp_err" }, 129 { .int_msk = BIT(4), .msg = "zip_src_addr_parse_err" }, 130 { .int_msk = BIT(5), .msg = "zip_dst_addr_parse_err" }, 131 { .int_msk = BIT(6), .msg = "zip_pre_in_addr_err" }, 132 { .int_msk = BIT(7), .msg = "zip_pre_in_data_err" }, 133 { .int_msk = BIT(8), .msg = "zip_com_inf_err" }, 134 { .int_msk = BIT(9), .msg = "zip_enc_inf_err" }, 135 { .int_msk = BIT(10), .msg = "zip_pre_out_err" }, 136 { .int_msk = BIT(11), .msg = "zip_axi_poison_err" }, 137 { .int_msk = BIT(12), .msg = "zip_sva_err" }, 138 { /* sentinel */ } 139 }; 140 141 enum ctrl_debug_file_index { 142 HZIP_CLEAR_ENABLE, 143 HZIP_DEBUG_FILE_NUM, 144 }; 145 146 static const char * const ctrl_debug_file_name[] = { 147 [HZIP_CLEAR_ENABLE] = "clear_enable", 148 }; 149 150 struct ctrl_debug_file { 151 enum ctrl_debug_file_index index; 152 spinlock_t lock; 153 struct hisi_zip_ctrl *ctrl; 154 }; 155 156 /* 157 * One ZIP controller has one PF and multiple VFs, some global configurations 158 * which PF has need this structure. 159 * 160 * Just relevant for PF. 161 */ 162 struct hisi_zip_ctrl { 163 struct hisi_zip *hisi_zip; 164 struct ctrl_debug_file files[HZIP_DEBUG_FILE_NUM]; 165 }; 166 167 enum { 168 HZIP_COMP_CORE0, 169 HZIP_COMP_CORE1, 170 HZIP_DECOMP_CORE0, 171 HZIP_DECOMP_CORE1, 172 HZIP_DECOMP_CORE2, 173 HZIP_DECOMP_CORE3, 174 HZIP_DECOMP_CORE4, 175 HZIP_DECOMP_CORE5, 176 }; 177 178 static const u64 core_offsets[] = { 179 [HZIP_COMP_CORE0] = 0x302000, 180 [HZIP_COMP_CORE1] = 0x303000, 181 [HZIP_DECOMP_CORE0] = 0x304000, 182 [HZIP_DECOMP_CORE1] = 0x305000, 183 [HZIP_DECOMP_CORE2] = 0x306000, 184 [HZIP_DECOMP_CORE3] = 0x307000, 185 [HZIP_DECOMP_CORE4] = 0x308000, 186 [HZIP_DECOMP_CORE5] = 0x309000, 187 }; 188 189 static const struct debugfs_reg32 hzip_dfx_regs[] = { 190 {"HZIP_GET_BD_NUM ", 0x00ull}, 191 {"HZIP_GET_RIGHT_BD ", 0x04ull}, 192 {"HZIP_GET_ERROR_BD ", 0x08ull}, 193 {"HZIP_DONE_BD_NUM ", 0x0cull}, 194 {"HZIP_WORK_CYCLE ", 0x10ull}, 195 {"HZIP_IDLE_CYCLE ", 0x18ull}, 196 {"HZIP_MAX_DELAY ", 0x20ull}, 197 {"HZIP_MIN_DELAY ", 0x24ull}, 198 {"HZIP_AVG_DELAY ", 0x28ull}, 199 {"HZIP_MEM_VISIBLE_DATA ", 0x30ull}, 200 {"HZIP_MEM_VISIBLE_ADDR ", 0x34ull}, 201 {"HZIP_COMSUMED_BYTE ", 0x38ull}, 202 {"HZIP_PRODUCED_BYTE ", 0x40ull}, 203 {"HZIP_COMP_INF ", 0x70ull}, 204 {"HZIP_PRE_OUT ", 0x78ull}, 205 {"HZIP_BD_RD ", 0x7cull}, 206 {"HZIP_BD_WR ", 0x80ull}, 207 {"HZIP_GET_BD_AXI_ERR_NUM ", 0x84ull}, 208 {"HZIP_GET_BD_PARSE_ERR_NUM ", 0x88ull}, 209 {"HZIP_ADD_BD_AXI_ERR_NUM ", 0x8cull}, 210 {"HZIP_DECOMP_STF_RELOAD_CURR_ST ", 0x94ull}, 211 {"HZIP_DECOMP_LZ77_CURR_ST ", 0x9cull}, 212 }; 213 214 static const struct kernel_param_ops zip_uacce_mode_ops = { 215 .set = uacce_mode_set, 216 .get = param_get_int, 217 }; 218 219 /* 220 * uacce_mode = 0 means zip only register to crypto, 221 * uacce_mode = 1 means zip both register to crypto and uacce. 222 */ 223 static u32 uacce_mode = UACCE_MODE_NOUACCE; 224 module_param_cb(uacce_mode, &zip_uacce_mode_ops, &uacce_mode, 0444); 225 MODULE_PARM_DESC(uacce_mode, UACCE_MODE_DESC); 226 227 static int pf_q_num_set(const char *val, const struct kernel_param *kp) 228 { 229 return q_num_set(val, kp, PCI_DEVICE_ID_ZIP_PF); 230 } 231 232 static const struct kernel_param_ops pf_q_num_ops = { 233 .set = pf_q_num_set, 234 .get = param_get_int, 235 }; 236 237 static u32 pf_q_num = HZIP_PF_DEF_Q_NUM; 238 module_param_cb(pf_q_num, &pf_q_num_ops, &pf_q_num, 0444); 239 MODULE_PARM_DESC(pf_q_num, "Number of queues in PF(v1 2-4096, v2 2-1024)"); 240 241 static const struct kernel_param_ops vfs_num_ops = { 242 .set = vfs_num_set, 243 .get = param_get_int, 244 }; 245 246 static u32 vfs_num; 247 module_param_cb(vfs_num, &vfs_num_ops, &vfs_num, 0444); 248 MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)"); 249 250 static const struct pci_device_id hisi_zip_dev_ids[] = { 251 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_ZIP_PF) }, 252 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_ZIP_VF) }, 253 { 0, } 254 }; 255 MODULE_DEVICE_TABLE(pci, hisi_zip_dev_ids); 256 257 int zip_create_qps(struct hisi_qp **qps, int qp_num, int node) 258 { 259 if (node == NUMA_NO_NODE) 260 node = cpu_to_node(smp_processor_id()); 261 262 return hisi_qm_alloc_qps_node(&zip_devices, qp_num, 0, node, qps); 263 } 264 265 static int hisi_zip_set_user_domain_and_cache(struct hisi_qm *qm) 266 { 267 void __iomem *base = qm->io_base; 268 269 /* qm user domain */ 270 writel(AXUSER_BASE, base + QM_ARUSER_M_CFG_1); 271 writel(ARUSER_M_CFG_ENABLE, base + QM_ARUSER_M_CFG_ENABLE); 272 writel(AXUSER_BASE, base + QM_AWUSER_M_CFG_1); 273 writel(AWUSER_M_CFG_ENABLE, base + QM_AWUSER_M_CFG_ENABLE); 274 writel(WUSER_M_CFG_ENABLE, base + QM_WUSER_M_CFG_ENABLE); 275 276 /* qm cache */ 277 writel(AXI_M_CFG, base + QM_AXI_M_CFG); 278 writel(AXI_M_CFG_ENABLE, base + QM_AXI_M_CFG_ENABLE); 279 280 /* disable FLR triggered by BME(bus master enable) */ 281 writel(PEH_AXUSER_CFG, base + QM_PEH_AXUSER_CFG); 282 writel(PEH_AXUSER_CFG_ENABLE, base + QM_PEH_AXUSER_CFG_ENABLE); 283 284 /* cache */ 285 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_ARCA_CHE_0); 286 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_ARCA_CHE_1); 287 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_AWCA_CHE_0); 288 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_AWCA_CHE_1); 289 290 /* user domain configurations */ 291 writel(AXUSER_BASE, base + HZIP_BD_RUSER_32_63); 292 writel(AXUSER_BASE, base + HZIP_SGL_RUSER_32_63); 293 writel(AXUSER_BASE, base + HZIP_BD_WUSER_32_63); 294 295 if (qm->use_sva && qm->ver == QM_HW_V2) { 296 writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_DATA_RUSER_32_63); 297 writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_DATA_WUSER_32_63); 298 } else { 299 writel(AXUSER_BASE, base + HZIP_DATA_RUSER_32_63); 300 writel(AXUSER_BASE, base + HZIP_DATA_WUSER_32_63); 301 } 302 303 /* let's open all compression/decompression cores */ 304 writel(HZIP_DECOMP_CHECK_ENABLE | HZIP_ALL_COMP_DECOMP_EN, 305 base + HZIP_CLOCK_GATE_CTRL); 306 307 /* enable sqc,cqc writeback */ 308 writel(SQC_CACHE_ENABLE | CQC_CACHE_ENABLE | SQC_CACHE_WB_ENABLE | 309 CQC_CACHE_WB_ENABLE | FIELD_PREP(SQC_CACHE_WB_THRD, 1) | 310 FIELD_PREP(CQC_CACHE_WB_THRD, 1), base + QM_CACHE_CTL); 311 312 return 0; 313 } 314 315 static void hisi_zip_hw_error_enable(struct hisi_qm *qm) 316 { 317 u32 val; 318 319 if (qm->ver == QM_HW_V1) { 320 writel(HZIP_CORE_INT_MASK_ALL, 321 qm->io_base + HZIP_CORE_INT_MASK_REG); 322 dev_info(&qm->pdev->dev, "Does not support hw error handle\n"); 323 return; 324 } 325 326 /* clear ZIP hw error source if having */ 327 writel(HZIP_CORE_INT_MASK_ALL, qm->io_base + HZIP_CORE_INT_SOURCE); 328 329 /* configure error type */ 330 writel(HZIP_CORE_INT_RAS_CE_ENABLE, 331 qm->io_base + HZIP_CORE_INT_RAS_CE_ENB); 332 writel(0x0, qm->io_base + HZIP_CORE_INT_RAS_FE_ENB); 333 writel(HZIP_CORE_INT_RAS_NFE_ENABLE, 334 qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 335 336 /* enable ZIP hw error interrupts */ 337 writel(0, qm->io_base + HZIP_CORE_INT_MASK_REG); 338 339 /* enable ZIP block master OOO when m-bit error occur */ 340 val = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 341 val = val | HZIP_AXI_SHUTDOWN_ENABLE; 342 writel(val, qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 343 } 344 345 static void hisi_zip_hw_error_disable(struct hisi_qm *qm) 346 { 347 u32 val; 348 349 /* disable ZIP hw error interrupts */ 350 writel(HZIP_CORE_INT_MASK_ALL, qm->io_base + HZIP_CORE_INT_MASK_REG); 351 352 /* disable ZIP block master OOO when m-bit error occur */ 353 val = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 354 val = val & ~HZIP_AXI_SHUTDOWN_ENABLE; 355 writel(val, qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 356 } 357 358 static inline struct hisi_qm *file_to_qm(struct ctrl_debug_file *file) 359 { 360 struct hisi_zip *hisi_zip = file->ctrl->hisi_zip; 361 362 return &hisi_zip->qm; 363 } 364 365 static u32 clear_enable_read(struct ctrl_debug_file *file) 366 { 367 struct hisi_qm *qm = file_to_qm(file); 368 369 return readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) & 370 HZIP_SOFT_CTRL_CNT_CLR_CE_BIT; 371 } 372 373 static int clear_enable_write(struct ctrl_debug_file *file, u32 val) 374 { 375 struct hisi_qm *qm = file_to_qm(file); 376 u32 tmp; 377 378 if (val != 1 && val != 0) 379 return -EINVAL; 380 381 tmp = (readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) & 382 ~HZIP_SOFT_CTRL_CNT_CLR_CE_BIT) | val; 383 writel(tmp, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE); 384 385 return 0; 386 } 387 388 static ssize_t hisi_zip_ctrl_debug_read(struct file *filp, char __user *buf, 389 size_t count, loff_t *pos) 390 { 391 struct ctrl_debug_file *file = filp->private_data; 392 char tbuf[HZIP_BUF_SIZE]; 393 u32 val; 394 int ret; 395 396 spin_lock_irq(&file->lock); 397 switch (file->index) { 398 case HZIP_CLEAR_ENABLE: 399 val = clear_enable_read(file); 400 break; 401 default: 402 spin_unlock_irq(&file->lock); 403 return -EINVAL; 404 } 405 spin_unlock_irq(&file->lock); 406 ret = scnprintf(tbuf, sizeof(tbuf), "%u\n", val); 407 return simple_read_from_buffer(buf, count, pos, tbuf, ret); 408 } 409 410 static ssize_t hisi_zip_ctrl_debug_write(struct file *filp, 411 const char __user *buf, 412 size_t count, loff_t *pos) 413 { 414 struct ctrl_debug_file *file = filp->private_data; 415 char tbuf[HZIP_BUF_SIZE]; 416 unsigned long val; 417 int len, ret; 418 419 if (*pos != 0) 420 return 0; 421 422 if (count >= HZIP_BUF_SIZE) 423 return -ENOSPC; 424 425 len = simple_write_to_buffer(tbuf, HZIP_BUF_SIZE - 1, pos, buf, count); 426 if (len < 0) 427 return len; 428 429 tbuf[len] = '\0'; 430 if (kstrtoul(tbuf, 0, &val)) 431 return -EFAULT; 432 433 spin_lock_irq(&file->lock); 434 switch (file->index) { 435 case HZIP_CLEAR_ENABLE: 436 ret = clear_enable_write(file, val); 437 if (ret) 438 goto err_input; 439 break; 440 default: 441 ret = -EINVAL; 442 goto err_input; 443 } 444 spin_unlock_irq(&file->lock); 445 446 return count; 447 448 err_input: 449 spin_unlock_irq(&file->lock); 450 return ret; 451 } 452 453 static const struct file_operations ctrl_debug_fops = { 454 .owner = THIS_MODULE, 455 .open = simple_open, 456 .read = hisi_zip_ctrl_debug_read, 457 .write = hisi_zip_ctrl_debug_write, 458 }; 459 460 static int zip_debugfs_atomic64_set(void *data, u64 val) 461 { 462 if (val) 463 return -EINVAL; 464 465 atomic64_set((atomic64_t *)data, 0); 466 467 return 0; 468 } 469 470 static int zip_debugfs_atomic64_get(void *data, u64 *val) 471 { 472 *val = atomic64_read((atomic64_t *)data); 473 474 return 0; 475 } 476 477 DEFINE_DEBUGFS_ATTRIBUTE(zip_atomic64_ops, zip_debugfs_atomic64_get, 478 zip_debugfs_atomic64_set, "%llu\n"); 479 480 static int hisi_zip_core_debug_init(struct hisi_qm *qm) 481 { 482 struct device *dev = &qm->pdev->dev; 483 struct debugfs_regset32 *regset; 484 struct dentry *tmp_d; 485 char buf[HZIP_BUF_SIZE]; 486 int i; 487 488 for (i = 0; i < HZIP_CORE_NUM; i++) { 489 if (i < HZIP_COMP_CORE_NUM) 490 scnprintf(buf, sizeof(buf), "comp_core%d", i); 491 else 492 scnprintf(buf, sizeof(buf), "decomp_core%d", 493 i - HZIP_COMP_CORE_NUM); 494 495 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 496 if (!regset) 497 return -ENOENT; 498 499 regset->regs = hzip_dfx_regs; 500 regset->nregs = ARRAY_SIZE(hzip_dfx_regs); 501 regset->base = qm->io_base + core_offsets[i]; 502 503 tmp_d = debugfs_create_dir(buf, qm->debug.debug_root); 504 debugfs_create_regset32("regs", 0444, tmp_d, regset); 505 } 506 507 return 0; 508 } 509 510 static void hisi_zip_dfx_debug_init(struct hisi_qm *qm) 511 { 512 struct hisi_zip *zip = container_of(qm, struct hisi_zip, qm); 513 struct hisi_zip_dfx *dfx = &zip->dfx; 514 struct dentry *tmp_dir; 515 void *data; 516 int i; 517 518 tmp_dir = debugfs_create_dir("zip_dfx", qm->debug.debug_root); 519 for (i = 0; i < ARRAY_SIZE(zip_dfx_files); i++) { 520 data = (atomic64_t *)((uintptr_t)dfx + zip_dfx_files[i].offset); 521 debugfs_create_file(zip_dfx_files[i].name, 522 0644, tmp_dir, data, 523 &zip_atomic64_ops); 524 } 525 } 526 527 static int hisi_zip_ctrl_debug_init(struct hisi_qm *qm) 528 { 529 struct hisi_zip *zip = container_of(qm, struct hisi_zip, qm); 530 int i; 531 532 for (i = HZIP_CLEAR_ENABLE; i < HZIP_DEBUG_FILE_NUM; i++) { 533 spin_lock_init(&zip->ctrl->files[i].lock); 534 zip->ctrl->files[i].ctrl = zip->ctrl; 535 zip->ctrl->files[i].index = i; 536 537 debugfs_create_file(ctrl_debug_file_name[i], 0600, 538 qm->debug.debug_root, 539 zip->ctrl->files + i, 540 &ctrl_debug_fops); 541 } 542 543 return hisi_zip_core_debug_init(qm); 544 } 545 546 static int hisi_zip_debugfs_init(struct hisi_qm *qm) 547 { 548 struct device *dev = &qm->pdev->dev; 549 struct dentry *dev_d; 550 int ret; 551 552 dev_d = debugfs_create_dir(dev_name(dev), hzip_debugfs_root); 553 554 qm->debug.sqe_mask_offset = HZIP_SQE_MASK_OFFSET; 555 qm->debug.sqe_mask_len = HZIP_SQE_MASK_LEN; 556 qm->debug.debug_root = dev_d; 557 hisi_qm_debug_init(qm); 558 559 if (qm->fun_type == QM_HW_PF) { 560 ret = hisi_zip_ctrl_debug_init(qm); 561 if (ret) 562 goto failed_to_create; 563 } 564 565 hisi_zip_dfx_debug_init(qm); 566 567 return 0; 568 569 failed_to_create: 570 debugfs_remove_recursive(hzip_debugfs_root); 571 return ret; 572 } 573 574 /* hisi_zip_debug_regs_clear() - clear the zip debug regs */ 575 static void hisi_zip_debug_regs_clear(struct hisi_qm *qm) 576 { 577 int i, j; 578 579 /* enable register read_clear bit */ 580 writel(HZIP_RD_CNT_CLR_CE_EN, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE); 581 for (i = 0; i < ARRAY_SIZE(core_offsets); i++) 582 for (j = 0; j < ARRAY_SIZE(hzip_dfx_regs); j++) 583 readl(qm->io_base + core_offsets[i] + 584 hzip_dfx_regs[j].offset); 585 586 /* disable register read_clear bit */ 587 writel(0x0, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE); 588 589 hisi_qm_debug_regs_clear(qm); 590 } 591 592 static void hisi_zip_debugfs_exit(struct hisi_qm *qm) 593 { 594 debugfs_remove_recursive(qm->debug.debug_root); 595 596 if (qm->fun_type == QM_HW_PF) { 597 hisi_zip_debug_regs_clear(qm); 598 qm->debug.curr_qm_qp_num = 0; 599 } 600 } 601 602 static void hisi_zip_log_hw_error(struct hisi_qm *qm, u32 err_sts) 603 { 604 const struct hisi_zip_hw_error *err = zip_hw_error; 605 struct device *dev = &qm->pdev->dev; 606 u32 err_val; 607 608 while (err->msg) { 609 if (err->int_msk & err_sts) { 610 dev_err(dev, "%s [error status=0x%x] found\n", 611 err->msg, err->int_msk); 612 613 if (err->int_msk & HZIP_CORE_INT_STATUS_M_ECC) { 614 err_val = readl(qm->io_base + 615 HZIP_CORE_SRAM_ECC_ERR_INFO); 616 dev_err(dev, "hisi-zip multi ecc sram num=0x%x\n", 617 ((err_val >> 618 HZIP_SRAM_ECC_ERR_NUM_SHIFT) & 0xFF)); 619 } 620 } 621 err++; 622 } 623 } 624 625 static u32 hisi_zip_get_hw_err_status(struct hisi_qm *qm) 626 { 627 return readl(qm->io_base + HZIP_CORE_INT_STATUS); 628 } 629 630 static void hisi_zip_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts) 631 { 632 writel(err_sts, qm->io_base + HZIP_CORE_INT_SOURCE); 633 } 634 635 static void hisi_zip_open_axi_master_ooo(struct hisi_qm *qm) 636 { 637 u32 val; 638 639 val = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 640 641 writel(val & ~HZIP_AXI_SHUTDOWN_ENABLE, 642 qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 643 644 writel(val | HZIP_AXI_SHUTDOWN_ENABLE, 645 qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 646 } 647 648 static void hisi_zip_close_axi_master_ooo(struct hisi_qm *qm) 649 { 650 u32 nfe_enb; 651 652 /* Disable ECC Mbit error report. */ 653 nfe_enb = readl(qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 654 writel(nfe_enb & ~HZIP_CORE_INT_STATUS_M_ECC, 655 qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 656 657 /* Inject zip ECC Mbit error to block master ooo. */ 658 writel(HZIP_CORE_INT_STATUS_M_ECC, 659 qm->io_base + HZIP_CORE_INT_SET); 660 } 661 662 static void hisi_zip_err_info_init(struct hisi_qm *qm) 663 { 664 struct hisi_qm_err_info *err_info = &qm->err_info; 665 666 err_info->ce = QM_BASE_CE; 667 err_info->fe = 0; 668 err_info->ecc_2bits_mask = HZIP_CORE_INT_STATUS_M_ECC; 669 err_info->dev_ce_mask = HZIP_CORE_INT_RAS_CE_ENABLE; 670 err_info->msi_wr_port = HZIP_WR_PORT; 671 err_info->acpi_rst = "ZRST"; 672 err_info->nfe = QM_BASE_NFE | QM_ACC_WB_NOT_READY_TIMEOUT; 673 674 if (qm->ver >= QM_HW_V3) 675 err_info->nfe |= QM_ACC_DO_TASK_TIMEOUT; 676 } 677 678 static const struct hisi_qm_err_ini hisi_zip_err_ini = { 679 .hw_init = hisi_zip_set_user_domain_and_cache, 680 .hw_err_enable = hisi_zip_hw_error_enable, 681 .hw_err_disable = hisi_zip_hw_error_disable, 682 .get_dev_hw_err_status = hisi_zip_get_hw_err_status, 683 .clear_dev_hw_err_status = hisi_zip_clear_hw_err_status, 684 .log_dev_hw_err = hisi_zip_log_hw_error, 685 .open_axi_master_ooo = hisi_zip_open_axi_master_ooo, 686 .close_axi_master_ooo = hisi_zip_close_axi_master_ooo, 687 .err_info_init = hisi_zip_err_info_init, 688 }; 689 690 static int hisi_zip_pf_probe_init(struct hisi_zip *hisi_zip) 691 { 692 struct hisi_qm *qm = &hisi_zip->qm; 693 struct hisi_zip_ctrl *ctrl; 694 695 ctrl = devm_kzalloc(&qm->pdev->dev, sizeof(*ctrl), GFP_KERNEL); 696 if (!ctrl) 697 return -ENOMEM; 698 699 hisi_zip->ctrl = ctrl; 700 ctrl->hisi_zip = hisi_zip; 701 qm->err_ini = &hisi_zip_err_ini; 702 qm->err_ini->err_info_init(qm); 703 704 hisi_zip_set_user_domain_and_cache(qm); 705 hisi_qm_dev_err_init(qm); 706 hisi_zip_debug_regs_clear(qm); 707 708 return 0; 709 } 710 711 static int hisi_zip_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) 712 { 713 int ret; 714 715 qm->pdev = pdev; 716 qm->ver = pdev->revision; 717 qm->algs = "zlib\ngzip"; 718 qm->mode = uacce_mode; 719 qm->sqe_size = HZIP_SQE_SIZE; 720 qm->dev_name = hisi_zip_name; 721 722 qm->fun_type = (pdev->device == PCI_DEVICE_ID_ZIP_PF) ? 723 QM_HW_PF : QM_HW_VF; 724 if (qm->fun_type == QM_HW_PF) { 725 qm->qp_base = HZIP_PF_DEF_Q_BASE; 726 qm->qp_num = pf_q_num; 727 qm->debug.curr_qm_qp_num = pf_q_num; 728 qm->qm_list = &zip_devices; 729 } else if (qm->fun_type == QM_HW_VF && qm->ver == QM_HW_V1) { 730 /* 731 * have no way to get qm configure in VM in v1 hardware, 732 * so currently force PF to uses HZIP_PF_DEF_Q_NUM, and force 733 * to trigger only one VF in v1 hardware. 734 * 735 * v2 hardware has no such problem. 736 */ 737 qm->qp_base = HZIP_PF_DEF_Q_NUM; 738 qm->qp_num = HZIP_QUEUE_NUM_V1 - HZIP_PF_DEF_Q_NUM; 739 } 740 741 qm->wq = alloc_workqueue("%s", WQ_HIGHPRI | WQ_MEM_RECLAIM | 742 WQ_UNBOUND, num_online_cpus(), 743 pci_name(qm->pdev)); 744 if (!qm->wq) { 745 pci_err(qm->pdev, "fail to alloc workqueue\n"); 746 return -ENOMEM; 747 } 748 749 ret = hisi_qm_init(qm); 750 if (ret) 751 destroy_workqueue(qm->wq); 752 753 return ret; 754 } 755 756 static void hisi_zip_qm_uninit(struct hisi_qm *qm) 757 { 758 hisi_qm_uninit(qm); 759 destroy_workqueue(qm->wq); 760 } 761 762 static int hisi_zip_probe_init(struct hisi_zip *hisi_zip) 763 { 764 struct hisi_qm *qm = &hisi_zip->qm; 765 int ret; 766 767 if (qm->fun_type == QM_HW_PF) { 768 ret = hisi_zip_pf_probe_init(hisi_zip); 769 if (ret) 770 return ret; 771 } 772 773 return 0; 774 } 775 776 static int hisi_zip_probe(struct pci_dev *pdev, const struct pci_device_id *id) 777 { 778 struct hisi_zip *hisi_zip; 779 struct hisi_qm *qm; 780 int ret; 781 782 hisi_zip = devm_kzalloc(&pdev->dev, sizeof(*hisi_zip), GFP_KERNEL); 783 if (!hisi_zip) 784 return -ENOMEM; 785 786 qm = &hisi_zip->qm; 787 788 ret = hisi_zip_qm_init(qm, pdev); 789 if (ret) { 790 pci_err(pdev, "Failed to init ZIP QM (%d)!\n", ret); 791 return ret; 792 } 793 794 ret = hisi_zip_probe_init(hisi_zip); 795 if (ret) { 796 pci_err(pdev, "Failed to probe (%d)!\n", ret); 797 goto err_qm_uninit; 798 } 799 800 ret = hisi_qm_start(qm); 801 if (ret) 802 goto err_dev_err_uninit; 803 804 ret = hisi_zip_debugfs_init(qm); 805 if (ret) 806 pci_err(pdev, "failed to init debugfs (%d)!\n", ret); 807 808 ret = hisi_qm_alg_register(qm, &zip_devices); 809 if (ret < 0) { 810 pci_err(pdev, "failed to register driver to crypto!\n"); 811 goto err_qm_stop; 812 } 813 814 if (qm->uacce) { 815 ret = uacce_register(qm->uacce); 816 if (ret) { 817 pci_err(pdev, "failed to register uacce (%d)!\n", ret); 818 goto err_qm_alg_unregister; 819 } 820 } 821 822 if (qm->fun_type == QM_HW_PF && vfs_num > 0) { 823 ret = hisi_qm_sriov_enable(pdev, vfs_num); 824 if (ret < 0) 825 goto err_qm_alg_unregister; 826 } 827 828 return 0; 829 830 err_qm_alg_unregister: 831 hisi_qm_alg_unregister(qm, &zip_devices); 832 833 err_qm_stop: 834 hisi_zip_debugfs_exit(qm); 835 hisi_qm_stop(qm, QM_NORMAL); 836 837 err_dev_err_uninit: 838 hisi_qm_dev_err_uninit(qm); 839 840 err_qm_uninit: 841 hisi_zip_qm_uninit(qm); 842 843 return ret; 844 } 845 846 static void hisi_zip_remove(struct pci_dev *pdev) 847 { 848 struct hisi_qm *qm = pci_get_drvdata(pdev); 849 850 hisi_qm_wait_task_finish(qm, &zip_devices); 851 hisi_qm_alg_unregister(qm, &zip_devices); 852 853 if (qm->fun_type == QM_HW_PF && qm->vfs_num) 854 hisi_qm_sriov_disable(pdev, true); 855 856 hisi_zip_debugfs_exit(qm); 857 hisi_qm_stop(qm, QM_NORMAL); 858 hisi_qm_dev_err_uninit(qm); 859 hisi_zip_qm_uninit(qm); 860 } 861 862 static const struct pci_error_handlers hisi_zip_err_handler = { 863 .error_detected = hisi_qm_dev_err_detected, 864 .slot_reset = hisi_qm_dev_slot_reset, 865 .reset_prepare = hisi_qm_reset_prepare, 866 .reset_done = hisi_qm_reset_done, 867 }; 868 869 static struct pci_driver hisi_zip_pci_driver = { 870 .name = "hisi_zip", 871 .id_table = hisi_zip_dev_ids, 872 .probe = hisi_zip_probe, 873 .remove = hisi_zip_remove, 874 .sriov_configure = IS_ENABLED(CONFIG_PCI_IOV) ? 875 hisi_qm_sriov_configure : NULL, 876 .err_handler = &hisi_zip_err_handler, 877 .shutdown = hisi_qm_dev_shutdown, 878 }; 879 880 static void hisi_zip_register_debugfs(void) 881 { 882 if (!debugfs_initialized()) 883 return; 884 885 hzip_debugfs_root = debugfs_create_dir("hisi_zip", NULL); 886 } 887 888 static void hisi_zip_unregister_debugfs(void) 889 { 890 debugfs_remove_recursive(hzip_debugfs_root); 891 } 892 893 static int __init hisi_zip_init(void) 894 { 895 int ret; 896 897 hisi_qm_init_list(&zip_devices); 898 hisi_zip_register_debugfs(); 899 900 ret = pci_register_driver(&hisi_zip_pci_driver); 901 if (ret < 0) { 902 hisi_zip_unregister_debugfs(); 903 pr_err("Failed to register pci driver.\n"); 904 } 905 906 return ret; 907 } 908 909 static void __exit hisi_zip_exit(void) 910 { 911 pci_unregister_driver(&hisi_zip_pci_driver); 912 hisi_zip_unregister_debugfs(); 913 } 914 915 module_init(hisi_zip_init); 916 module_exit(hisi_zip_exit); 917 918 MODULE_LICENSE("GPL v2"); 919 MODULE_AUTHOR("Zhou Wang <wangzhou1@hisilicon.com>"); 920 MODULE_DESCRIPTION("Driver for HiSilicon ZIP accelerator"); 921