1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2019 HiSilicon Limited. */ 3 4 #include <linux/acpi.h> 5 #include <linux/aer.h> 6 #include <linux/bitops.h> 7 #include <linux/debugfs.h> 8 #include <linux/init.h> 9 #include <linux/io.h> 10 #include <linux/iommu.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/pci.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/seq_file.h> 16 #include <linux/topology.h> 17 #include <linux/uacce.h> 18 19 #include "sec.h" 20 21 #define SEC_VF_NUM 63 22 #define SEC_QUEUE_NUM_V1 4096 23 #define SEC_PF_PCI_DEVICE_ID 0xa255 24 #define SEC_VF_PCI_DEVICE_ID 0xa256 25 26 #define SEC_BD_ERR_CHK_EN0 0xEFFFFFFF 27 #define SEC_BD_ERR_CHK_EN1 0x7ffff7fd 28 #define SEC_BD_ERR_CHK_EN3 0xffffbfff 29 30 #define SEC_SQE_SIZE 128 31 #define SEC_SQ_SIZE (SEC_SQE_SIZE * QM_Q_DEPTH) 32 #define SEC_PF_DEF_Q_NUM 256 33 #define SEC_PF_DEF_Q_BASE 0 34 #define SEC_CTX_Q_NUM_DEF 2 35 #define SEC_CTX_Q_NUM_MAX 32 36 37 #define SEC_CTRL_CNT_CLR_CE 0x301120 38 #define SEC_CTRL_CNT_CLR_CE_BIT BIT(0) 39 #define SEC_CORE_INT_SOURCE 0x301010 40 #define SEC_CORE_INT_MASK 0x301000 41 #define SEC_CORE_INT_STATUS 0x301008 42 #define SEC_CORE_SRAM_ECC_ERR_INFO 0x301C14 43 #define SEC_ECC_NUM 16 44 #define SEC_ECC_MASH 0xFF 45 #define SEC_CORE_INT_DISABLE 0x0 46 #define SEC_CORE_INT_ENABLE 0x7c1ff 47 #define SEC_CORE_INT_CLEAR 0x7c1ff 48 #define SEC_SAA_ENABLE 0x17f 49 50 #define SEC_RAS_CE_REG 0x301050 51 #define SEC_RAS_FE_REG 0x301054 52 #define SEC_RAS_NFE_REG 0x301058 53 #define SEC_RAS_CE_ENB_MSK 0x88 54 #define SEC_RAS_FE_ENB_MSK 0x0 55 #define SEC_RAS_NFE_ENB_MSK 0x7c177 56 #define SEC_OOO_SHUTDOWN_SEL 0x301014 57 #define SEC_RAS_DISABLE 0x0 58 #define SEC_MEM_START_INIT_REG 0x301100 59 #define SEC_MEM_INIT_DONE_REG 0x301104 60 61 /* clock gating */ 62 #define SEC_CONTROL_REG 0x301200 63 #define SEC_DYNAMIC_GATE_REG 0x30121c 64 #define SEC_CORE_AUTO_GATE 0x30212c 65 #define SEC_DYNAMIC_GATE_EN 0x7bff 66 #define SEC_CORE_AUTO_GATE_EN GENMASK(3, 0) 67 #define SEC_CLK_GATE_ENABLE BIT(3) 68 #define SEC_CLK_GATE_DISABLE (~BIT(3)) 69 70 #define SEC_TRNG_EN_SHIFT 8 71 #define SEC_AXI_SHUTDOWN_ENABLE BIT(12) 72 #define SEC_AXI_SHUTDOWN_DISABLE 0xFFFFEFFF 73 74 #define SEC_INTERFACE_USER_CTRL0_REG 0x301220 75 #define SEC_INTERFACE_USER_CTRL1_REG 0x301224 76 #define SEC_SAA_EN_REG 0x301270 77 #define SEC_BD_ERR_CHK_EN_REG0 0x301380 78 #define SEC_BD_ERR_CHK_EN_REG1 0x301384 79 #define SEC_BD_ERR_CHK_EN_REG3 0x30138c 80 81 #define SEC_USER0_SMMU_NORMAL (BIT(23) | BIT(15)) 82 #define SEC_USER1_SMMU_NORMAL (BIT(31) | BIT(23) | BIT(15) | BIT(7)) 83 #define SEC_USER1_ENABLE_CONTEXT_SSV BIT(24) 84 #define SEC_USER1_ENABLE_DATA_SSV BIT(16) 85 #define SEC_USER1_WB_CONTEXT_SSV BIT(8) 86 #define SEC_USER1_WB_DATA_SSV BIT(0) 87 #define SEC_USER1_SVA_SET (SEC_USER1_ENABLE_CONTEXT_SSV | \ 88 SEC_USER1_ENABLE_DATA_SSV | \ 89 SEC_USER1_WB_CONTEXT_SSV | \ 90 SEC_USER1_WB_DATA_SSV) 91 #define SEC_USER1_SMMU_SVA (SEC_USER1_SMMU_NORMAL | SEC_USER1_SVA_SET) 92 #define SEC_USER1_SMMU_MASK (~SEC_USER1_SVA_SET) 93 #define SEC_INTERFACE_USER_CTRL0_REG_V3 0x302220 94 #define SEC_INTERFACE_USER_CTRL1_REG_V3 0x302224 95 #define SEC_USER1_SMMU_NORMAL_V3 (BIT(23) | BIT(17) | BIT(11) | BIT(5)) 96 #define SEC_USER1_SMMU_MASK_V3 0xFF79E79E 97 #define SEC_CORE_INT_STATUS_M_ECC BIT(2) 98 99 #define SEC_PREFETCH_CFG 0x301130 100 #define SEC_SVA_TRANS 0x301EC4 101 #define SEC_PREFETCH_ENABLE (~(BIT(0) | BIT(1) | BIT(11))) 102 #define SEC_PREFETCH_DISABLE BIT(1) 103 #define SEC_SVA_DISABLE_READY (BIT(7) | BIT(11)) 104 105 #define SEC_DELAY_10_US 10 106 #define SEC_POLL_TIMEOUT_US 1000 107 #define SEC_DBGFS_VAL_MAX_LEN 20 108 #define SEC_SINGLE_PORT_MAX_TRANS 0x2060 109 110 #define SEC_SQE_MASK_OFFSET 64 111 #define SEC_SQE_MASK_LEN 48 112 #define SEC_SHAPER_TYPE_RATE 400 113 114 struct sec_hw_error { 115 u32 int_msk; 116 const char *msg; 117 }; 118 119 struct sec_dfx_item { 120 const char *name; 121 u32 offset; 122 }; 123 124 static const char sec_name[] = "hisi_sec2"; 125 static struct dentry *sec_debugfs_root; 126 127 static struct hisi_qm_list sec_devices = { 128 .register_to_crypto = sec_register_to_crypto, 129 .unregister_from_crypto = sec_unregister_from_crypto, 130 }; 131 132 static const struct sec_hw_error sec_hw_errors[] = { 133 { 134 .int_msk = BIT(0), 135 .msg = "sec_axi_rresp_err_rint" 136 }, 137 { 138 .int_msk = BIT(1), 139 .msg = "sec_axi_bresp_err_rint" 140 }, 141 { 142 .int_msk = BIT(2), 143 .msg = "sec_ecc_2bit_err_rint" 144 }, 145 { 146 .int_msk = BIT(3), 147 .msg = "sec_ecc_1bit_err_rint" 148 }, 149 { 150 .int_msk = BIT(4), 151 .msg = "sec_req_trng_timeout_rint" 152 }, 153 { 154 .int_msk = BIT(5), 155 .msg = "sec_fsm_hbeat_rint" 156 }, 157 { 158 .int_msk = BIT(6), 159 .msg = "sec_channel_req_rng_timeout_rint" 160 }, 161 { 162 .int_msk = BIT(7), 163 .msg = "sec_bd_err_rint" 164 }, 165 { 166 .int_msk = BIT(8), 167 .msg = "sec_chain_buff_err_rint" 168 }, 169 { 170 .int_msk = BIT(14), 171 .msg = "sec_no_secure_access" 172 }, 173 { 174 .int_msk = BIT(15), 175 .msg = "sec_wrapping_key_auth_err" 176 }, 177 { 178 .int_msk = BIT(16), 179 .msg = "sec_km_key_crc_fail" 180 }, 181 { 182 .int_msk = BIT(17), 183 .msg = "sec_axi_poison_err" 184 }, 185 { 186 .int_msk = BIT(18), 187 .msg = "sec_sva_err" 188 }, 189 {} 190 }; 191 192 static const char * const sec_dbg_file_name[] = { 193 [SEC_CLEAR_ENABLE] = "clear_enable", 194 }; 195 196 static struct sec_dfx_item sec_dfx_labels[] = { 197 {"send_cnt", offsetof(struct sec_dfx, send_cnt)}, 198 {"recv_cnt", offsetof(struct sec_dfx, recv_cnt)}, 199 {"send_busy_cnt", offsetof(struct sec_dfx, send_busy_cnt)}, 200 {"recv_busy_cnt", offsetof(struct sec_dfx, recv_busy_cnt)}, 201 {"err_bd_cnt", offsetof(struct sec_dfx, err_bd_cnt)}, 202 {"invalid_req_cnt", offsetof(struct sec_dfx, invalid_req_cnt)}, 203 {"done_flag_cnt", offsetof(struct sec_dfx, done_flag_cnt)}, 204 }; 205 206 static const struct debugfs_reg32 sec_dfx_regs[] = { 207 {"SEC_PF_ABNORMAL_INT_SOURCE ", 0x301010}, 208 {"SEC_SAA_EN ", 0x301270}, 209 {"SEC_BD_LATENCY_MIN ", 0x301600}, 210 {"SEC_BD_LATENCY_MAX ", 0x301608}, 211 {"SEC_BD_LATENCY_AVG ", 0x30160C}, 212 {"SEC_BD_NUM_IN_SAA0 ", 0x301670}, 213 {"SEC_BD_NUM_IN_SAA1 ", 0x301674}, 214 {"SEC_BD_NUM_IN_SEC ", 0x301680}, 215 {"SEC_ECC_1BIT_CNT ", 0x301C00}, 216 {"SEC_ECC_1BIT_INFO ", 0x301C04}, 217 {"SEC_ECC_2BIT_CNT ", 0x301C10}, 218 {"SEC_ECC_2BIT_INFO ", 0x301C14}, 219 {"SEC_BD_SAA0 ", 0x301C20}, 220 {"SEC_BD_SAA1 ", 0x301C24}, 221 {"SEC_BD_SAA2 ", 0x301C28}, 222 {"SEC_BD_SAA3 ", 0x301C2C}, 223 {"SEC_BD_SAA4 ", 0x301C30}, 224 {"SEC_BD_SAA5 ", 0x301C34}, 225 {"SEC_BD_SAA6 ", 0x301C38}, 226 {"SEC_BD_SAA7 ", 0x301C3C}, 227 {"SEC_BD_SAA8 ", 0x301C40}, 228 }; 229 230 static int sec_pf_q_num_set(const char *val, const struct kernel_param *kp) 231 { 232 return q_num_set(val, kp, SEC_PF_PCI_DEVICE_ID); 233 } 234 235 static const struct kernel_param_ops sec_pf_q_num_ops = { 236 .set = sec_pf_q_num_set, 237 .get = param_get_int, 238 }; 239 240 static u32 pf_q_num = SEC_PF_DEF_Q_NUM; 241 module_param_cb(pf_q_num, &sec_pf_q_num_ops, &pf_q_num, 0444); 242 MODULE_PARM_DESC(pf_q_num, "Number of queues in PF(v1 2-4096, v2 2-1024)"); 243 244 static int sec_ctx_q_num_set(const char *val, const struct kernel_param *kp) 245 { 246 u32 ctx_q_num; 247 int ret; 248 249 if (!val) 250 return -EINVAL; 251 252 ret = kstrtou32(val, 10, &ctx_q_num); 253 if (ret) 254 return -EINVAL; 255 256 if (!ctx_q_num || ctx_q_num > SEC_CTX_Q_NUM_MAX || ctx_q_num & 0x1) { 257 pr_err("ctx queue num[%u] is invalid!\n", ctx_q_num); 258 return -EINVAL; 259 } 260 261 return param_set_int(val, kp); 262 } 263 264 static const struct kernel_param_ops sec_ctx_q_num_ops = { 265 .set = sec_ctx_q_num_set, 266 .get = param_get_int, 267 }; 268 static u32 ctx_q_num = SEC_CTX_Q_NUM_DEF; 269 module_param_cb(ctx_q_num, &sec_ctx_q_num_ops, &ctx_q_num, 0444); 270 MODULE_PARM_DESC(ctx_q_num, "Queue num in ctx (2 default, 2, 4, ..., 32)"); 271 272 static const struct kernel_param_ops vfs_num_ops = { 273 .set = vfs_num_set, 274 .get = param_get_int, 275 }; 276 277 static u32 vfs_num; 278 module_param_cb(vfs_num, &vfs_num_ops, &vfs_num, 0444); 279 MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)"); 280 281 void sec_destroy_qps(struct hisi_qp **qps, int qp_num) 282 { 283 hisi_qm_free_qps(qps, qp_num); 284 kfree(qps); 285 } 286 287 struct hisi_qp **sec_create_qps(void) 288 { 289 int node = cpu_to_node(smp_processor_id()); 290 u32 ctx_num = ctx_q_num; 291 struct hisi_qp **qps; 292 int ret; 293 294 qps = kcalloc(ctx_num, sizeof(struct hisi_qp *), GFP_KERNEL); 295 if (!qps) 296 return NULL; 297 298 ret = hisi_qm_alloc_qps_node(&sec_devices, ctx_num, 0, node, qps); 299 if (!ret) 300 return qps; 301 302 kfree(qps); 303 return NULL; 304 } 305 306 static const struct kernel_param_ops sec_uacce_mode_ops = { 307 .set = uacce_mode_set, 308 .get = param_get_int, 309 }; 310 311 /* 312 * uacce_mode = 0 means sec only register to crypto, 313 * uacce_mode = 1 means sec both register to crypto and uacce. 314 */ 315 static u32 uacce_mode = UACCE_MODE_NOUACCE; 316 module_param_cb(uacce_mode, &sec_uacce_mode_ops, &uacce_mode, 0444); 317 MODULE_PARM_DESC(uacce_mode, UACCE_MODE_DESC); 318 319 static const struct pci_device_id sec_dev_ids[] = { 320 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, SEC_PF_PCI_DEVICE_ID) }, 321 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, SEC_VF_PCI_DEVICE_ID) }, 322 { 0, } 323 }; 324 MODULE_DEVICE_TABLE(pci, sec_dev_ids); 325 326 static void sec_set_endian(struct hisi_qm *qm) 327 { 328 u32 reg; 329 330 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG); 331 reg &= ~(BIT(1) | BIT(0)); 332 if (!IS_ENABLED(CONFIG_64BIT)) 333 reg |= BIT(1); 334 335 336 if (!IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN)) 337 reg |= BIT(0); 338 339 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG); 340 } 341 342 static void sec_engine_sva_config(struct hisi_qm *qm) 343 { 344 u32 reg; 345 346 if (qm->ver > QM_HW_V2) { 347 reg = readl_relaxed(qm->io_base + 348 SEC_INTERFACE_USER_CTRL0_REG_V3); 349 reg |= SEC_USER0_SMMU_NORMAL; 350 writel_relaxed(reg, qm->io_base + 351 SEC_INTERFACE_USER_CTRL0_REG_V3); 352 353 reg = readl_relaxed(qm->io_base + 354 SEC_INTERFACE_USER_CTRL1_REG_V3); 355 reg &= SEC_USER1_SMMU_MASK_V3; 356 reg |= SEC_USER1_SMMU_NORMAL_V3; 357 writel_relaxed(reg, qm->io_base + 358 SEC_INTERFACE_USER_CTRL1_REG_V3); 359 } else { 360 reg = readl_relaxed(qm->io_base + 361 SEC_INTERFACE_USER_CTRL0_REG); 362 reg |= SEC_USER0_SMMU_NORMAL; 363 writel_relaxed(reg, qm->io_base + 364 SEC_INTERFACE_USER_CTRL0_REG); 365 reg = readl_relaxed(qm->io_base + 366 SEC_INTERFACE_USER_CTRL1_REG); 367 reg &= SEC_USER1_SMMU_MASK; 368 if (qm->use_sva) 369 reg |= SEC_USER1_SMMU_SVA; 370 else 371 reg |= SEC_USER1_SMMU_NORMAL; 372 writel_relaxed(reg, qm->io_base + 373 SEC_INTERFACE_USER_CTRL1_REG); 374 } 375 } 376 377 static void sec_open_sva_prefetch(struct hisi_qm *qm) 378 { 379 u32 val; 380 int ret; 381 382 if (qm->ver < QM_HW_V3) 383 return; 384 385 /* Enable prefetch */ 386 val = readl_relaxed(qm->io_base + SEC_PREFETCH_CFG); 387 val &= SEC_PREFETCH_ENABLE; 388 writel(val, qm->io_base + SEC_PREFETCH_CFG); 389 390 ret = readl_relaxed_poll_timeout(qm->io_base + SEC_PREFETCH_CFG, 391 val, !(val & SEC_PREFETCH_DISABLE), 392 SEC_DELAY_10_US, SEC_POLL_TIMEOUT_US); 393 if (ret) 394 pci_err(qm->pdev, "failed to open sva prefetch\n"); 395 } 396 397 static void sec_close_sva_prefetch(struct hisi_qm *qm) 398 { 399 u32 val; 400 int ret; 401 402 if (qm->ver < QM_HW_V3) 403 return; 404 405 val = readl_relaxed(qm->io_base + SEC_PREFETCH_CFG); 406 val |= SEC_PREFETCH_DISABLE; 407 writel(val, qm->io_base + SEC_PREFETCH_CFG); 408 409 ret = readl_relaxed_poll_timeout(qm->io_base + SEC_SVA_TRANS, 410 val, !(val & SEC_SVA_DISABLE_READY), 411 SEC_DELAY_10_US, SEC_POLL_TIMEOUT_US); 412 if (ret) 413 pci_err(qm->pdev, "failed to close sva prefetch\n"); 414 } 415 416 static void sec_enable_clock_gate(struct hisi_qm *qm) 417 { 418 u32 val; 419 420 if (qm->ver < QM_HW_V3) 421 return; 422 423 val = readl_relaxed(qm->io_base + SEC_CONTROL_REG); 424 val |= SEC_CLK_GATE_ENABLE; 425 writel_relaxed(val, qm->io_base + SEC_CONTROL_REG); 426 427 val = readl(qm->io_base + SEC_DYNAMIC_GATE_REG); 428 val |= SEC_DYNAMIC_GATE_EN; 429 writel(val, qm->io_base + SEC_DYNAMIC_GATE_REG); 430 431 val = readl(qm->io_base + SEC_CORE_AUTO_GATE); 432 val |= SEC_CORE_AUTO_GATE_EN; 433 writel(val, qm->io_base + SEC_CORE_AUTO_GATE); 434 } 435 436 static void sec_disable_clock_gate(struct hisi_qm *qm) 437 { 438 u32 val; 439 440 /* Kunpeng920 needs to close clock gating */ 441 val = readl_relaxed(qm->io_base + SEC_CONTROL_REG); 442 val &= SEC_CLK_GATE_DISABLE; 443 writel_relaxed(val, qm->io_base + SEC_CONTROL_REG); 444 } 445 446 static int sec_engine_init(struct hisi_qm *qm) 447 { 448 int ret; 449 u32 reg; 450 451 /* disable clock gate control before mem init */ 452 sec_disable_clock_gate(qm); 453 454 writel_relaxed(0x1, qm->io_base + SEC_MEM_START_INIT_REG); 455 456 ret = readl_relaxed_poll_timeout(qm->io_base + SEC_MEM_INIT_DONE_REG, 457 reg, reg & 0x1, SEC_DELAY_10_US, 458 SEC_POLL_TIMEOUT_US); 459 if (ret) { 460 pci_err(qm->pdev, "fail to init sec mem\n"); 461 return ret; 462 } 463 464 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG); 465 reg |= (0x1 << SEC_TRNG_EN_SHIFT); 466 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG); 467 468 sec_engine_sva_config(qm); 469 470 writel(SEC_SINGLE_PORT_MAX_TRANS, 471 qm->io_base + AM_CFG_SINGLE_PORT_MAX_TRANS); 472 473 writel(SEC_SAA_ENABLE, qm->io_base + SEC_SAA_EN_REG); 474 475 /* HW V2 enable sm4 extra mode, as ctr/ecb */ 476 if (qm->ver < QM_HW_V3) 477 writel_relaxed(SEC_BD_ERR_CHK_EN0, 478 qm->io_base + SEC_BD_ERR_CHK_EN_REG0); 479 480 /* Enable sm4 xts mode multiple iv */ 481 writel_relaxed(SEC_BD_ERR_CHK_EN1, 482 qm->io_base + SEC_BD_ERR_CHK_EN_REG1); 483 writel_relaxed(SEC_BD_ERR_CHK_EN3, 484 qm->io_base + SEC_BD_ERR_CHK_EN_REG3); 485 486 /* config endian */ 487 sec_set_endian(qm); 488 489 sec_enable_clock_gate(qm); 490 491 return 0; 492 } 493 494 static int sec_set_user_domain_and_cache(struct hisi_qm *qm) 495 { 496 /* qm user domain */ 497 writel(AXUSER_BASE, qm->io_base + QM_ARUSER_M_CFG_1); 498 writel(ARUSER_M_CFG_ENABLE, qm->io_base + QM_ARUSER_M_CFG_ENABLE); 499 writel(AXUSER_BASE, qm->io_base + QM_AWUSER_M_CFG_1); 500 writel(AWUSER_M_CFG_ENABLE, qm->io_base + QM_AWUSER_M_CFG_ENABLE); 501 writel(WUSER_M_CFG_ENABLE, qm->io_base + QM_WUSER_M_CFG_ENABLE); 502 503 /* qm cache */ 504 writel(AXI_M_CFG, qm->io_base + QM_AXI_M_CFG); 505 writel(AXI_M_CFG_ENABLE, qm->io_base + QM_AXI_M_CFG_ENABLE); 506 507 /* disable FLR triggered by BME(bus master enable) */ 508 writel(PEH_AXUSER_CFG, qm->io_base + QM_PEH_AXUSER_CFG); 509 writel(PEH_AXUSER_CFG_ENABLE, qm->io_base + QM_PEH_AXUSER_CFG_ENABLE); 510 511 /* enable sqc,cqc writeback */ 512 writel(SQC_CACHE_ENABLE | CQC_CACHE_ENABLE | SQC_CACHE_WB_ENABLE | 513 CQC_CACHE_WB_ENABLE | FIELD_PREP(SQC_CACHE_WB_THRD, 1) | 514 FIELD_PREP(CQC_CACHE_WB_THRD, 1), qm->io_base + QM_CACHE_CTL); 515 516 return sec_engine_init(qm); 517 } 518 519 /* sec_debug_regs_clear() - clear the sec debug regs */ 520 static void sec_debug_regs_clear(struct hisi_qm *qm) 521 { 522 int i; 523 524 /* clear sec dfx regs */ 525 writel(0x1, qm->io_base + SEC_CTRL_CNT_CLR_CE); 526 for (i = 0; i < ARRAY_SIZE(sec_dfx_regs); i++) 527 readl(qm->io_base + sec_dfx_regs[i].offset); 528 529 /* clear rdclr_en */ 530 writel(0x0, qm->io_base + SEC_CTRL_CNT_CLR_CE); 531 532 hisi_qm_debug_regs_clear(qm); 533 } 534 535 static void sec_master_ooo_ctrl(struct hisi_qm *qm, bool enable) 536 { 537 u32 val1, val2; 538 539 val1 = readl(qm->io_base + SEC_CONTROL_REG); 540 if (enable) { 541 val1 |= SEC_AXI_SHUTDOWN_ENABLE; 542 val2 = SEC_RAS_NFE_ENB_MSK; 543 } else { 544 val1 &= SEC_AXI_SHUTDOWN_DISABLE; 545 val2 = 0x0; 546 } 547 548 if (qm->ver > QM_HW_V2) 549 writel(val2, qm->io_base + SEC_OOO_SHUTDOWN_SEL); 550 551 writel(val1, qm->io_base + SEC_CONTROL_REG); 552 } 553 554 static void sec_hw_error_enable(struct hisi_qm *qm) 555 { 556 if (qm->ver == QM_HW_V1) { 557 writel(SEC_CORE_INT_DISABLE, qm->io_base + SEC_CORE_INT_MASK); 558 pci_info(qm->pdev, "V1 not support hw error handle\n"); 559 return; 560 } 561 562 /* clear SEC hw error source if having */ 563 writel(SEC_CORE_INT_CLEAR, qm->io_base + SEC_CORE_INT_SOURCE); 564 565 /* enable RAS int */ 566 writel(SEC_RAS_CE_ENB_MSK, qm->io_base + SEC_RAS_CE_REG); 567 writel(SEC_RAS_FE_ENB_MSK, qm->io_base + SEC_RAS_FE_REG); 568 writel(SEC_RAS_NFE_ENB_MSK, qm->io_base + SEC_RAS_NFE_REG); 569 570 /* enable SEC block master OOO when nfe occurs on Kunpeng930 */ 571 sec_master_ooo_ctrl(qm, true); 572 573 /* enable SEC hw error interrupts */ 574 writel(SEC_CORE_INT_ENABLE, qm->io_base + SEC_CORE_INT_MASK); 575 } 576 577 static void sec_hw_error_disable(struct hisi_qm *qm) 578 { 579 /* disable SEC hw error interrupts */ 580 writel(SEC_CORE_INT_DISABLE, qm->io_base + SEC_CORE_INT_MASK); 581 582 /* disable SEC block master OOO when nfe occurs on Kunpeng930 */ 583 sec_master_ooo_ctrl(qm, false); 584 585 /* disable RAS int */ 586 writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_CE_REG); 587 writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_FE_REG); 588 writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_NFE_REG); 589 } 590 591 static u32 sec_clear_enable_read(struct hisi_qm *qm) 592 { 593 return readl(qm->io_base + SEC_CTRL_CNT_CLR_CE) & 594 SEC_CTRL_CNT_CLR_CE_BIT; 595 } 596 597 static int sec_clear_enable_write(struct hisi_qm *qm, u32 val) 598 { 599 u32 tmp; 600 601 if (val != 1 && val) 602 return -EINVAL; 603 604 tmp = (readl(qm->io_base + SEC_CTRL_CNT_CLR_CE) & 605 ~SEC_CTRL_CNT_CLR_CE_BIT) | val; 606 writel(tmp, qm->io_base + SEC_CTRL_CNT_CLR_CE); 607 608 return 0; 609 } 610 611 static ssize_t sec_debug_read(struct file *filp, char __user *buf, 612 size_t count, loff_t *pos) 613 { 614 struct sec_debug_file *file = filp->private_data; 615 char tbuf[SEC_DBGFS_VAL_MAX_LEN]; 616 struct hisi_qm *qm = file->qm; 617 u32 val; 618 int ret; 619 620 ret = hisi_qm_get_dfx_access(qm); 621 if (ret) 622 return ret; 623 624 spin_lock_irq(&file->lock); 625 626 switch (file->index) { 627 case SEC_CLEAR_ENABLE: 628 val = sec_clear_enable_read(qm); 629 break; 630 default: 631 goto err_input; 632 } 633 634 spin_unlock_irq(&file->lock); 635 636 hisi_qm_put_dfx_access(qm); 637 ret = snprintf(tbuf, SEC_DBGFS_VAL_MAX_LEN, "%u\n", val); 638 return simple_read_from_buffer(buf, count, pos, tbuf, ret); 639 640 err_input: 641 spin_unlock_irq(&file->lock); 642 hisi_qm_put_dfx_access(qm); 643 return -EINVAL; 644 } 645 646 static ssize_t sec_debug_write(struct file *filp, const char __user *buf, 647 size_t count, loff_t *pos) 648 { 649 struct sec_debug_file *file = filp->private_data; 650 char tbuf[SEC_DBGFS_VAL_MAX_LEN]; 651 struct hisi_qm *qm = file->qm; 652 unsigned long val; 653 int len, ret; 654 655 if (*pos != 0) 656 return 0; 657 658 if (count >= SEC_DBGFS_VAL_MAX_LEN) 659 return -ENOSPC; 660 661 len = simple_write_to_buffer(tbuf, SEC_DBGFS_VAL_MAX_LEN - 1, 662 pos, buf, count); 663 if (len < 0) 664 return len; 665 666 tbuf[len] = '\0'; 667 if (kstrtoul(tbuf, 0, &val)) 668 return -EFAULT; 669 670 ret = hisi_qm_get_dfx_access(qm); 671 if (ret) 672 return ret; 673 674 spin_lock_irq(&file->lock); 675 676 switch (file->index) { 677 case SEC_CLEAR_ENABLE: 678 ret = sec_clear_enable_write(qm, val); 679 if (ret) 680 goto err_input; 681 break; 682 default: 683 ret = -EINVAL; 684 goto err_input; 685 } 686 687 ret = count; 688 689 err_input: 690 spin_unlock_irq(&file->lock); 691 hisi_qm_put_dfx_access(qm); 692 return ret; 693 } 694 695 static const struct file_operations sec_dbg_fops = { 696 .owner = THIS_MODULE, 697 .open = simple_open, 698 .read = sec_debug_read, 699 .write = sec_debug_write, 700 }; 701 702 static int sec_debugfs_atomic64_get(void *data, u64 *val) 703 { 704 *val = atomic64_read((atomic64_t *)data); 705 706 return 0; 707 } 708 709 static int sec_debugfs_atomic64_set(void *data, u64 val) 710 { 711 if (val) 712 return -EINVAL; 713 714 atomic64_set((atomic64_t *)data, 0); 715 716 return 0; 717 } 718 719 DEFINE_DEBUGFS_ATTRIBUTE(sec_atomic64_ops, sec_debugfs_atomic64_get, 720 sec_debugfs_atomic64_set, "%lld\n"); 721 722 static int sec_regs_show(struct seq_file *s, void *unused) 723 { 724 hisi_qm_regs_dump(s, s->private); 725 726 return 0; 727 } 728 729 DEFINE_SHOW_ATTRIBUTE(sec_regs); 730 731 static int sec_core_debug_init(struct hisi_qm *qm) 732 { 733 struct sec_dev *sec = container_of(qm, struct sec_dev, qm); 734 struct device *dev = &qm->pdev->dev; 735 struct sec_dfx *dfx = &sec->debug.dfx; 736 struct debugfs_regset32 *regset; 737 struct dentry *tmp_d; 738 int i; 739 740 tmp_d = debugfs_create_dir("sec_dfx", qm->debug.debug_root); 741 742 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 743 if (!regset) 744 return -ENOMEM; 745 746 regset->regs = sec_dfx_regs; 747 regset->nregs = ARRAY_SIZE(sec_dfx_regs); 748 regset->base = qm->io_base; 749 regset->dev = dev; 750 751 if (qm->pdev->device == SEC_PF_PCI_DEVICE_ID) 752 debugfs_create_file("regs", 0444, tmp_d, regset, &sec_regs_fops); 753 754 for (i = 0; i < ARRAY_SIZE(sec_dfx_labels); i++) { 755 atomic64_t *data = (atomic64_t *)((uintptr_t)dfx + 756 sec_dfx_labels[i].offset); 757 debugfs_create_file(sec_dfx_labels[i].name, 0644, 758 tmp_d, data, &sec_atomic64_ops); 759 } 760 761 return 0; 762 } 763 764 static int sec_debug_init(struct hisi_qm *qm) 765 { 766 struct sec_dev *sec = container_of(qm, struct sec_dev, qm); 767 int i; 768 769 if (qm->pdev->device == SEC_PF_PCI_DEVICE_ID) { 770 for (i = SEC_CLEAR_ENABLE; i < SEC_DEBUG_FILE_NUM; i++) { 771 spin_lock_init(&sec->debug.files[i].lock); 772 sec->debug.files[i].index = i; 773 sec->debug.files[i].qm = qm; 774 775 debugfs_create_file(sec_dbg_file_name[i], 0600, 776 qm->debug.debug_root, 777 sec->debug.files + i, 778 &sec_dbg_fops); 779 } 780 } 781 782 return sec_core_debug_init(qm); 783 } 784 785 static int sec_debugfs_init(struct hisi_qm *qm) 786 { 787 struct device *dev = &qm->pdev->dev; 788 int ret; 789 790 qm->debug.debug_root = debugfs_create_dir(dev_name(dev), 791 sec_debugfs_root); 792 qm->debug.sqe_mask_offset = SEC_SQE_MASK_OFFSET; 793 qm->debug.sqe_mask_len = SEC_SQE_MASK_LEN; 794 hisi_qm_debug_init(qm); 795 796 ret = sec_debug_init(qm); 797 if (ret) 798 goto failed_to_create; 799 800 return 0; 801 802 failed_to_create: 803 debugfs_remove_recursive(sec_debugfs_root); 804 return ret; 805 } 806 807 static void sec_debugfs_exit(struct hisi_qm *qm) 808 { 809 debugfs_remove_recursive(qm->debug.debug_root); 810 } 811 812 static void sec_log_hw_error(struct hisi_qm *qm, u32 err_sts) 813 { 814 const struct sec_hw_error *errs = sec_hw_errors; 815 struct device *dev = &qm->pdev->dev; 816 u32 err_val; 817 818 while (errs->msg) { 819 if (errs->int_msk & err_sts) { 820 dev_err(dev, "%s [error status=0x%x] found\n", 821 errs->msg, errs->int_msk); 822 823 if (SEC_CORE_INT_STATUS_M_ECC & errs->int_msk) { 824 err_val = readl(qm->io_base + 825 SEC_CORE_SRAM_ECC_ERR_INFO); 826 dev_err(dev, "multi ecc sram num=0x%x\n", 827 ((err_val) >> SEC_ECC_NUM) & 828 SEC_ECC_MASH); 829 } 830 } 831 errs++; 832 } 833 } 834 835 static u32 sec_get_hw_err_status(struct hisi_qm *qm) 836 { 837 return readl(qm->io_base + SEC_CORE_INT_STATUS); 838 } 839 840 static void sec_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts) 841 { 842 writel(err_sts, qm->io_base + SEC_CORE_INT_SOURCE); 843 } 844 845 static void sec_open_axi_master_ooo(struct hisi_qm *qm) 846 { 847 u32 val; 848 849 val = readl(qm->io_base + SEC_CONTROL_REG); 850 writel(val & SEC_AXI_SHUTDOWN_DISABLE, qm->io_base + SEC_CONTROL_REG); 851 writel(val | SEC_AXI_SHUTDOWN_ENABLE, qm->io_base + SEC_CONTROL_REG); 852 } 853 854 static void sec_err_info_init(struct hisi_qm *qm) 855 { 856 struct hisi_qm_err_info *err_info = &qm->err_info; 857 858 err_info->ce = QM_BASE_CE; 859 err_info->fe = 0; 860 err_info->ecc_2bits_mask = SEC_CORE_INT_STATUS_M_ECC; 861 err_info->dev_ce_mask = SEC_RAS_CE_ENB_MSK; 862 err_info->msi_wr_port = BIT(0); 863 err_info->acpi_rst = "SRST"; 864 err_info->nfe = QM_BASE_NFE | QM_ACC_DO_TASK_TIMEOUT | 865 QM_ACC_WB_NOT_READY_TIMEOUT; 866 } 867 868 static const struct hisi_qm_err_ini sec_err_ini = { 869 .hw_init = sec_set_user_domain_and_cache, 870 .hw_err_enable = sec_hw_error_enable, 871 .hw_err_disable = sec_hw_error_disable, 872 .get_dev_hw_err_status = sec_get_hw_err_status, 873 .clear_dev_hw_err_status = sec_clear_hw_err_status, 874 .log_dev_hw_err = sec_log_hw_error, 875 .open_axi_master_ooo = sec_open_axi_master_ooo, 876 .open_sva_prefetch = sec_open_sva_prefetch, 877 .close_sva_prefetch = sec_close_sva_prefetch, 878 .err_info_init = sec_err_info_init, 879 }; 880 881 static int sec_pf_probe_init(struct sec_dev *sec) 882 { 883 struct hisi_qm *qm = &sec->qm; 884 int ret; 885 886 qm->err_ini = &sec_err_ini; 887 qm->err_ini->err_info_init(qm); 888 889 ret = sec_set_user_domain_and_cache(qm); 890 if (ret) 891 return ret; 892 893 sec_open_sva_prefetch(qm); 894 hisi_qm_dev_err_init(qm); 895 sec_debug_regs_clear(qm); 896 897 return 0; 898 } 899 900 static int sec_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) 901 { 902 int ret; 903 904 qm->pdev = pdev; 905 qm->ver = pdev->revision; 906 qm->algs = "cipher\ndigest\naead"; 907 qm->mode = uacce_mode; 908 qm->sqe_size = SEC_SQE_SIZE; 909 qm->dev_name = sec_name; 910 911 qm->fun_type = (pdev->device == SEC_PF_PCI_DEVICE_ID) ? 912 QM_HW_PF : QM_HW_VF; 913 if (qm->fun_type == QM_HW_PF) { 914 qm->qp_base = SEC_PF_DEF_Q_BASE; 915 qm->qp_num = pf_q_num; 916 qm->debug.curr_qm_qp_num = pf_q_num; 917 qm->qm_list = &sec_devices; 918 } else if (qm->fun_type == QM_HW_VF && qm->ver == QM_HW_V1) { 919 /* 920 * have no way to get qm configure in VM in v1 hardware, 921 * so currently force PF to uses SEC_PF_DEF_Q_NUM, and force 922 * to trigger only one VF in v1 hardware. 923 * v2 hardware has no such problem. 924 */ 925 qm->qp_base = SEC_PF_DEF_Q_NUM; 926 qm->qp_num = SEC_QUEUE_NUM_V1 - SEC_PF_DEF_Q_NUM; 927 } 928 929 /* 930 * WQ_HIGHPRI: SEC request must be low delayed, 931 * so need a high priority workqueue. 932 * WQ_UNBOUND: SEC task is likely with long 933 * running CPU intensive workloads. 934 */ 935 qm->wq = alloc_workqueue("%s", WQ_HIGHPRI | WQ_MEM_RECLAIM | 936 WQ_UNBOUND, num_online_cpus(), 937 pci_name(qm->pdev)); 938 if (!qm->wq) { 939 pci_err(qm->pdev, "fail to alloc workqueue\n"); 940 return -ENOMEM; 941 } 942 943 ret = hisi_qm_init(qm); 944 if (ret) 945 destroy_workqueue(qm->wq); 946 947 return ret; 948 } 949 950 static void sec_qm_uninit(struct hisi_qm *qm) 951 { 952 hisi_qm_uninit(qm); 953 } 954 955 static int sec_probe_init(struct sec_dev *sec) 956 { 957 u32 type_rate = SEC_SHAPER_TYPE_RATE; 958 struct hisi_qm *qm = &sec->qm; 959 int ret; 960 961 if (qm->fun_type == QM_HW_PF) { 962 ret = sec_pf_probe_init(sec); 963 if (ret) 964 return ret; 965 /* enable shaper type 0 */ 966 if (qm->ver >= QM_HW_V3) { 967 type_rate |= QM_SHAPER_ENABLE; 968 qm->type_rate = type_rate; 969 } 970 } 971 972 return 0; 973 } 974 975 static void sec_probe_uninit(struct hisi_qm *qm) 976 { 977 hisi_qm_dev_err_uninit(qm); 978 979 destroy_workqueue(qm->wq); 980 } 981 982 static void sec_iommu_used_check(struct sec_dev *sec) 983 { 984 struct iommu_domain *domain; 985 struct device *dev = &sec->qm.pdev->dev; 986 987 domain = iommu_get_domain_for_dev(dev); 988 989 /* Check if iommu is used */ 990 sec->iommu_used = false; 991 if (domain) { 992 if (domain->type & __IOMMU_DOMAIN_PAGING) 993 sec->iommu_used = true; 994 dev_info(dev, "SMMU Opened, the iommu type = %u\n", 995 domain->type); 996 } 997 } 998 999 static int sec_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1000 { 1001 struct sec_dev *sec; 1002 struct hisi_qm *qm; 1003 int ret; 1004 1005 sec = devm_kzalloc(&pdev->dev, sizeof(*sec), GFP_KERNEL); 1006 if (!sec) 1007 return -ENOMEM; 1008 1009 qm = &sec->qm; 1010 ret = sec_qm_init(qm, pdev); 1011 if (ret) { 1012 pci_err(pdev, "Failed to init SEC QM (%d)!\n", ret); 1013 return ret; 1014 } 1015 1016 sec->ctx_q_num = ctx_q_num; 1017 sec_iommu_used_check(sec); 1018 1019 ret = sec_probe_init(sec); 1020 if (ret) { 1021 pci_err(pdev, "Failed to probe!\n"); 1022 goto err_qm_uninit; 1023 } 1024 1025 ret = hisi_qm_start(qm); 1026 if (ret) { 1027 pci_err(pdev, "Failed to start sec qm!\n"); 1028 goto err_probe_uninit; 1029 } 1030 1031 ret = sec_debugfs_init(qm); 1032 if (ret) 1033 pci_warn(pdev, "Failed to init debugfs!\n"); 1034 1035 if (qm->qp_num >= ctx_q_num) { 1036 ret = hisi_qm_alg_register(qm, &sec_devices); 1037 if (ret < 0) { 1038 pr_err("Failed to register driver to crypto.\n"); 1039 goto err_qm_stop; 1040 } 1041 } else { 1042 pci_warn(qm->pdev, 1043 "Failed to use kernel mode, qp not enough!\n"); 1044 } 1045 1046 if (qm->uacce) { 1047 ret = uacce_register(qm->uacce); 1048 if (ret) { 1049 pci_err(pdev, "failed to register uacce (%d)!\n", ret); 1050 goto err_alg_unregister; 1051 } 1052 } 1053 1054 if (qm->fun_type == QM_HW_PF && vfs_num) { 1055 ret = hisi_qm_sriov_enable(pdev, vfs_num); 1056 if (ret < 0) 1057 goto err_alg_unregister; 1058 } 1059 1060 hisi_qm_pm_init(qm); 1061 1062 return 0; 1063 1064 err_alg_unregister: 1065 if (qm->qp_num >= ctx_q_num) 1066 hisi_qm_alg_unregister(qm, &sec_devices); 1067 err_qm_stop: 1068 sec_debugfs_exit(qm); 1069 hisi_qm_stop(qm, QM_NORMAL); 1070 err_probe_uninit: 1071 sec_probe_uninit(qm); 1072 err_qm_uninit: 1073 sec_qm_uninit(qm); 1074 return ret; 1075 } 1076 1077 static void sec_remove(struct pci_dev *pdev) 1078 { 1079 struct hisi_qm *qm = pci_get_drvdata(pdev); 1080 1081 hisi_qm_pm_uninit(qm); 1082 hisi_qm_wait_task_finish(qm, &sec_devices); 1083 if (qm->qp_num >= ctx_q_num) 1084 hisi_qm_alg_unregister(qm, &sec_devices); 1085 1086 if (qm->fun_type == QM_HW_PF && qm->vfs_num) 1087 hisi_qm_sriov_disable(pdev, true); 1088 1089 sec_debugfs_exit(qm); 1090 1091 (void)hisi_qm_stop(qm, QM_NORMAL); 1092 1093 if (qm->fun_type == QM_HW_PF) 1094 sec_debug_regs_clear(qm); 1095 1096 sec_probe_uninit(qm); 1097 1098 sec_qm_uninit(qm); 1099 } 1100 1101 static const struct dev_pm_ops sec_pm_ops = { 1102 SET_RUNTIME_PM_OPS(hisi_qm_suspend, hisi_qm_resume, NULL) 1103 }; 1104 1105 static const struct pci_error_handlers sec_err_handler = { 1106 .error_detected = hisi_qm_dev_err_detected, 1107 .slot_reset = hisi_qm_dev_slot_reset, 1108 .reset_prepare = hisi_qm_reset_prepare, 1109 .reset_done = hisi_qm_reset_done, 1110 }; 1111 1112 static struct pci_driver sec_pci_driver = { 1113 .name = "hisi_sec2", 1114 .id_table = sec_dev_ids, 1115 .probe = sec_probe, 1116 .remove = sec_remove, 1117 .err_handler = &sec_err_handler, 1118 .sriov_configure = hisi_qm_sriov_configure, 1119 .shutdown = hisi_qm_dev_shutdown, 1120 .driver.pm = &sec_pm_ops, 1121 }; 1122 1123 static void sec_register_debugfs(void) 1124 { 1125 if (!debugfs_initialized()) 1126 return; 1127 1128 sec_debugfs_root = debugfs_create_dir("hisi_sec2", NULL); 1129 } 1130 1131 static void sec_unregister_debugfs(void) 1132 { 1133 debugfs_remove_recursive(sec_debugfs_root); 1134 } 1135 1136 static int __init sec_init(void) 1137 { 1138 int ret; 1139 1140 hisi_qm_init_list(&sec_devices); 1141 sec_register_debugfs(); 1142 1143 ret = pci_register_driver(&sec_pci_driver); 1144 if (ret < 0) { 1145 sec_unregister_debugfs(); 1146 pr_err("Failed to register pci driver.\n"); 1147 return ret; 1148 } 1149 1150 return 0; 1151 } 1152 1153 static void __exit sec_exit(void) 1154 { 1155 pci_unregister_driver(&sec_pci_driver); 1156 sec_unregister_debugfs(); 1157 } 1158 1159 module_init(sec_init); 1160 module_exit(sec_exit); 1161 1162 MODULE_LICENSE("GPL v2"); 1163 MODULE_AUTHOR("Zaibo Xu <xuzaibo@huawei.com>"); 1164 MODULE_AUTHOR("Longfang Liu <liulongfang@huawei.com>"); 1165 MODULE_AUTHOR("Kai Ye <yekai13@huawei.com>"); 1166 MODULE_AUTHOR("Wei Zhang <zhangwei375@huawei.com>"); 1167 MODULE_DESCRIPTION("Driver for HiSilicon SEC accelerator"); 1168