1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2019 HiSilicon Limited. */ 3 4 #include <linux/acpi.h> 5 #include <linux/aer.h> 6 #include <linux/bitops.h> 7 #include <linux/debugfs.h> 8 #include <linux/init.h> 9 #include <linux/io.h> 10 #include <linux/iommu.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/pci.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/seq_file.h> 16 #include <linux/topology.h> 17 #include <linux/uacce.h> 18 19 #include "sec.h" 20 21 #define SEC_VF_NUM 63 22 #define SEC_QUEUE_NUM_V1 4096 23 #define PCI_DEVICE_ID_HUAWEI_SEC_PF 0xa255 24 25 #define SEC_BD_ERR_CHK_EN0 0xEFFFFFFF 26 #define SEC_BD_ERR_CHK_EN1 0x7ffff7fd 27 #define SEC_BD_ERR_CHK_EN3 0xffffbfff 28 29 #define SEC_SQE_SIZE 128 30 #define SEC_SQ_SIZE (SEC_SQE_SIZE * QM_Q_DEPTH) 31 #define SEC_PF_DEF_Q_NUM 256 32 #define SEC_PF_DEF_Q_BASE 0 33 #define SEC_CTX_Q_NUM_DEF 2 34 #define SEC_CTX_Q_NUM_MAX 32 35 36 #define SEC_CTRL_CNT_CLR_CE 0x301120 37 #define SEC_CTRL_CNT_CLR_CE_BIT BIT(0) 38 #define SEC_CORE_INT_SOURCE 0x301010 39 #define SEC_CORE_INT_MASK 0x301000 40 #define SEC_CORE_INT_STATUS 0x301008 41 #define SEC_CORE_SRAM_ECC_ERR_INFO 0x301C14 42 #define SEC_ECC_NUM 16 43 #define SEC_ECC_MASH 0xFF 44 #define SEC_CORE_INT_DISABLE 0x0 45 #define SEC_CORE_INT_ENABLE 0x7c1ff 46 #define SEC_CORE_INT_CLEAR 0x7c1ff 47 #define SEC_SAA_ENABLE 0x17f 48 49 #define SEC_RAS_CE_REG 0x301050 50 #define SEC_RAS_FE_REG 0x301054 51 #define SEC_RAS_NFE_REG 0x301058 52 #define SEC_RAS_CE_ENB_MSK 0x88 53 #define SEC_RAS_FE_ENB_MSK 0x0 54 #define SEC_RAS_NFE_ENB_MSK 0x7c177 55 #define SEC_OOO_SHUTDOWN_SEL 0x301014 56 #define SEC_RAS_DISABLE 0x0 57 #define SEC_MEM_START_INIT_REG 0x301100 58 #define SEC_MEM_INIT_DONE_REG 0x301104 59 60 /* clock gating */ 61 #define SEC_CONTROL_REG 0x301200 62 #define SEC_DYNAMIC_GATE_REG 0x30121c 63 #define SEC_CORE_AUTO_GATE 0x30212c 64 #define SEC_DYNAMIC_GATE_EN 0x7bff 65 #define SEC_CORE_AUTO_GATE_EN GENMASK(3, 0) 66 #define SEC_CLK_GATE_ENABLE BIT(3) 67 #define SEC_CLK_GATE_DISABLE (~BIT(3)) 68 69 #define SEC_TRNG_EN_SHIFT 8 70 #define SEC_AXI_SHUTDOWN_ENABLE BIT(12) 71 #define SEC_AXI_SHUTDOWN_DISABLE 0xFFFFEFFF 72 73 #define SEC_INTERFACE_USER_CTRL0_REG 0x301220 74 #define SEC_INTERFACE_USER_CTRL1_REG 0x301224 75 #define SEC_SAA_EN_REG 0x301270 76 #define SEC_BD_ERR_CHK_EN_REG0 0x301380 77 #define SEC_BD_ERR_CHK_EN_REG1 0x301384 78 #define SEC_BD_ERR_CHK_EN_REG3 0x30138c 79 80 #define SEC_USER0_SMMU_NORMAL (BIT(23) | BIT(15)) 81 #define SEC_USER1_SMMU_NORMAL (BIT(31) | BIT(23) | BIT(15) | BIT(7)) 82 #define SEC_USER1_ENABLE_CONTEXT_SSV BIT(24) 83 #define SEC_USER1_ENABLE_DATA_SSV BIT(16) 84 #define SEC_USER1_WB_CONTEXT_SSV BIT(8) 85 #define SEC_USER1_WB_DATA_SSV BIT(0) 86 #define SEC_USER1_SVA_SET (SEC_USER1_ENABLE_CONTEXT_SSV | \ 87 SEC_USER1_ENABLE_DATA_SSV | \ 88 SEC_USER1_WB_CONTEXT_SSV | \ 89 SEC_USER1_WB_DATA_SSV) 90 #define SEC_USER1_SMMU_SVA (SEC_USER1_SMMU_NORMAL | SEC_USER1_SVA_SET) 91 #define SEC_USER1_SMMU_MASK (~SEC_USER1_SVA_SET) 92 #define SEC_INTERFACE_USER_CTRL0_REG_V3 0x302220 93 #define SEC_INTERFACE_USER_CTRL1_REG_V3 0x302224 94 #define SEC_USER1_SMMU_NORMAL_V3 (BIT(23) | BIT(17) | BIT(11) | BIT(5)) 95 #define SEC_USER1_SMMU_MASK_V3 0xFF79E79E 96 #define SEC_CORE_INT_STATUS_M_ECC BIT(2) 97 98 #define SEC_PREFETCH_CFG 0x301130 99 #define SEC_SVA_TRANS 0x301EC4 100 #define SEC_PREFETCH_ENABLE (~(BIT(0) | BIT(1) | BIT(11))) 101 #define SEC_PREFETCH_DISABLE BIT(1) 102 #define SEC_SVA_DISABLE_READY (BIT(7) | BIT(11)) 103 104 #define SEC_DELAY_10_US 10 105 #define SEC_POLL_TIMEOUT_US 1000 106 #define SEC_DBGFS_VAL_MAX_LEN 20 107 #define SEC_SINGLE_PORT_MAX_TRANS 0x2060 108 109 #define SEC_SQE_MASK_OFFSET 64 110 #define SEC_SQE_MASK_LEN 48 111 #define SEC_SHAPER_TYPE_RATE 400 112 113 struct sec_hw_error { 114 u32 int_msk; 115 const char *msg; 116 }; 117 118 struct sec_dfx_item { 119 const char *name; 120 u32 offset; 121 }; 122 123 static const char sec_name[] = "hisi_sec2"; 124 static struct dentry *sec_debugfs_root; 125 126 static struct hisi_qm_list sec_devices = { 127 .register_to_crypto = sec_register_to_crypto, 128 .unregister_from_crypto = sec_unregister_from_crypto, 129 }; 130 131 static const struct sec_hw_error sec_hw_errors[] = { 132 { 133 .int_msk = BIT(0), 134 .msg = "sec_axi_rresp_err_rint" 135 }, 136 { 137 .int_msk = BIT(1), 138 .msg = "sec_axi_bresp_err_rint" 139 }, 140 { 141 .int_msk = BIT(2), 142 .msg = "sec_ecc_2bit_err_rint" 143 }, 144 { 145 .int_msk = BIT(3), 146 .msg = "sec_ecc_1bit_err_rint" 147 }, 148 { 149 .int_msk = BIT(4), 150 .msg = "sec_req_trng_timeout_rint" 151 }, 152 { 153 .int_msk = BIT(5), 154 .msg = "sec_fsm_hbeat_rint" 155 }, 156 { 157 .int_msk = BIT(6), 158 .msg = "sec_channel_req_rng_timeout_rint" 159 }, 160 { 161 .int_msk = BIT(7), 162 .msg = "sec_bd_err_rint" 163 }, 164 { 165 .int_msk = BIT(8), 166 .msg = "sec_chain_buff_err_rint" 167 }, 168 { 169 .int_msk = BIT(14), 170 .msg = "sec_no_secure_access" 171 }, 172 { 173 .int_msk = BIT(15), 174 .msg = "sec_wrapping_key_auth_err" 175 }, 176 { 177 .int_msk = BIT(16), 178 .msg = "sec_km_key_crc_fail" 179 }, 180 { 181 .int_msk = BIT(17), 182 .msg = "sec_axi_poison_err" 183 }, 184 { 185 .int_msk = BIT(18), 186 .msg = "sec_sva_err" 187 }, 188 {} 189 }; 190 191 static const char * const sec_dbg_file_name[] = { 192 [SEC_CLEAR_ENABLE] = "clear_enable", 193 }; 194 195 static struct sec_dfx_item sec_dfx_labels[] = { 196 {"send_cnt", offsetof(struct sec_dfx, send_cnt)}, 197 {"recv_cnt", offsetof(struct sec_dfx, recv_cnt)}, 198 {"send_busy_cnt", offsetof(struct sec_dfx, send_busy_cnt)}, 199 {"recv_busy_cnt", offsetof(struct sec_dfx, recv_busy_cnt)}, 200 {"err_bd_cnt", offsetof(struct sec_dfx, err_bd_cnt)}, 201 {"invalid_req_cnt", offsetof(struct sec_dfx, invalid_req_cnt)}, 202 {"done_flag_cnt", offsetof(struct sec_dfx, done_flag_cnt)}, 203 }; 204 205 static const struct debugfs_reg32 sec_dfx_regs[] = { 206 {"SEC_PF_ABNORMAL_INT_SOURCE ", 0x301010}, 207 {"SEC_SAA_EN ", 0x301270}, 208 {"SEC_BD_LATENCY_MIN ", 0x301600}, 209 {"SEC_BD_LATENCY_MAX ", 0x301608}, 210 {"SEC_BD_LATENCY_AVG ", 0x30160C}, 211 {"SEC_BD_NUM_IN_SAA0 ", 0x301670}, 212 {"SEC_BD_NUM_IN_SAA1 ", 0x301674}, 213 {"SEC_BD_NUM_IN_SEC ", 0x301680}, 214 {"SEC_ECC_1BIT_CNT ", 0x301C00}, 215 {"SEC_ECC_1BIT_INFO ", 0x301C04}, 216 {"SEC_ECC_2BIT_CNT ", 0x301C10}, 217 {"SEC_ECC_2BIT_INFO ", 0x301C14}, 218 {"SEC_BD_SAA0 ", 0x301C20}, 219 {"SEC_BD_SAA1 ", 0x301C24}, 220 {"SEC_BD_SAA2 ", 0x301C28}, 221 {"SEC_BD_SAA3 ", 0x301C2C}, 222 {"SEC_BD_SAA4 ", 0x301C30}, 223 {"SEC_BD_SAA5 ", 0x301C34}, 224 {"SEC_BD_SAA6 ", 0x301C38}, 225 {"SEC_BD_SAA7 ", 0x301C3C}, 226 {"SEC_BD_SAA8 ", 0x301C40}, 227 }; 228 229 static int sec_pf_q_num_set(const char *val, const struct kernel_param *kp) 230 { 231 return q_num_set(val, kp, PCI_DEVICE_ID_HUAWEI_SEC_PF); 232 } 233 234 static const struct kernel_param_ops sec_pf_q_num_ops = { 235 .set = sec_pf_q_num_set, 236 .get = param_get_int, 237 }; 238 239 static u32 pf_q_num = SEC_PF_DEF_Q_NUM; 240 module_param_cb(pf_q_num, &sec_pf_q_num_ops, &pf_q_num, 0444); 241 MODULE_PARM_DESC(pf_q_num, "Number of queues in PF(v1 2-4096, v2 2-1024)"); 242 243 static int sec_ctx_q_num_set(const char *val, const struct kernel_param *kp) 244 { 245 u32 ctx_q_num; 246 int ret; 247 248 if (!val) 249 return -EINVAL; 250 251 ret = kstrtou32(val, 10, &ctx_q_num); 252 if (ret) 253 return -EINVAL; 254 255 if (!ctx_q_num || ctx_q_num > SEC_CTX_Q_NUM_MAX || ctx_q_num & 0x1) { 256 pr_err("ctx queue num[%u] is invalid!\n", ctx_q_num); 257 return -EINVAL; 258 } 259 260 return param_set_int(val, kp); 261 } 262 263 static const struct kernel_param_ops sec_ctx_q_num_ops = { 264 .set = sec_ctx_q_num_set, 265 .get = param_get_int, 266 }; 267 static u32 ctx_q_num = SEC_CTX_Q_NUM_DEF; 268 module_param_cb(ctx_q_num, &sec_ctx_q_num_ops, &ctx_q_num, 0444); 269 MODULE_PARM_DESC(ctx_q_num, "Queue num in ctx (2 default, 2, 4, ..., 32)"); 270 271 static const struct kernel_param_ops vfs_num_ops = { 272 .set = vfs_num_set, 273 .get = param_get_int, 274 }; 275 276 static u32 vfs_num; 277 module_param_cb(vfs_num, &vfs_num_ops, &vfs_num, 0444); 278 MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)"); 279 280 void sec_destroy_qps(struct hisi_qp **qps, int qp_num) 281 { 282 hisi_qm_free_qps(qps, qp_num); 283 kfree(qps); 284 } 285 286 struct hisi_qp **sec_create_qps(void) 287 { 288 int node = cpu_to_node(smp_processor_id()); 289 u32 ctx_num = ctx_q_num; 290 struct hisi_qp **qps; 291 int ret; 292 293 qps = kcalloc(ctx_num, sizeof(struct hisi_qp *), GFP_KERNEL); 294 if (!qps) 295 return NULL; 296 297 ret = hisi_qm_alloc_qps_node(&sec_devices, ctx_num, 0, node, qps); 298 if (!ret) 299 return qps; 300 301 kfree(qps); 302 return NULL; 303 } 304 305 static const struct kernel_param_ops sec_uacce_mode_ops = { 306 .set = uacce_mode_set, 307 .get = param_get_int, 308 }; 309 310 /* 311 * uacce_mode = 0 means sec only register to crypto, 312 * uacce_mode = 1 means sec both register to crypto and uacce. 313 */ 314 static u32 uacce_mode = UACCE_MODE_NOUACCE; 315 module_param_cb(uacce_mode, &sec_uacce_mode_ops, &uacce_mode, 0444); 316 MODULE_PARM_DESC(uacce_mode, UACCE_MODE_DESC); 317 318 static const struct pci_device_id sec_dev_ids[] = { 319 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_SEC_PF) }, 320 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_SEC_VF) }, 321 { 0, } 322 }; 323 MODULE_DEVICE_TABLE(pci, sec_dev_ids); 324 325 static void sec_set_endian(struct hisi_qm *qm) 326 { 327 u32 reg; 328 329 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG); 330 reg &= ~(BIT(1) | BIT(0)); 331 if (!IS_ENABLED(CONFIG_64BIT)) 332 reg |= BIT(1); 333 334 335 if (!IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN)) 336 reg |= BIT(0); 337 338 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG); 339 } 340 341 static void sec_engine_sva_config(struct hisi_qm *qm) 342 { 343 u32 reg; 344 345 if (qm->ver > QM_HW_V2) { 346 reg = readl_relaxed(qm->io_base + 347 SEC_INTERFACE_USER_CTRL0_REG_V3); 348 reg |= SEC_USER0_SMMU_NORMAL; 349 writel_relaxed(reg, qm->io_base + 350 SEC_INTERFACE_USER_CTRL0_REG_V3); 351 352 reg = readl_relaxed(qm->io_base + 353 SEC_INTERFACE_USER_CTRL1_REG_V3); 354 reg &= SEC_USER1_SMMU_MASK_V3; 355 reg |= SEC_USER1_SMMU_NORMAL_V3; 356 writel_relaxed(reg, qm->io_base + 357 SEC_INTERFACE_USER_CTRL1_REG_V3); 358 } else { 359 reg = readl_relaxed(qm->io_base + 360 SEC_INTERFACE_USER_CTRL0_REG); 361 reg |= SEC_USER0_SMMU_NORMAL; 362 writel_relaxed(reg, qm->io_base + 363 SEC_INTERFACE_USER_CTRL0_REG); 364 reg = readl_relaxed(qm->io_base + 365 SEC_INTERFACE_USER_CTRL1_REG); 366 reg &= SEC_USER1_SMMU_MASK; 367 if (qm->use_sva) 368 reg |= SEC_USER1_SMMU_SVA; 369 else 370 reg |= SEC_USER1_SMMU_NORMAL; 371 writel_relaxed(reg, qm->io_base + 372 SEC_INTERFACE_USER_CTRL1_REG); 373 } 374 } 375 376 static void sec_open_sva_prefetch(struct hisi_qm *qm) 377 { 378 u32 val; 379 int ret; 380 381 if (qm->ver < QM_HW_V3) 382 return; 383 384 /* Enable prefetch */ 385 val = readl_relaxed(qm->io_base + SEC_PREFETCH_CFG); 386 val &= SEC_PREFETCH_ENABLE; 387 writel(val, qm->io_base + SEC_PREFETCH_CFG); 388 389 ret = readl_relaxed_poll_timeout(qm->io_base + SEC_PREFETCH_CFG, 390 val, !(val & SEC_PREFETCH_DISABLE), 391 SEC_DELAY_10_US, SEC_POLL_TIMEOUT_US); 392 if (ret) 393 pci_err(qm->pdev, "failed to open sva prefetch\n"); 394 } 395 396 static void sec_close_sva_prefetch(struct hisi_qm *qm) 397 { 398 u32 val; 399 int ret; 400 401 if (qm->ver < QM_HW_V3) 402 return; 403 404 val = readl_relaxed(qm->io_base + SEC_PREFETCH_CFG); 405 val |= SEC_PREFETCH_DISABLE; 406 writel(val, qm->io_base + SEC_PREFETCH_CFG); 407 408 ret = readl_relaxed_poll_timeout(qm->io_base + SEC_SVA_TRANS, 409 val, !(val & SEC_SVA_DISABLE_READY), 410 SEC_DELAY_10_US, SEC_POLL_TIMEOUT_US); 411 if (ret) 412 pci_err(qm->pdev, "failed to close sva prefetch\n"); 413 } 414 415 static void sec_enable_clock_gate(struct hisi_qm *qm) 416 { 417 u32 val; 418 419 if (qm->ver < QM_HW_V3) 420 return; 421 422 val = readl_relaxed(qm->io_base + SEC_CONTROL_REG); 423 val |= SEC_CLK_GATE_ENABLE; 424 writel_relaxed(val, qm->io_base + SEC_CONTROL_REG); 425 426 val = readl(qm->io_base + SEC_DYNAMIC_GATE_REG); 427 val |= SEC_DYNAMIC_GATE_EN; 428 writel(val, qm->io_base + SEC_DYNAMIC_GATE_REG); 429 430 val = readl(qm->io_base + SEC_CORE_AUTO_GATE); 431 val |= SEC_CORE_AUTO_GATE_EN; 432 writel(val, qm->io_base + SEC_CORE_AUTO_GATE); 433 } 434 435 static void sec_disable_clock_gate(struct hisi_qm *qm) 436 { 437 u32 val; 438 439 /* Kunpeng920 needs to close clock gating */ 440 val = readl_relaxed(qm->io_base + SEC_CONTROL_REG); 441 val &= SEC_CLK_GATE_DISABLE; 442 writel_relaxed(val, qm->io_base + SEC_CONTROL_REG); 443 } 444 445 static int sec_engine_init(struct hisi_qm *qm) 446 { 447 int ret; 448 u32 reg; 449 450 /* disable clock gate control before mem init */ 451 sec_disable_clock_gate(qm); 452 453 writel_relaxed(0x1, qm->io_base + SEC_MEM_START_INIT_REG); 454 455 ret = readl_relaxed_poll_timeout(qm->io_base + SEC_MEM_INIT_DONE_REG, 456 reg, reg & 0x1, SEC_DELAY_10_US, 457 SEC_POLL_TIMEOUT_US); 458 if (ret) { 459 pci_err(qm->pdev, "fail to init sec mem\n"); 460 return ret; 461 } 462 463 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG); 464 reg |= (0x1 << SEC_TRNG_EN_SHIFT); 465 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG); 466 467 sec_engine_sva_config(qm); 468 469 writel(SEC_SINGLE_PORT_MAX_TRANS, 470 qm->io_base + AM_CFG_SINGLE_PORT_MAX_TRANS); 471 472 writel(SEC_SAA_ENABLE, qm->io_base + SEC_SAA_EN_REG); 473 474 /* HW V2 enable sm4 extra mode, as ctr/ecb */ 475 if (qm->ver < QM_HW_V3) 476 writel_relaxed(SEC_BD_ERR_CHK_EN0, 477 qm->io_base + SEC_BD_ERR_CHK_EN_REG0); 478 479 /* Enable sm4 xts mode multiple iv */ 480 writel_relaxed(SEC_BD_ERR_CHK_EN1, 481 qm->io_base + SEC_BD_ERR_CHK_EN_REG1); 482 writel_relaxed(SEC_BD_ERR_CHK_EN3, 483 qm->io_base + SEC_BD_ERR_CHK_EN_REG3); 484 485 /* config endian */ 486 sec_set_endian(qm); 487 488 sec_enable_clock_gate(qm); 489 490 return 0; 491 } 492 493 static int sec_set_user_domain_and_cache(struct hisi_qm *qm) 494 { 495 /* qm user domain */ 496 writel(AXUSER_BASE, qm->io_base + QM_ARUSER_M_CFG_1); 497 writel(ARUSER_M_CFG_ENABLE, qm->io_base + QM_ARUSER_M_CFG_ENABLE); 498 writel(AXUSER_BASE, qm->io_base + QM_AWUSER_M_CFG_1); 499 writel(AWUSER_M_CFG_ENABLE, qm->io_base + QM_AWUSER_M_CFG_ENABLE); 500 writel(WUSER_M_CFG_ENABLE, qm->io_base + QM_WUSER_M_CFG_ENABLE); 501 502 /* qm cache */ 503 writel(AXI_M_CFG, qm->io_base + QM_AXI_M_CFG); 504 writel(AXI_M_CFG_ENABLE, qm->io_base + QM_AXI_M_CFG_ENABLE); 505 506 /* disable FLR triggered by BME(bus master enable) */ 507 writel(PEH_AXUSER_CFG, qm->io_base + QM_PEH_AXUSER_CFG); 508 writel(PEH_AXUSER_CFG_ENABLE, qm->io_base + QM_PEH_AXUSER_CFG_ENABLE); 509 510 /* enable sqc,cqc writeback */ 511 writel(SQC_CACHE_ENABLE | CQC_CACHE_ENABLE | SQC_CACHE_WB_ENABLE | 512 CQC_CACHE_WB_ENABLE | FIELD_PREP(SQC_CACHE_WB_THRD, 1) | 513 FIELD_PREP(CQC_CACHE_WB_THRD, 1), qm->io_base + QM_CACHE_CTL); 514 515 return sec_engine_init(qm); 516 } 517 518 /* sec_debug_regs_clear() - clear the sec debug regs */ 519 static void sec_debug_regs_clear(struct hisi_qm *qm) 520 { 521 int i; 522 523 /* clear sec dfx regs */ 524 writel(0x1, qm->io_base + SEC_CTRL_CNT_CLR_CE); 525 for (i = 0; i < ARRAY_SIZE(sec_dfx_regs); i++) 526 readl(qm->io_base + sec_dfx_regs[i].offset); 527 528 /* clear rdclr_en */ 529 writel(0x0, qm->io_base + SEC_CTRL_CNT_CLR_CE); 530 531 hisi_qm_debug_regs_clear(qm); 532 } 533 534 static void sec_master_ooo_ctrl(struct hisi_qm *qm, bool enable) 535 { 536 u32 val1, val2; 537 538 val1 = readl(qm->io_base + SEC_CONTROL_REG); 539 if (enable) { 540 val1 |= SEC_AXI_SHUTDOWN_ENABLE; 541 val2 = SEC_RAS_NFE_ENB_MSK; 542 } else { 543 val1 &= SEC_AXI_SHUTDOWN_DISABLE; 544 val2 = 0x0; 545 } 546 547 if (qm->ver > QM_HW_V2) 548 writel(val2, qm->io_base + SEC_OOO_SHUTDOWN_SEL); 549 550 writel(val1, qm->io_base + SEC_CONTROL_REG); 551 } 552 553 static void sec_hw_error_enable(struct hisi_qm *qm) 554 { 555 if (qm->ver == QM_HW_V1) { 556 writel(SEC_CORE_INT_DISABLE, qm->io_base + SEC_CORE_INT_MASK); 557 pci_info(qm->pdev, "V1 not support hw error handle\n"); 558 return; 559 } 560 561 /* clear SEC hw error source if having */ 562 writel(SEC_CORE_INT_CLEAR, qm->io_base + SEC_CORE_INT_SOURCE); 563 564 /* enable RAS int */ 565 writel(SEC_RAS_CE_ENB_MSK, qm->io_base + SEC_RAS_CE_REG); 566 writel(SEC_RAS_FE_ENB_MSK, qm->io_base + SEC_RAS_FE_REG); 567 writel(SEC_RAS_NFE_ENB_MSK, qm->io_base + SEC_RAS_NFE_REG); 568 569 /* enable SEC block master OOO when nfe occurs on Kunpeng930 */ 570 sec_master_ooo_ctrl(qm, true); 571 572 /* enable SEC hw error interrupts */ 573 writel(SEC_CORE_INT_ENABLE, qm->io_base + SEC_CORE_INT_MASK); 574 } 575 576 static void sec_hw_error_disable(struct hisi_qm *qm) 577 { 578 /* disable SEC hw error interrupts */ 579 writel(SEC_CORE_INT_DISABLE, qm->io_base + SEC_CORE_INT_MASK); 580 581 /* disable SEC block master OOO when nfe occurs on Kunpeng930 */ 582 sec_master_ooo_ctrl(qm, false); 583 584 /* disable RAS int */ 585 writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_CE_REG); 586 writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_FE_REG); 587 writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_NFE_REG); 588 } 589 590 static u32 sec_clear_enable_read(struct hisi_qm *qm) 591 { 592 return readl(qm->io_base + SEC_CTRL_CNT_CLR_CE) & 593 SEC_CTRL_CNT_CLR_CE_BIT; 594 } 595 596 static int sec_clear_enable_write(struct hisi_qm *qm, u32 val) 597 { 598 u32 tmp; 599 600 if (val != 1 && val) 601 return -EINVAL; 602 603 tmp = (readl(qm->io_base + SEC_CTRL_CNT_CLR_CE) & 604 ~SEC_CTRL_CNT_CLR_CE_BIT) | val; 605 writel(tmp, qm->io_base + SEC_CTRL_CNT_CLR_CE); 606 607 return 0; 608 } 609 610 static ssize_t sec_debug_read(struct file *filp, char __user *buf, 611 size_t count, loff_t *pos) 612 { 613 struct sec_debug_file *file = filp->private_data; 614 char tbuf[SEC_DBGFS_VAL_MAX_LEN]; 615 struct hisi_qm *qm = file->qm; 616 u32 val; 617 int ret; 618 619 ret = hisi_qm_get_dfx_access(qm); 620 if (ret) 621 return ret; 622 623 spin_lock_irq(&file->lock); 624 625 switch (file->index) { 626 case SEC_CLEAR_ENABLE: 627 val = sec_clear_enable_read(qm); 628 break; 629 default: 630 goto err_input; 631 } 632 633 spin_unlock_irq(&file->lock); 634 635 hisi_qm_put_dfx_access(qm); 636 ret = snprintf(tbuf, SEC_DBGFS_VAL_MAX_LEN, "%u\n", val); 637 return simple_read_from_buffer(buf, count, pos, tbuf, ret); 638 639 err_input: 640 spin_unlock_irq(&file->lock); 641 hisi_qm_put_dfx_access(qm); 642 return -EINVAL; 643 } 644 645 static ssize_t sec_debug_write(struct file *filp, const char __user *buf, 646 size_t count, loff_t *pos) 647 { 648 struct sec_debug_file *file = filp->private_data; 649 char tbuf[SEC_DBGFS_VAL_MAX_LEN]; 650 struct hisi_qm *qm = file->qm; 651 unsigned long val; 652 int len, ret; 653 654 if (*pos != 0) 655 return 0; 656 657 if (count >= SEC_DBGFS_VAL_MAX_LEN) 658 return -ENOSPC; 659 660 len = simple_write_to_buffer(tbuf, SEC_DBGFS_VAL_MAX_LEN - 1, 661 pos, buf, count); 662 if (len < 0) 663 return len; 664 665 tbuf[len] = '\0'; 666 if (kstrtoul(tbuf, 0, &val)) 667 return -EFAULT; 668 669 ret = hisi_qm_get_dfx_access(qm); 670 if (ret) 671 return ret; 672 673 spin_lock_irq(&file->lock); 674 675 switch (file->index) { 676 case SEC_CLEAR_ENABLE: 677 ret = sec_clear_enable_write(qm, val); 678 if (ret) 679 goto err_input; 680 break; 681 default: 682 ret = -EINVAL; 683 goto err_input; 684 } 685 686 ret = count; 687 688 err_input: 689 spin_unlock_irq(&file->lock); 690 hisi_qm_put_dfx_access(qm); 691 return ret; 692 } 693 694 static const struct file_operations sec_dbg_fops = { 695 .owner = THIS_MODULE, 696 .open = simple_open, 697 .read = sec_debug_read, 698 .write = sec_debug_write, 699 }; 700 701 static int sec_debugfs_atomic64_get(void *data, u64 *val) 702 { 703 *val = atomic64_read((atomic64_t *)data); 704 705 return 0; 706 } 707 708 static int sec_debugfs_atomic64_set(void *data, u64 val) 709 { 710 if (val) 711 return -EINVAL; 712 713 atomic64_set((atomic64_t *)data, 0); 714 715 return 0; 716 } 717 718 DEFINE_DEBUGFS_ATTRIBUTE(sec_atomic64_ops, sec_debugfs_atomic64_get, 719 sec_debugfs_atomic64_set, "%lld\n"); 720 721 static int sec_regs_show(struct seq_file *s, void *unused) 722 { 723 hisi_qm_regs_dump(s, s->private); 724 725 return 0; 726 } 727 728 DEFINE_SHOW_ATTRIBUTE(sec_regs); 729 730 static int sec_core_debug_init(struct hisi_qm *qm) 731 { 732 struct sec_dev *sec = container_of(qm, struct sec_dev, qm); 733 struct device *dev = &qm->pdev->dev; 734 struct sec_dfx *dfx = &sec->debug.dfx; 735 struct debugfs_regset32 *regset; 736 struct dentry *tmp_d; 737 int i; 738 739 tmp_d = debugfs_create_dir("sec_dfx", qm->debug.debug_root); 740 741 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 742 if (!regset) 743 return -ENOMEM; 744 745 regset->regs = sec_dfx_regs; 746 regset->nregs = ARRAY_SIZE(sec_dfx_regs); 747 regset->base = qm->io_base; 748 regset->dev = dev; 749 750 if (qm->pdev->device == PCI_DEVICE_ID_HUAWEI_SEC_PF) 751 debugfs_create_file("regs", 0444, tmp_d, regset, &sec_regs_fops); 752 753 for (i = 0; i < ARRAY_SIZE(sec_dfx_labels); i++) { 754 atomic64_t *data = (atomic64_t *)((uintptr_t)dfx + 755 sec_dfx_labels[i].offset); 756 debugfs_create_file(sec_dfx_labels[i].name, 0644, 757 tmp_d, data, &sec_atomic64_ops); 758 } 759 760 return 0; 761 } 762 763 static int sec_debug_init(struct hisi_qm *qm) 764 { 765 struct sec_dev *sec = container_of(qm, struct sec_dev, qm); 766 int i; 767 768 if (qm->pdev->device == PCI_DEVICE_ID_HUAWEI_SEC_PF) { 769 for (i = SEC_CLEAR_ENABLE; i < SEC_DEBUG_FILE_NUM; i++) { 770 spin_lock_init(&sec->debug.files[i].lock); 771 sec->debug.files[i].index = i; 772 sec->debug.files[i].qm = qm; 773 774 debugfs_create_file(sec_dbg_file_name[i], 0600, 775 qm->debug.debug_root, 776 sec->debug.files + i, 777 &sec_dbg_fops); 778 } 779 } 780 781 return sec_core_debug_init(qm); 782 } 783 784 static int sec_debugfs_init(struct hisi_qm *qm) 785 { 786 struct device *dev = &qm->pdev->dev; 787 int ret; 788 789 qm->debug.debug_root = debugfs_create_dir(dev_name(dev), 790 sec_debugfs_root); 791 qm->debug.sqe_mask_offset = SEC_SQE_MASK_OFFSET; 792 qm->debug.sqe_mask_len = SEC_SQE_MASK_LEN; 793 hisi_qm_debug_init(qm); 794 795 ret = sec_debug_init(qm); 796 if (ret) 797 goto failed_to_create; 798 799 return 0; 800 801 failed_to_create: 802 debugfs_remove_recursive(sec_debugfs_root); 803 return ret; 804 } 805 806 static void sec_debugfs_exit(struct hisi_qm *qm) 807 { 808 debugfs_remove_recursive(qm->debug.debug_root); 809 } 810 811 static void sec_log_hw_error(struct hisi_qm *qm, u32 err_sts) 812 { 813 const struct sec_hw_error *errs = sec_hw_errors; 814 struct device *dev = &qm->pdev->dev; 815 u32 err_val; 816 817 while (errs->msg) { 818 if (errs->int_msk & err_sts) { 819 dev_err(dev, "%s [error status=0x%x] found\n", 820 errs->msg, errs->int_msk); 821 822 if (SEC_CORE_INT_STATUS_M_ECC & errs->int_msk) { 823 err_val = readl(qm->io_base + 824 SEC_CORE_SRAM_ECC_ERR_INFO); 825 dev_err(dev, "multi ecc sram num=0x%x\n", 826 ((err_val) >> SEC_ECC_NUM) & 827 SEC_ECC_MASH); 828 } 829 } 830 errs++; 831 } 832 } 833 834 static u32 sec_get_hw_err_status(struct hisi_qm *qm) 835 { 836 return readl(qm->io_base + SEC_CORE_INT_STATUS); 837 } 838 839 static void sec_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts) 840 { 841 writel(err_sts, qm->io_base + SEC_CORE_INT_SOURCE); 842 } 843 844 static void sec_open_axi_master_ooo(struct hisi_qm *qm) 845 { 846 u32 val; 847 848 val = readl(qm->io_base + SEC_CONTROL_REG); 849 writel(val & SEC_AXI_SHUTDOWN_DISABLE, qm->io_base + SEC_CONTROL_REG); 850 writel(val | SEC_AXI_SHUTDOWN_ENABLE, qm->io_base + SEC_CONTROL_REG); 851 } 852 853 static void sec_err_info_init(struct hisi_qm *qm) 854 { 855 struct hisi_qm_err_info *err_info = &qm->err_info; 856 857 err_info->ce = QM_BASE_CE; 858 err_info->fe = 0; 859 err_info->ecc_2bits_mask = SEC_CORE_INT_STATUS_M_ECC; 860 err_info->dev_ce_mask = SEC_RAS_CE_ENB_MSK; 861 err_info->msi_wr_port = BIT(0); 862 err_info->acpi_rst = "SRST"; 863 err_info->nfe = QM_BASE_NFE | QM_ACC_DO_TASK_TIMEOUT | 864 QM_ACC_WB_NOT_READY_TIMEOUT; 865 } 866 867 static const struct hisi_qm_err_ini sec_err_ini = { 868 .hw_init = sec_set_user_domain_and_cache, 869 .hw_err_enable = sec_hw_error_enable, 870 .hw_err_disable = sec_hw_error_disable, 871 .get_dev_hw_err_status = sec_get_hw_err_status, 872 .clear_dev_hw_err_status = sec_clear_hw_err_status, 873 .log_dev_hw_err = sec_log_hw_error, 874 .open_axi_master_ooo = sec_open_axi_master_ooo, 875 .open_sva_prefetch = sec_open_sva_prefetch, 876 .close_sva_prefetch = sec_close_sva_prefetch, 877 .err_info_init = sec_err_info_init, 878 }; 879 880 static int sec_pf_probe_init(struct sec_dev *sec) 881 { 882 struct hisi_qm *qm = &sec->qm; 883 int ret; 884 885 qm->err_ini = &sec_err_ini; 886 qm->err_ini->err_info_init(qm); 887 888 ret = sec_set_user_domain_and_cache(qm); 889 if (ret) 890 return ret; 891 892 sec_open_sva_prefetch(qm); 893 hisi_qm_dev_err_init(qm); 894 sec_debug_regs_clear(qm); 895 896 return 0; 897 } 898 899 static int sec_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) 900 { 901 int ret; 902 903 qm->pdev = pdev; 904 qm->ver = pdev->revision; 905 qm->algs = "cipher\ndigest\naead"; 906 qm->mode = uacce_mode; 907 qm->sqe_size = SEC_SQE_SIZE; 908 qm->dev_name = sec_name; 909 910 qm->fun_type = (pdev->device == PCI_DEVICE_ID_HUAWEI_SEC_PF) ? 911 QM_HW_PF : QM_HW_VF; 912 if (qm->fun_type == QM_HW_PF) { 913 qm->qp_base = SEC_PF_DEF_Q_BASE; 914 qm->qp_num = pf_q_num; 915 qm->debug.curr_qm_qp_num = pf_q_num; 916 qm->qm_list = &sec_devices; 917 } else if (qm->fun_type == QM_HW_VF && qm->ver == QM_HW_V1) { 918 /* 919 * have no way to get qm configure in VM in v1 hardware, 920 * so currently force PF to uses SEC_PF_DEF_Q_NUM, and force 921 * to trigger only one VF in v1 hardware. 922 * v2 hardware has no such problem. 923 */ 924 qm->qp_base = SEC_PF_DEF_Q_NUM; 925 qm->qp_num = SEC_QUEUE_NUM_V1 - SEC_PF_DEF_Q_NUM; 926 } 927 928 /* 929 * WQ_HIGHPRI: SEC request must be low delayed, 930 * so need a high priority workqueue. 931 * WQ_UNBOUND: SEC task is likely with long 932 * running CPU intensive workloads. 933 */ 934 qm->wq = alloc_workqueue("%s", WQ_HIGHPRI | WQ_MEM_RECLAIM | 935 WQ_UNBOUND, num_online_cpus(), 936 pci_name(qm->pdev)); 937 if (!qm->wq) { 938 pci_err(qm->pdev, "fail to alloc workqueue\n"); 939 return -ENOMEM; 940 } 941 942 ret = hisi_qm_init(qm); 943 if (ret) 944 destroy_workqueue(qm->wq); 945 946 return ret; 947 } 948 949 static void sec_qm_uninit(struct hisi_qm *qm) 950 { 951 hisi_qm_uninit(qm); 952 } 953 954 static int sec_probe_init(struct sec_dev *sec) 955 { 956 u32 type_rate = SEC_SHAPER_TYPE_RATE; 957 struct hisi_qm *qm = &sec->qm; 958 int ret; 959 960 if (qm->fun_type == QM_HW_PF) { 961 ret = sec_pf_probe_init(sec); 962 if (ret) 963 return ret; 964 /* enable shaper type 0 */ 965 if (qm->ver >= QM_HW_V3) { 966 type_rate |= QM_SHAPER_ENABLE; 967 qm->type_rate = type_rate; 968 } 969 } 970 971 return 0; 972 } 973 974 static void sec_probe_uninit(struct hisi_qm *qm) 975 { 976 hisi_qm_dev_err_uninit(qm); 977 978 destroy_workqueue(qm->wq); 979 } 980 981 static void sec_iommu_used_check(struct sec_dev *sec) 982 { 983 struct iommu_domain *domain; 984 struct device *dev = &sec->qm.pdev->dev; 985 986 domain = iommu_get_domain_for_dev(dev); 987 988 /* Check if iommu is used */ 989 sec->iommu_used = false; 990 if (domain) { 991 if (domain->type & __IOMMU_DOMAIN_PAGING) 992 sec->iommu_used = true; 993 dev_info(dev, "SMMU Opened, the iommu type = %u\n", 994 domain->type); 995 } 996 } 997 998 static int sec_probe(struct pci_dev *pdev, const struct pci_device_id *id) 999 { 1000 struct sec_dev *sec; 1001 struct hisi_qm *qm; 1002 int ret; 1003 1004 sec = devm_kzalloc(&pdev->dev, sizeof(*sec), GFP_KERNEL); 1005 if (!sec) 1006 return -ENOMEM; 1007 1008 qm = &sec->qm; 1009 ret = sec_qm_init(qm, pdev); 1010 if (ret) { 1011 pci_err(pdev, "Failed to init SEC QM (%d)!\n", ret); 1012 return ret; 1013 } 1014 1015 sec->ctx_q_num = ctx_q_num; 1016 sec_iommu_used_check(sec); 1017 1018 ret = sec_probe_init(sec); 1019 if (ret) { 1020 pci_err(pdev, "Failed to probe!\n"); 1021 goto err_qm_uninit; 1022 } 1023 1024 ret = hisi_qm_start(qm); 1025 if (ret) { 1026 pci_err(pdev, "Failed to start sec qm!\n"); 1027 goto err_probe_uninit; 1028 } 1029 1030 ret = sec_debugfs_init(qm); 1031 if (ret) 1032 pci_warn(pdev, "Failed to init debugfs!\n"); 1033 1034 if (qm->qp_num >= ctx_q_num) { 1035 ret = hisi_qm_alg_register(qm, &sec_devices); 1036 if (ret < 0) { 1037 pr_err("Failed to register driver to crypto.\n"); 1038 goto err_qm_stop; 1039 } 1040 } else { 1041 pci_warn(qm->pdev, 1042 "Failed to use kernel mode, qp not enough!\n"); 1043 } 1044 1045 if (qm->uacce) { 1046 ret = uacce_register(qm->uacce); 1047 if (ret) { 1048 pci_err(pdev, "failed to register uacce (%d)!\n", ret); 1049 goto err_alg_unregister; 1050 } 1051 } 1052 1053 if (qm->fun_type == QM_HW_PF && vfs_num) { 1054 ret = hisi_qm_sriov_enable(pdev, vfs_num); 1055 if (ret < 0) 1056 goto err_alg_unregister; 1057 } 1058 1059 hisi_qm_pm_init(qm); 1060 1061 return 0; 1062 1063 err_alg_unregister: 1064 if (qm->qp_num >= ctx_q_num) 1065 hisi_qm_alg_unregister(qm, &sec_devices); 1066 err_qm_stop: 1067 sec_debugfs_exit(qm); 1068 hisi_qm_stop(qm, QM_NORMAL); 1069 err_probe_uninit: 1070 sec_probe_uninit(qm); 1071 err_qm_uninit: 1072 sec_qm_uninit(qm); 1073 return ret; 1074 } 1075 1076 static void sec_remove(struct pci_dev *pdev) 1077 { 1078 struct hisi_qm *qm = pci_get_drvdata(pdev); 1079 1080 hisi_qm_pm_uninit(qm); 1081 hisi_qm_wait_task_finish(qm, &sec_devices); 1082 if (qm->qp_num >= ctx_q_num) 1083 hisi_qm_alg_unregister(qm, &sec_devices); 1084 1085 if (qm->fun_type == QM_HW_PF && qm->vfs_num) 1086 hisi_qm_sriov_disable(pdev, true); 1087 1088 sec_debugfs_exit(qm); 1089 1090 (void)hisi_qm_stop(qm, QM_NORMAL); 1091 1092 if (qm->fun_type == QM_HW_PF) 1093 sec_debug_regs_clear(qm); 1094 1095 sec_probe_uninit(qm); 1096 1097 sec_qm_uninit(qm); 1098 } 1099 1100 static const struct dev_pm_ops sec_pm_ops = { 1101 SET_RUNTIME_PM_OPS(hisi_qm_suspend, hisi_qm_resume, NULL) 1102 }; 1103 1104 static const struct pci_error_handlers sec_err_handler = { 1105 .error_detected = hisi_qm_dev_err_detected, 1106 .slot_reset = hisi_qm_dev_slot_reset, 1107 .reset_prepare = hisi_qm_reset_prepare, 1108 .reset_done = hisi_qm_reset_done, 1109 }; 1110 1111 static struct pci_driver sec_pci_driver = { 1112 .name = "hisi_sec2", 1113 .id_table = sec_dev_ids, 1114 .probe = sec_probe, 1115 .remove = sec_remove, 1116 .err_handler = &sec_err_handler, 1117 .sriov_configure = hisi_qm_sriov_configure, 1118 .shutdown = hisi_qm_dev_shutdown, 1119 .driver.pm = &sec_pm_ops, 1120 }; 1121 1122 struct pci_driver *hisi_sec_get_pf_driver(void) 1123 { 1124 return &sec_pci_driver; 1125 } 1126 EXPORT_SYMBOL_GPL(hisi_sec_get_pf_driver); 1127 1128 static void sec_register_debugfs(void) 1129 { 1130 if (!debugfs_initialized()) 1131 return; 1132 1133 sec_debugfs_root = debugfs_create_dir("hisi_sec2", NULL); 1134 } 1135 1136 static void sec_unregister_debugfs(void) 1137 { 1138 debugfs_remove_recursive(sec_debugfs_root); 1139 } 1140 1141 static int __init sec_init(void) 1142 { 1143 int ret; 1144 1145 hisi_qm_init_list(&sec_devices); 1146 sec_register_debugfs(); 1147 1148 ret = pci_register_driver(&sec_pci_driver); 1149 if (ret < 0) { 1150 sec_unregister_debugfs(); 1151 pr_err("Failed to register pci driver.\n"); 1152 return ret; 1153 } 1154 1155 return 0; 1156 } 1157 1158 static void __exit sec_exit(void) 1159 { 1160 pci_unregister_driver(&sec_pci_driver); 1161 sec_unregister_debugfs(); 1162 } 1163 1164 module_init(sec_init); 1165 module_exit(sec_exit); 1166 1167 MODULE_LICENSE("GPL v2"); 1168 MODULE_AUTHOR("Zaibo Xu <xuzaibo@huawei.com>"); 1169 MODULE_AUTHOR("Longfang Liu <liulongfang@huawei.com>"); 1170 MODULE_AUTHOR("Kai Ye <yekai13@huawei.com>"); 1171 MODULE_AUTHOR("Wei Zhang <zhangwei375@huawei.com>"); 1172 MODULE_DESCRIPTION("Driver for HiSilicon SEC accelerator"); 1173