1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2019 HiSilicon Limited. */ 3 4 #ifndef __HISI_SEC_V2_CRYPTO_H 5 #define __HISI_SEC_V2_CRYPTO_H 6 7 #define SEC_IV_SIZE 24 8 #define SEC_MAX_KEY_SIZE 64 9 #define SEC_COMM_SCENE 0 10 11 enum sec_calg { 12 SEC_CALG_3DES = 0x1, 13 SEC_CALG_AES = 0x2, 14 SEC_CALG_SM4 = 0x3, 15 }; 16 17 enum sec_cmode { 18 SEC_CMODE_ECB = 0x0, 19 SEC_CMODE_CBC = 0x1, 20 SEC_CMODE_CTR = 0x4, 21 SEC_CMODE_XTS = 0x7, 22 }; 23 24 enum sec_ckey_type { 25 SEC_CKEY_128BIT = 0x0, 26 SEC_CKEY_192BIT = 0x1, 27 SEC_CKEY_256BIT = 0x2, 28 SEC_CKEY_3DES_3KEY = 0x1, 29 SEC_CKEY_3DES_2KEY = 0x3, 30 }; 31 32 enum sec_bd_type { 33 SEC_BD_TYPE1 = 0x1, 34 SEC_BD_TYPE2 = 0x2, 35 }; 36 37 enum sec_cipher_dir { 38 SEC_CIPHER_ENC = 0x1, 39 SEC_CIPHER_DEC = 0x2, 40 }; 41 42 enum sec_addr_type { 43 SEC_PBUF = 0x0, 44 SEC_SGL = 0x1, 45 SEC_PRP = 0x2, 46 }; 47 48 struct sec_sqe_type2 { 49 50 /* 51 * mac_len: 0~5 bits 52 * a_key_len: 6~10 bits 53 * a_alg: 11~16 bits 54 */ 55 __le32 mac_key_alg; 56 57 /* 58 * c_icv_len: 0~5 bits 59 * c_width: 6~8 bits 60 * c_key_len: 9~11 bits 61 * c_mode: 12~15 bits 62 */ 63 __le16 icvw_kmode; 64 65 /* c_alg: 0~3 bits */ 66 __u8 c_alg; 67 __u8 rsvd4; 68 69 /* 70 * a_len: 0~23 bits 71 * iv_offset_l: 24~31 bits 72 */ 73 __le32 alen_ivllen; 74 75 /* 76 * c_len: 0~23 bits 77 * iv_offset_h: 24~31 bits 78 */ 79 __le32 clen_ivhlen; 80 81 __le16 auth_src_offset; 82 __le16 cipher_src_offset; 83 __le16 cs_ip_header_offset; 84 __le16 cs_udp_header_offset; 85 __le16 pass_word_len; 86 __le16 dk_len; 87 __u8 salt3; 88 __u8 salt2; 89 __u8 salt1; 90 __u8 salt0; 91 92 __le16 tag; 93 __le16 rsvd5; 94 95 /* 96 * c_pad_type: 0~3 bits 97 * c_pad_len: 4~11 bits 98 * c_pad_data_type: 12~15 bits 99 */ 100 __le16 cph_pad; 101 102 /* c_pad_len_field: 0~1 bits */ 103 __le16 c_pad_len_field; 104 105 106 __le64 long_a_data_len; 107 __le64 a_ivin_addr; 108 __le64 a_key_addr; 109 __le64 mac_addr; 110 __le64 c_ivin_addr; 111 __le64 c_key_addr; 112 113 __le64 data_src_addr; 114 __le64 data_dst_addr; 115 116 /* 117 * done: 0 bit 118 * icv: 1~3 bits 119 * csc: 4~6 bits 120 * flag: 7-10 bits 121 * dif_check: 11~13 bits 122 */ 123 __le16 done_flag; 124 125 __u8 error_type; 126 __u8 warning_type; 127 __u8 mac_i3; 128 __u8 mac_i2; 129 __u8 mac_i1; 130 __u8 mac_i0; 131 __le16 check_sum_i; 132 __u8 tls_pad_len_i; 133 __u8 rsvd12; 134 __le32 counter; 135 }; 136 137 struct sec_sqe { 138 /* 139 * type: 0~3 bits 140 * cipher: 4~5 bits 141 * auth: 6~7 bit s 142 */ 143 __u8 type_cipher_auth; 144 145 /* 146 * seq: 0 bit 147 * de: 1~2 bits 148 * scene: 3~6 bits 149 * src_addr_type: ~7 bit, with sdm_addr_type 0-1 bits 150 */ 151 __u8 sds_sa_type; 152 153 /* 154 * src_addr_type: 0~1 bits, not used now, 155 * if support PRP, set this field, or set zero. 156 * dst_addr_type: 2~4 bits 157 * mac_addr_type: 5~7 bits 158 */ 159 __u8 sdm_addr_type; 160 __u8 rsvd0; 161 162 /* 163 * nonce_len(type2): 0~3 bits 164 * huk(type2): 4 bit 165 * key_s(type2): 5 bit 166 * ci_gen: 6~7 bits 167 */ 168 __u8 huk_key_ci; 169 170 /* 171 * ai_gen: 0~1 bits 172 * a_pad(type2): 2~3 bits 173 * c_s(type2): 4~5 bits 174 */ 175 __u8 ai_apd_cs; 176 177 /* 178 * rhf(type2): 0 bit 179 * c_key_type: 1~2 bits 180 * a_key_type: 3~4 bits 181 * write_frame_len(type2): 5~7 bits 182 */ 183 __u8 rca_key_frm; 184 185 /* 186 * cal_iv_addr_en(type2): 0 bit 187 * tls_up(type2): 1 bit 188 * inveld: 7 bit 189 */ 190 __u8 iv_tls_ld; 191 192 /* Just using type2 BD now */ 193 struct sec_sqe_type2 type2; 194 }; 195 196 int sec_register_to_crypto(void); 197 void sec_unregister_from_crypto(void); 198 #endif 199