1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2019 HiSilicon Limited. */ 3 4 #ifndef __HISI_SEC_V2_CRYPTO_H 5 #define __HISI_SEC_V2_CRYPTO_H 6 7 #define SEC_IV_SIZE 24 8 #define SEC_MAX_KEY_SIZE 64 9 #define SEC_COMM_SCENE 0 10 11 enum sec_calg { 12 SEC_CALG_3DES = 0x1, 13 SEC_CALG_AES = 0x2, 14 SEC_CALG_SM4 = 0x3, 15 }; 16 17 enum sec_hash_alg { 18 SEC_A_HMAC_SHA1 = 0x10, 19 SEC_A_HMAC_SHA256 = 0x11, 20 SEC_A_HMAC_SHA512 = 0x15, 21 }; 22 23 enum sec_mac_len { 24 SEC_HMAC_SHA1_MAC = 20, 25 SEC_HMAC_SHA256_MAC = 32, 26 SEC_HMAC_SHA512_MAC = 64, 27 }; 28 29 enum sec_cmode { 30 SEC_CMODE_ECB = 0x0, 31 SEC_CMODE_CBC = 0x1, 32 SEC_CMODE_CTR = 0x4, 33 SEC_CMODE_XTS = 0x7, 34 }; 35 36 enum sec_ckey_type { 37 SEC_CKEY_128BIT = 0x0, 38 SEC_CKEY_192BIT = 0x1, 39 SEC_CKEY_256BIT = 0x2, 40 SEC_CKEY_3DES_3KEY = 0x1, 41 SEC_CKEY_3DES_2KEY = 0x3, 42 }; 43 44 enum sec_bd_type { 45 SEC_BD_TYPE1 = 0x1, 46 SEC_BD_TYPE2 = 0x2, 47 }; 48 49 enum sec_auth { 50 SEC_NO_AUTH = 0x0, 51 SEC_AUTH_TYPE1 = 0x1, 52 SEC_AUTH_TYPE2 = 0x2, 53 }; 54 55 enum sec_cipher_dir { 56 SEC_CIPHER_ENC = 0x1, 57 SEC_CIPHER_DEC = 0x2, 58 }; 59 60 enum sec_addr_type { 61 SEC_PBUF = 0x0, 62 SEC_SGL = 0x1, 63 SEC_PRP = 0x2, 64 }; 65 66 struct sec_sqe_type2 { 67 /* 68 * mac_len: 0~4 bits 69 * a_key_len: 5~10 bits 70 * a_alg: 11~16 bits 71 */ 72 __le32 mac_key_alg; 73 74 /* 75 * c_icv_len: 0~5 bits 76 * c_width: 6~8 bits 77 * c_key_len: 9~11 bits 78 * c_mode: 12~15 bits 79 */ 80 __le16 icvw_kmode; 81 82 /* c_alg: 0~3 bits */ 83 __u8 c_alg; 84 __u8 rsvd4; 85 86 /* 87 * a_len: 0~23 bits 88 * iv_offset_l: 24~31 bits 89 */ 90 __le32 alen_ivllen; 91 92 /* 93 * c_len: 0~23 bits 94 * iv_offset_h: 24~31 bits 95 */ 96 __le32 clen_ivhlen; 97 98 __le16 auth_src_offset; 99 __le16 cipher_src_offset; 100 __le16 cs_ip_header_offset; 101 __le16 cs_udp_header_offset; 102 __le16 pass_word_len; 103 __le16 dk_len; 104 __u8 salt3; 105 __u8 salt2; 106 __u8 salt1; 107 __u8 salt0; 108 109 __le16 tag; 110 __le16 rsvd5; 111 112 /* 113 * c_pad_type: 0~3 bits 114 * c_pad_len: 4~11 bits 115 * c_pad_data_type: 12~15 bits 116 */ 117 __le16 cph_pad; 118 119 /* c_pad_len_field: 0~1 bits */ 120 __le16 c_pad_len_field; 121 122 __le64 long_a_data_len; 123 __le64 a_ivin_addr; 124 __le64 a_key_addr; 125 __le64 mac_addr; 126 __le64 c_ivin_addr; 127 __le64 c_key_addr; 128 129 __le64 data_src_addr; 130 __le64 data_dst_addr; 131 132 /* 133 * done: 0 bit 134 * icv: 1~3 bits 135 * csc: 4~6 bits 136 * flag: 7-10 bits 137 * dif_check: 11~13 bits 138 */ 139 __le16 done_flag; 140 141 __u8 error_type; 142 __u8 warning_type; 143 __u8 mac_i3; 144 __u8 mac_i2; 145 __u8 mac_i1; 146 __u8 mac_i0; 147 __le16 check_sum_i; 148 __u8 tls_pad_len_i; 149 __u8 rsvd12; 150 __le32 counter; 151 }; 152 153 struct sec_sqe { 154 /* 155 * type: 0~3 bits 156 * cipher: 4~5 bits 157 * auth: 6~7 bit s 158 */ 159 __u8 type_cipher_auth; 160 161 /* 162 * seq: 0 bit 163 * de: 1~2 bits 164 * scene: 3~6 bits 165 * src_addr_type: ~7 bit, with sdm_addr_type 0-1 bits 166 */ 167 __u8 sds_sa_type; 168 169 /* 170 * src_addr_type: 0~1 bits, not used now, 171 * if support PRP, set this field, or set zero. 172 * dst_addr_type: 2~4 bits 173 * mac_addr_type: 5~7 bits 174 */ 175 __u8 sdm_addr_type; 176 __u8 rsvd0; 177 178 /* 179 * nonce_len(type2): 0~3 bits 180 * huk(type2): 4 bit 181 * key_s(type2): 5 bit 182 * ci_gen: 6~7 bits 183 */ 184 __u8 huk_key_ci; 185 186 /* 187 * ai_gen: 0~1 bits 188 * a_pad(type2): 2~3 bits 189 * c_s(type2): 4~5 bits 190 */ 191 __u8 ai_apd_cs; 192 193 /* 194 * rhf(type2): 0 bit 195 * c_key_type: 1~2 bits 196 * a_key_type: 3~4 bits 197 * write_frame_len(type2): 5~7 bits 198 */ 199 __u8 rca_key_frm; 200 201 /* 202 * cal_iv_addr_en(type2): 0 bit 203 * tls_up(type2): 1 bit 204 * inveld: 7 bit 205 */ 206 __u8 iv_tls_ld; 207 208 /* Just using type2 BD now */ 209 struct sec_sqe_type2 type2; 210 }; 211 212 int sec_register_to_crypto(struct hisi_qm *qm); 213 void sec_unregister_from_crypto(struct hisi_qm *qm); 214 #endif 215