1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2016-2017 Hisilicon Limited. */ 3 #include <linux/crypto.h> 4 #include <linux/dma-mapping.h> 5 #include <linux/dmapool.h> 6 #include <linux/module.h> 7 #include <linux/mutex.h> 8 #include <linux/slab.h> 9 10 #include <crypto/aes.h> 11 #include <crypto/algapi.h> 12 #include <crypto/internal/des.h> 13 #include <crypto/skcipher.h> 14 #include <crypto/xts.h> 15 #include <crypto/internal/skcipher.h> 16 17 #include "sec_drv.h" 18 19 #define SEC_MAX_CIPHER_KEY 64 20 #define SEC_REQ_LIMIT SZ_32M 21 22 struct sec_c_alg_cfg { 23 unsigned c_alg : 3; 24 unsigned c_mode : 3; 25 unsigned key_len : 2; 26 unsigned c_width : 2; 27 }; 28 29 static const struct sec_c_alg_cfg sec_c_alg_cfgs[] = { 30 [SEC_C_DES_ECB_64] = { 31 .c_alg = SEC_C_ALG_DES, 32 .c_mode = SEC_C_MODE_ECB, 33 .key_len = SEC_KEY_LEN_DES, 34 }, 35 [SEC_C_DES_CBC_64] = { 36 .c_alg = SEC_C_ALG_DES, 37 .c_mode = SEC_C_MODE_CBC, 38 .key_len = SEC_KEY_LEN_DES, 39 }, 40 [SEC_C_3DES_ECB_192_3KEY] = { 41 .c_alg = SEC_C_ALG_3DES, 42 .c_mode = SEC_C_MODE_ECB, 43 .key_len = SEC_KEY_LEN_3DES_3_KEY, 44 }, 45 [SEC_C_3DES_ECB_192_2KEY] = { 46 .c_alg = SEC_C_ALG_3DES, 47 .c_mode = SEC_C_MODE_ECB, 48 .key_len = SEC_KEY_LEN_3DES_2_KEY, 49 }, 50 [SEC_C_3DES_CBC_192_3KEY] = { 51 .c_alg = SEC_C_ALG_3DES, 52 .c_mode = SEC_C_MODE_CBC, 53 .key_len = SEC_KEY_LEN_3DES_3_KEY, 54 }, 55 [SEC_C_3DES_CBC_192_2KEY] = { 56 .c_alg = SEC_C_ALG_3DES, 57 .c_mode = SEC_C_MODE_CBC, 58 .key_len = SEC_KEY_LEN_3DES_2_KEY, 59 }, 60 [SEC_C_AES_ECB_128] = { 61 .c_alg = SEC_C_ALG_AES, 62 .c_mode = SEC_C_MODE_ECB, 63 .key_len = SEC_KEY_LEN_AES_128, 64 }, 65 [SEC_C_AES_ECB_192] = { 66 .c_alg = SEC_C_ALG_AES, 67 .c_mode = SEC_C_MODE_ECB, 68 .key_len = SEC_KEY_LEN_AES_192, 69 }, 70 [SEC_C_AES_ECB_256] = { 71 .c_alg = SEC_C_ALG_AES, 72 .c_mode = SEC_C_MODE_ECB, 73 .key_len = SEC_KEY_LEN_AES_256, 74 }, 75 [SEC_C_AES_CBC_128] = { 76 .c_alg = SEC_C_ALG_AES, 77 .c_mode = SEC_C_MODE_CBC, 78 .key_len = SEC_KEY_LEN_AES_128, 79 }, 80 [SEC_C_AES_CBC_192] = { 81 .c_alg = SEC_C_ALG_AES, 82 .c_mode = SEC_C_MODE_CBC, 83 .key_len = SEC_KEY_LEN_AES_192, 84 }, 85 [SEC_C_AES_CBC_256] = { 86 .c_alg = SEC_C_ALG_AES, 87 .c_mode = SEC_C_MODE_CBC, 88 .key_len = SEC_KEY_LEN_AES_256, 89 }, 90 [SEC_C_AES_CTR_128] = { 91 .c_alg = SEC_C_ALG_AES, 92 .c_mode = SEC_C_MODE_CTR, 93 .key_len = SEC_KEY_LEN_AES_128, 94 }, 95 [SEC_C_AES_CTR_192] = { 96 .c_alg = SEC_C_ALG_AES, 97 .c_mode = SEC_C_MODE_CTR, 98 .key_len = SEC_KEY_LEN_AES_192, 99 }, 100 [SEC_C_AES_CTR_256] = { 101 .c_alg = SEC_C_ALG_AES, 102 .c_mode = SEC_C_MODE_CTR, 103 .key_len = SEC_KEY_LEN_AES_256, 104 }, 105 [SEC_C_AES_XTS_128] = { 106 .c_alg = SEC_C_ALG_AES, 107 .c_mode = SEC_C_MODE_XTS, 108 .key_len = SEC_KEY_LEN_AES_128, 109 }, 110 [SEC_C_AES_XTS_256] = { 111 .c_alg = SEC_C_ALG_AES, 112 .c_mode = SEC_C_MODE_XTS, 113 .key_len = SEC_KEY_LEN_AES_256, 114 }, 115 [SEC_C_NULL] = { 116 }, 117 }; 118 119 /* 120 * Mutex used to ensure safe operation of reference count of 121 * alg providers 122 */ 123 static DEFINE_MUTEX(algs_lock); 124 static unsigned int active_devs; 125 126 static void sec_alg_skcipher_init_template(struct sec_alg_tfm_ctx *ctx, 127 struct sec_bd_info *req, 128 enum sec_cipher_alg alg) 129 { 130 const struct sec_c_alg_cfg *cfg = &sec_c_alg_cfgs[alg]; 131 132 memset(req, 0, sizeof(*req)); 133 req->w0 |= cfg->c_mode << SEC_BD_W0_C_MODE_S; 134 req->w1 |= cfg->c_alg << SEC_BD_W1_C_ALG_S; 135 req->w3 |= cfg->key_len << SEC_BD_W3_C_KEY_LEN_S; 136 req->w0 |= cfg->c_width << SEC_BD_W0_C_WIDTH_S; 137 138 req->cipher_key_addr_lo = lower_32_bits(ctx->pkey); 139 req->cipher_key_addr_hi = upper_32_bits(ctx->pkey); 140 } 141 142 static void sec_alg_skcipher_init_context(struct crypto_skcipher *atfm, 143 const u8 *key, 144 unsigned int keylen, 145 enum sec_cipher_alg alg) 146 { 147 struct crypto_tfm *tfm = crypto_skcipher_tfm(atfm); 148 struct sec_alg_tfm_ctx *ctx = crypto_tfm_ctx(tfm); 149 150 ctx->cipher_alg = alg; 151 memcpy(ctx->key, key, keylen); 152 sec_alg_skcipher_init_template(ctx, &ctx->req_template, 153 ctx->cipher_alg); 154 } 155 156 static int sec_alloc_and_fill_hw_sgl(struct sec_hw_sgl **sec_sgl, 157 dma_addr_t *psec_sgl, 158 struct scatterlist *sgl, 159 int count, 160 struct sec_dev_info *info) 161 { 162 struct sec_hw_sgl *sgl_current = NULL; 163 struct sec_hw_sgl *sgl_next; 164 dma_addr_t sgl_next_dma; 165 struct scatterlist *sg; 166 int ret, sge_index, i; 167 168 if (!count) 169 return -EINVAL; 170 171 for_each_sg(sgl, sg, count, i) { 172 sge_index = i % SEC_MAX_SGE_NUM; 173 if (sge_index == 0) { 174 sgl_next = dma_pool_zalloc(info->hw_sgl_pool, 175 GFP_KERNEL, &sgl_next_dma); 176 if (!sgl_next) { 177 ret = -ENOMEM; 178 goto err_free_hw_sgls; 179 } 180 181 if (!sgl_current) { /* First one */ 182 *psec_sgl = sgl_next_dma; 183 *sec_sgl = sgl_next; 184 } else { /* Chained */ 185 sgl_current->entry_sum_in_sgl = SEC_MAX_SGE_NUM; 186 sgl_current->next_sgl = sgl_next_dma; 187 sgl_current->next = sgl_next; 188 } 189 sgl_current = sgl_next; 190 } 191 sgl_current->sge_entries[sge_index].buf = sg_dma_address(sg); 192 sgl_current->sge_entries[sge_index].len = sg_dma_len(sg); 193 sgl_current->data_bytes_in_sgl += sg_dma_len(sg); 194 } 195 sgl_current->entry_sum_in_sgl = count % SEC_MAX_SGE_NUM; 196 sgl_current->next_sgl = 0; 197 (*sec_sgl)->entry_sum_in_chain = count; 198 199 return 0; 200 201 err_free_hw_sgls: 202 sgl_current = *sec_sgl; 203 while (sgl_current) { 204 sgl_next = sgl_current->next; 205 dma_pool_free(info->hw_sgl_pool, sgl_current, 206 sgl_current->next_sgl); 207 sgl_current = sgl_next; 208 } 209 *psec_sgl = 0; 210 211 return ret; 212 } 213 214 static void sec_free_hw_sgl(struct sec_hw_sgl *hw_sgl, 215 dma_addr_t psec_sgl, struct sec_dev_info *info) 216 { 217 struct sec_hw_sgl *sgl_current, *sgl_next; 218 219 if (!hw_sgl) 220 return; 221 sgl_current = hw_sgl; 222 while (sgl_current->next) { 223 sgl_next = sgl_current->next; 224 dma_pool_free(info->hw_sgl_pool, sgl_current, 225 sgl_current->next_sgl); 226 sgl_current = sgl_next; 227 } 228 dma_pool_free(info->hw_sgl_pool, hw_sgl, psec_sgl); 229 } 230 231 static int sec_alg_skcipher_setkey(struct crypto_skcipher *tfm, 232 const u8 *key, unsigned int keylen, 233 enum sec_cipher_alg alg) 234 { 235 struct sec_alg_tfm_ctx *ctx = crypto_skcipher_ctx(tfm); 236 struct device *dev = ctx->queue->dev_info->dev; 237 238 mutex_lock(&ctx->lock); 239 if (ctx->key) { 240 /* rekeying */ 241 memset(ctx->key, 0, SEC_MAX_CIPHER_KEY); 242 } else { 243 /* new key */ 244 ctx->key = dma_alloc_coherent(dev, SEC_MAX_CIPHER_KEY, 245 &ctx->pkey, GFP_KERNEL); 246 if (!ctx->key) { 247 mutex_unlock(&ctx->lock); 248 return -ENOMEM; 249 } 250 } 251 mutex_unlock(&ctx->lock); 252 sec_alg_skcipher_init_context(tfm, key, keylen, alg); 253 254 return 0; 255 } 256 257 static int sec_alg_skcipher_setkey_aes_ecb(struct crypto_skcipher *tfm, 258 const u8 *key, unsigned int keylen) 259 { 260 enum sec_cipher_alg alg; 261 262 switch (keylen) { 263 case AES_KEYSIZE_128: 264 alg = SEC_C_AES_ECB_128; 265 break; 266 case AES_KEYSIZE_192: 267 alg = SEC_C_AES_ECB_192; 268 break; 269 case AES_KEYSIZE_256: 270 alg = SEC_C_AES_ECB_256; 271 break; 272 default: 273 return -EINVAL; 274 } 275 276 return sec_alg_skcipher_setkey(tfm, key, keylen, alg); 277 } 278 279 static int sec_alg_skcipher_setkey_aes_cbc(struct crypto_skcipher *tfm, 280 const u8 *key, unsigned int keylen) 281 { 282 enum sec_cipher_alg alg; 283 284 switch (keylen) { 285 case AES_KEYSIZE_128: 286 alg = SEC_C_AES_CBC_128; 287 break; 288 case AES_KEYSIZE_192: 289 alg = SEC_C_AES_CBC_192; 290 break; 291 case AES_KEYSIZE_256: 292 alg = SEC_C_AES_CBC_256; 293 break; 294 default: 295 return -EINVAL; 296 } 297 298 return sec_alg_skcipher_setkey(tfm, key, keylen, alg); 299 } 300 301 static int sec_alg_skcipher_setkey_aes_ctr(struct crypto_skcipher *tfm, 302 const u8 *key, unsigned int keylen) 303 { 304 enum sec_cipher_alg alg; 305 306 switch (keylen) { 307 case AES_KEYSIZE_128: 308 alg = SEC_C_AES_CTR_128; 309 break; 310 case AES_KEYSIZE_192: 311 alg = SEC_C_AES_CTR_192; 312 break; 313 case AES_KEYSIZE_256: 314 alg = SEC_C_AES_CTR_256; 315 break; 316 default: 317 return -EINVAL; 318 } 319 320 return sec_alg_skcipher_setkey(tfm, key, keylen, alg); 321 } 322 323 static int sec_alg_skcipher_setkey_aes_xts(struct crypto_skcipher *tfm, 324 const u8 *key, unsigned int keylen) 325 { 326 enum sec_cipher_alg alg; 327 int ret; 328 329 ret = xts_verify_key(tfm, key, keylen); 330 if (ret) 331 return ret; 332 333 switch (keylen) { 334 case AES_KEYSIZE_128 * 2: 335 alg = SEC_C_AES_XTS_128; 336 break; 337 case AES_KEYSIZE_256 * 2: 338 alg = SEC_C_AES_XTS_256; 339 break; 340 default: 341 return -EINVAL; 342 } 343 344 return sec_alg_skcipher_setkey(tfm, key, keylen, alg); 345 } 346 347 static int sec_alg_skcipher_setkey_des_ecb(struct crypto_skcipher *tfm, 348 const u8 *key, unsigned int keylen) 349 { 350 return verify_skcipher_des_key(tfm, key) ?: 351 sec_alg_skcipher_setkey(tfm, key, keylen, SEC_C_DES_ECB_64); 352 } 353 354 static int sec_alg_skcipher_setkey_des_cbc(struct crypto_skcipher *tfm, 355 const u8 *key, unsigned int keylen) 356 { 357 return verify_skcipher_des_key(tfm, key) ?: 358 sec_alg_skcipher_setkey(tfm, key, keylen, SEC_C_DES_CBC_64); 359 } 360 361 static int sec_alg_skcipher_setkey_3des_ecb(struct crypto_skcipher *tfm, 362 const u8 *key, unsigned int keylen) 363 { 364 return verify_skcipher_des3_key(tfm, key) ?: 365 sec_alg_skcipher_setkey(tfm, key, keylen, 366 SEC_C_3DES_ECB_192_3KEY); 367 } 368 369 static int sec_alg_skcipher_setkey_3des_cbc(struct crypto_skcipher *tfm, 370 const u8 *key, unsigned int keylen) 371 { 372 return verify_skcipher_des3_key(tfm, key) ?: 373 sec_alg_skcipher_setkey(tfm, key, keylen, 374 SEC_C_3DES_CBC_192_3KEY); 375 } 376 377 static void sec_alg_free_el(struct sec_request_el *el, 378 struct sec_dev_info *info) 379 { 380 sec_free_hw_sgl(el->out, el->dma_out, info); 381 sec_free_hw_sgl(el->in, el->dma_in, info); 382 kfree(el->sgl_in); 383 kfree(el->sgl_out); 384 kfree(el); 385 } 386 387 /* queuelock must be held */ 388 static int sec_send_request(struct sec_request *sec_req, struct sec_queue *queue) 389 { 390 struct sec_request_el *el, *temp; 391 int ret = 0; 392 393 mutex_lock(&sec_req->lock); 394 list_for_each_entry_safe(el, temp, &sec_req->elements, head) { 395 /* 396 * Add to hardware queue only under following circumstances 397 * 1) Software and hardware queue empty so no chain dependencies 398 * 2) No dependencies as new IV - (check software queue empty 399 * to maintain order) 400 * 3) No dependencies because the mode does no chaining. 401 * 402 * In other cases first insert onto the software queue which 403 * is then emptied as requests complete 404 */ 405 if (!queue->havesoftqueue || 406 (kfifo_is_empty(&queue->softqueue) && 407 sec_queue_empty(queue))) { 408 ret = sec_queue_send(queue, &el->req, sec_req); 409 if (ret == -EAGAIN) { 410 /* Wait unti we can send then try again */ 411 /* DEAD if here - should not happen */ 412 ret = -EBUSY; 413 goto err_unlock; 414 } 415 } else { 416 kfifo_put(&queue->softqueue, el); 417 } 418 } 419 err_unlock: 420 mutex_unlock(&sec_req->lock); 421 422 return ret; 423 } 424 425 static void sec_skcipher_alg_callback(struct sec_bd_info *sec_resp, 426 struct crypto_async_request *req_base) 427 { 428 struct skcipher_request *skreq = container_of(req_base, 429 struct skcipher_request, 430 base); 431 struct sec_request *sec_req = skcipher_request_ctx(skreq); 432 struct sec_request *backlog_req; 433 struct sec_request_el *sec_req_el, *nextrequest; 434 struct sec_alg_tfm_ctx *ctx = sec_req->tfm_ctx; 435 struct crypto_skcipher *atfm = crypto_skcipher_reqtfm(skreq); 436 struct device *dev = ctx->queue->dev_info->dev; 437 int icv_or_skey_en, ret; 438 bool done; 439 440 sec_req_el = list_first_entry(&sec_req->elements, struct sec_request_el, 441 head); 442 icv_or_skey_en = (sec_resp->w0 & SEC_BD_W0_ICV_OR_SKEY_EN_M) >> 443 SEC_BD_W0_ICV_OR_SKEY_EN_S; 444 if (sec_resp->w1 & SEC_BD_W1_BD_INVALID || icv_or_skey_en == 3) { 445 dev_err(dev, "Got an invalid answer %lu %d\n", 446 sec_resp->w1 & SEC_BD_W1_BD_INVALID, 447 icv_or_skey_en); 448 sec_req->err = -EINVAL; 449 /* 450 * We need to muddle on to avoid getting stuck with elements 451 * on the queue. Error will be reported so requester so 452 * it should be able to handle appropriately. 453 */ 454 } 455 456 mutex_lock(&ctx->queue->queuelock); 457 /* Put the IV in place for chained cases */ 458 switch (ctx->cipher_alg) { 459 case SEC_C_AES_CBC_128: 460 case SEC_C_AES_CBC_192: 461 case SEC_C_AES_CBC_256: 462 if (sec_req_el->req.w0 & SEC_BD_W0_DE) 463 sg_pcopy_to_buffer(sec_req_el->sgl_out, 464 sg_nents(sec_req_el->sgl_out), 465 skreq->iv, 466 crypto_skcipher_ivsize(atfm), 467 sec_req_el->el_length - 468 crypto_skcipher_ivsize(atfm)); 469 else 470 sg_pcopy_to_buffer(sec_req_el->sgl_in, 471 sg_nents(sec_req_el->sgl_in), 472 skreq->iv, 473 crypto_skcipher_ivsize(atfm), 474 sec_req_el->el_length - 475 crypto_skcipher_ivsize(atfm)); 476 /* No need to sync to the device as coherent DMA */ 477 break; 478 case SEC_C_AES_CTR_128: 479 case SEC_C_AES_CTR_192: 480 case SEC_C_AES_CTR_256: 481 crypto_inc(skreq->iv, 16); 482 break; 483 default: 484 /* Do not update */ 485 break; 486 } 487 488 if (ctx->queue->havesoftqueue && 489 !kfifo_is_empty(&ctx->queue->softqueue) && 490 sec_queue_empty(ctx->queue)) { 491 ret = kfifo_get(&ctx->queue->softqueue, &nextrequest); 492 if (ret <= 0) 493 dev_err(dev, 494 "Error getting next element from kfifo %d\n", 495 ret); 496 else 497 /* We know there is space so this cannot fail */ 498 sec_queue_send(ctx->queue, &nextrequest->req, 499 nextrequest->sec_req); 500 } else if (!list_empty(&ctx->backlog)) { 501 /* Need to verify there is room first */ 502 backlog_req = list_first_entry(&ctx->backlog, 503 typeof(*backlog_req), 504 backlog_head); 505 if (sec_queue_can_enqueue(ctx->queue, 506 backlog_req->num_elements) || 507 (ctx->queue->havesoftqueue && 508 kfifo_avail(&ctx->queue->softqueue) > 509 backlog_req->num_elements)) { 510 sec_send_request(backlog_req, ctx->queue); 511 backlog_req->req_base->complete(backlog_req->req_base, 512 -EINPROGRESS); 513 list_del(&backlog_req->backlog_head); 514 } 515 } 516 mutex_unlock(&ctx->queue->queuelock); 517 518 mutex_lock(&sec_req->lock); 519 list_del(&sec_req_el->head); 520 mutex_unlock(&sec_req->lock); 521 sec_alg_free_el(sec_req_el, ctx->queue->dev_info); 522 523 /* 524 * Request is done. 525 * The dance is needed as the lock is freed in the completion 526 */ 527 mutex_lock(&sec_req->lock); 528 done = list_empty(&sec_req->elements); 529 mutex_unlock(&sec_req->lock); 530 if (done) { 531 if (crypto_skcipher_ivsize(atfm)) { 532 dma_unmap_single(dev, sec_req->dma_iv, 533 crypto_skcipher_ivsize(atfm), 534 DMA_TO_DEVICE); 535 } 536 dma_unmap_sg(dev, skreq->src, sec_req->len_in, 537 DMA_BIDIRECTIONAL); 538 if (skreq->src != skreq->dst) 539 dma_unmap_sg(dev, skreq->dst, sec_req->len_out, 540 DMA_BIDIRECTIONAL); 541 skreq->base.complete(&skreq->base, sec_req->err); 542 } 543 } 544 545 void sec_alg_callback(struct sec_bd_info *resp, void *shadow) 546 { 547 struct sec_request *sec_req = shadow; 548 549 sec_req->cb(resp, sec_req->req_base); 550 } 551 552 static int sec_alg_alloc_and_calc_split_sizes(int length, size_t **split_sizes, 553 int *steps) 554 { 555 size_t *sizes; 556 int i; 557 558 /* Split into suitable sized blocks */ 559 *steps = roundup(length, SEC_REQ_LIMIT) / SEC_REQ_LIMIT; 560 sizes = kcalloc(*steps, sizeof(*sizes), GFP_KERNEL); 561 if (!sizes) 562 return -ENOMEM; 563 564 for (i = 0; i < *steps - 1; i++) 565 sizes[i] = SEC_REQ_LIMIT; 566 sizes[*steps - 1] = length - SEC_REQ_LIMIT * (*steps - 1); 567 *split_sizes = sizes; 568 569 return 0; 570 } 571 572 static int sec_map_and_split_sg(struct scatterlist *sgl, size_t *split_sizes, 573 int steps, struct scatterlist ***splits, 574 int **splits_nents, 575 int sgl_len_in, 576 struct device *dev) 577 { 578 int ret, count; 579 580 count = dma_map_sg(dev, sgl, sgl_len_in, DMA_BIDIRECTIONAL); 581 if (!count) 582 return -EINVAL; 583 584 *splits = kcalloc(steps, sizeof(struct scatterlist *), GFP_KERNEL); 585 if (!*splits) { 586 ret = -ENOMEM; 587 goto err_unmap_sg; 588 } 589 *splits_nents = kcalloc(steps, sizeof(int), GFP_KERNEL); 590 if (!*splits_nents) { 591 ret = -ENOMEM; 592 goto err_free_splits; 593 } 594 595 /* output the scatter list before and after this */ 596 ret = sg_split(sgl, count, 0, steps, split_sizes, 597 *splits, *splits_nents, GFP_KERNEL); 598 if (ret) { 599 ret = -ENOMEM; 600 goto err_free_splits_nents; 601 } 602 603 return 0; 604 605 err_free_splits_nents: 606 kfree(*splits_nents); 607 err_free_splits: 608 kfree(*splits); 609 err_unmap_sg: 610 dma_unmap_sg(dev, sgl, sgl_len_in, DMA_BIDIRECTIONAL); 611 612 return ret; 613 } 614 615 /* 616 * Reverses the sec_map_and_split_sg call for messages not yet added to 617 * the queues. 618 */ 619 static void sec_unmap_sg_on_err(struct scatterlist *sgl, int steps, 620 struct scatterlist **splits, int *splits_nents, 621 int sgl_len_in, struct device *dev) 622 { 623 int i; 624 625 for (i = 0; i < steps; i++) 626 kfree(splits[i]); 627 kfree(splits_nents); 628 kfree(splits); 629 630 dma_unmap_sg(dev, sgl, sgl_len_in, DMA_BIDIRECTIONAL); 631 } 632 633 static struct sec_request_el 634 *sec_alg_alloc_and_fill_el(struct sec_bd_info *template, int encrypt, 635 int el_size, bool different_dest, 636 struct scatterlist *sgl_in, int n_ents_in, 637 struct scatterlist *sgl_out, int n_ents_out, 638 struct sec_dev_info *info) 639 { 640 struct sec_request_el *el; 641 struct sec_bd_info *req; 642 int ret; 643 644 el = kzalloc(sizeof(*el), GFP_KERNEL); 645 if (!el) 646 return ERR_PTR(-ENOMEM); 647 el->el_length = el_size; 648 req = &el->req; 649 memcpy(req, template, sizeof(*req)); 650 651 req->w0 &= ~SEC_BD_W0_CIPHER_M; 652 if (encrypt) 653 req->w0 |= SEC_CIPHER_ENCRYPT << SEC_BD_W0_CIPHER_S; 654 else 655 req->w0 |= SEC_CIPHER_DECRYPT << SEC_BD_W0_CIPHER_S; 656 657 req->w0 &= ~SEC_BD_W0_C_GRAN_SIZE_19_16_M; 658 req->w0 |= ((el_size >> 16) << SEC_BD_W0_C_GRAN_SIZE_19_16_S) & 659 SEC_BD_W0_C_GRAN_SIZE_19_16_M; 660 661 req->w0 &= ~SEC_BD_W0_C_GRAN_SIZE_21_20_M; 662 req->w0 |= ((el_size >> 20) << SEC_BD_W0_C_GRAN_SIZE_21_20_S) & 663 SEC_BD_W0_C_GRAN_SIZE_21_20_M; 664 665 /* Writing whole u32 so no need to take care of masking */ 666 req->w2 = ((1 << SEC_BD_W2_GRAN_NUM_S) & SEC_BD_W2_GRAN_NUM_M) | 667 ((el_size << SEC_BD_W2_C_GRAN_SIZE_15_0_S) & 668 SEC_BD_W2_C_GRAN_SIZE_15_0_M); 669 670 req->w3 &= ~SEC_BD_W3_CIPHER_LEN_OFFSET_M; 671 req->w1 |= SEC_BD_W1_ADDR_TYPE; 672 673 el->sgl_in = sgl_in; 674 675 ret = sec_alloc_and_fill_hw_sgl(&el->in, &el->dma_in, el->sgl_in, 676 n_ents_in, info); 677 if (ret) 678 goto err_free_el; 679 680 req->data_addr_lo = lower_32_bits(el->dma_in); 681 req->data_addr_hi = upper_32_bits(el->dma_in); 682 683 if (different_dest) { 684 el->sgl_out = sgl_out; 685 ret = sec_alloc_and_fill_hw_sgl(&el->out, &el->dma_out, 686 el->sgl_out, 687 n_ents_out, info); 688 if (ret) 689 goto err_free_hw_sgl_in; 690 691 req->w0 |= SEC_BD_W0_DE; 692 req->cipher_destin_addr_lo = lower_32_bits(el->dma_out); 693 req->cipher_destin_addr_hi = upper_32_bits(el->dma_out); 694 695 } else { 696 req->w0 &= ~SEC_BD_W0_DE; 697 req->cipher_destin_addr_lo = lower_32_bits(el->dma_in); 698 req->cipher_destin_addr_hi = upper_32_bits(el->dma_in); 699 } 700 701 return el; 702 703 err_free_hw_sgl_in: 704 sec_free_hw_sgl(el->in, el->dma_in, info); 705 err_free_el: 706 kfree(el); 707 708 return ERR_PTR(ret); 709 } 710 711 static int sec_alg_skcipher_crypto(struct skcipher_request *skreq, 712 bool encrypt) 713 { 714 struct crypto_skcipher *atfm = crypto_skcipher_reqtfm(skreq); 715 struct crypto_tfm *tfm = crypto_skcipher_tfm(atfm); 716 struct sec_alg_tfm_ctx *ctx = crypto_tfm_ctx(tfm); 717 struct sec_queue *queue = ctx->queue; 718 struct sec_request *sec_req = skcipher_request_ctx(skreq); 719 struct sec_dev_info *info = queue->dev_info; 720 int i, ret, steps; 721 size_t *split_sizes; 722 struct scatterlist **splits_in; 723 struct scatterlist **splits_out = NULL; 724 int *splits_in_nents; 725 int *splits_out_nents = NULL; 726 struct sec_request_el *el, *temp; 727 bool split = skreq->src != skreq->dst; 728 729 mutex_init(&sec_req->lock); 730 sec_req->req_base = &skreq->base; 731 sec_req->err = 0; 732 /* SGL mapping out here to allow us to break it up as necessary */ 733 sec_req->len_in = sg_nents(skreq->src); 734 735 ret = sec_alg_alloc_and_calc_split_sizes(skreq->cryptlen, &split_sizes, 736 &steps); 737 if (ret) 738 return ret; 739 sec_req->num_elements = steps; 740 ret = sec_map_and_split_sg(skreq->src, split_sizes, steps, &splits_in, 741 &splits_in_nents, sec_req->len_in, 742 info->dev); 743 if (ret) 744 goto err_free_split_sizes; 745 746 if (split) { 747 sec_req->len_out = sg_nents(skreq->dst); 748 ret = sec_map_and_split_sg(skreq->dst, split_sizes, steps, 749 &splits_out, &splits_out_nents, 750 sec_req->len_out, info->dev); 751 if (ret) 752 goto err_unmap_in_sg; 753 } 754 /* Shared info stored in seq_req - applies to all BDs */ 755 sec_req->tfm_ctx = ctx; 756 sec_req->cb = sec_skcipher_alg_callback; 757 INIT_LIST_HEAD(&sec_req->elements); 758 759 /* 760 * Future optimization. 761 * In the chaining case we can't use a dma pool bounce buffer 762 * but in the case where we know there is no chaining we can 763 */ 764 if (crypto_skcipher_ivsize(atfm)) { 765 sec_req->dma_iv = dma_map_single(info->dev, skreq->iv, 766 crypto_skcipher_ivsize(atfm), 767 DMA_TO_DEVICE); 768 if (dma_mapping_error(info->dev, sec_req->dma_iv)) { 769 ret = -ENOMEM; 770 goto err_unmap_out_sg; 771 } 772 } 773 774 /* Set them all up then queue - cleaner error handling. */ 775 for (i = 0; i < steps; i++) { 776 el = sec_alg_alloc_and_fill_el(&ctx->req_template, 777 encrypt ? 1 : 0, 778 split_sizes[i], 779 skreq->src != skreq->dst, 780 splits_in[i], splits_in_nents[i], 781 split ? splits_out[i] : NULL, 782 split ? splits_out_nents[i] : 0, 783 info); 784 if (IS_ERR(el)) { 785 ret = PTR_ERR(el); 786 goto err_free_elements; 787 } 788 el->req.cipher_iv_addr_lo = lower_32_bits(sec_req->dma_iv); 789 el->req.cipher_iv_addr_hi = upper_32_bits(sec_req->dma_iv); 790 el->sec_req = sec_req; 791 list_add_tail(&el->head, &sec_req->elements); 792 } 793 794 /* 795 * Only attempt to queue if the whole lot can fit in the queue - 796 * we can't successfully cleanup after a partial queing so this 797 * must succeed or fail atomically. 798 * 799 * Big hammer test of both software and hardware queues - could be 800 * more refined but this is unlikely to happen so no need. 801 */ 802 803 /* Grab a big lock for a long time to avoid concurrency issues */ 804 mutex_lock(&queue->queuelock); 805 806 /* 807 * Can go on to queue if we have space in either: 808 * 1) The hardware queue and no software queue 809 * 2) The software queue 810 * AND there is nothing in the backlog. If there is backlog we 811 * have to only queue to the backlog queue and return busy. 812 */ 813 if ((!sec_queue_can_enqueue(queue, steps) && 814 (!queue->havesoftqueue || 815 kfifo_avail(&queue->softqueue) > steps)) || 816 !list_empty(&ctx->backlog)) { 817 ret = -EBUSY; 818 if ((skreq->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) { 819 list_add_tail(&sec_req->backlog_head, &ctx->backlog); 820 mutex_unlock(&queue->queuelock); 821 goto out; 822 } 823 824 mutex_unlock(&queue->queuelock); 825 goto err_free_elements; 826 } 827 ret = sec_send_request(sec_req, queue); 828 mutex_unlock(&queue->queuelock); 829 if (ret) 830 goto err_free_elements; 831 832 ret = -EINPROGRESS; 833 out: 834 /* Cleanup - all elements in pointer arrays have been copied */ 835 kfree(splits_in_nents); 836 kfree(splits_in); 837 kfree(splits_out_nents); 838 kfree(splits_out); 839 kfree(split_sizes); 840 return ret; 841 842 err_free_elements: 843 list_for_each_entry_safe(el, temp, &sec_req->elements, head) { 844 list_del(&el->head); 845 sec_alg_free_el(el, info); 846 } 847 if (crypto_skcipher_ivsize(atfm)) 848 dma_unmap_single(info->dev, sec_req->dma_iv, 849 crypto_skcipher_ivsize(atfm), 850 DMA_BIDIRECTIONAL); 851 err_unmap_out_sg: 852 if (split) 853 sec_unmap_sg_on_err(skreq->dst, steps, splits_out, 854 splits_out_nents, sec_req->len_out, 855 info->dev); 856 err_unmap_in_sg: 857 sec_unmap_sg_on_err(skreq->src, steps, splits_in, splits_in_nents, 858 sec_req->len_in, info->dev); 859 err_free_split_sizes: 860 kfree(split_sizes); 861 862 return ret; 863 } 864 865 static int sec_alg_skcipher_encrypt(struct skcipher_request *req) 866 { 867 return sec_alg_skcipher_crypto(req, true); 868 } 869 870 static int sec_alg_skcipher_decrypt(struct skcipher_request *req) 871 { 872 return sec_alg_skcipher_crypto(req, false); 873 } 874 875 static int sec_alg_skcipher_init(struct crypto_skcipher *tfm) 876 { 877 struct sec_alg_tfm_ctx *ctx = crypto_skcipher_ctx(tfm); 878 879 mutex_init(&ctx->lock); 880 INIT_LIST_HEAD(&ctx->backlog); 881 crypto_skcipher_set_reqsize(tfm, sizeof(struct sec_request)); 882 883 ctx->queue = sec_queue_alloc_start_safe(); 884 if (IS_ERR(ctx->queue)) 885 return PTR_ERR(ctx->queue); 886 887 mutex_init(&ctx->queue->queuelock); 888 ctx->queue->havesoftqueue = false; 889 890 return 0; 891 } 892 893 static void sec_alg_skcipher_exit(struct crypto_skcipher *tfm) 894 { 895 struct sec_alg_tfm_ctx *ctx = crypto_skcipher_ctx(tfm); 896 struct device *dev = ctx->queue->dev_info->dev; 897 898 if (ctx->key) { 899 memzero_explicit(ctx->key, SEC_MAX_CIPHER_KEY); 900 dma_free_coherent(dev, SEC_MAX_CIPHER_KEY, ctx->key, 901 ctx->pkey); 902 } 903 sec_queue_stop_release(ctx->queue); 904 } 905 906 static int sec_alg_skcipher_init_with_queue(struct crypto_skcipher *tfm) 907 { 908 struct sec_alg_tfm_ctx *ctx = crypto_skcipher_ctx(tfm); 909 int ret; 910 911 ret = sec_alg_skcipher_init(tfm); 912 if (ret) 913 return ret; 914 915 INIT_KFIFO(ctx->queue->softqueue); 916 ret = kfifo_alloc(&ctx->queue->softqueue, 512, GFP_KERNEL); 917 if (ret) { 918 sec_alg_skcipher_exit(tfm); 919 return ret; 920 } 921 ctx->queue->havesoftqueue = true; 922 923 return 0; 924 } 925 926 static void sec_alg_skcipher_exit_with_queue(struct crypto_skcipher *tfm) 927 { 928 struct sec_alg_tfm_ctx *ctx = crypto_skcipher_ctx(tfm); 929 930 kfifo_free(&ctx->queue->softqueue); 931 sec_alg_skcipher_exit(tfm); 932 } 933 934 static struct skcipher_alg sec_algs[] = { 935 { 936 .base = { 937 .cra_name = "ecb(aes)", 938 .cra_driver_name = "hisi_sec_aes_ecb", 939 .cra_priority = 4001, 940 .cra_flags = CRYPTO_ALG_ASYNC, 941 .cra_blocksize = AES_BLOCK_SIZE, 942 .cra_ctxsize = sizeof(struct sec_alg_tfm_ctx), 943 .cra_alignmask = 0, 944 .cra_module = THIS_MODULE, 945 }, 946 .init = sec_alg_skcipher_init, 947 .exit = sec_alg_skcipher_exit, 948 .setkey = sec_alg_skcipher_setkey_aes_ecb, 949 .decrypt = sec_alg_skcipher_decrypt, 950 .encrypt = sec_alg_skcipher_encrypt, 951 .min_keysize = AES_MIN_KEY_SIZE, 952 .max_keysize = AES_MAX_KEY_SIZE, 953 .ivsize = 0, 954 }, { 955 .base = { 956 .cra_name = "cbc(aes)", 957 .cra_driver_name = "hisi_sec_aes_cbc", 958 .cra_priority = 4001, 959 .cra_flags = CRYPTO_ALG_ASYNC, 960 .cra_blocksize = AES_BLOCK_SIZE, 961 .cra_ctxsize = sizeof(struct sec_alg_tfm_ctx), 962 .cra_alignmask = 0, 963 .cra_module = THIS_MODULE, 964 }, 965 .init = sec_alg_skcipher_init_with_queue, 966 .exit = sec_alg_skcipher_exit_with_queue, 967 .setkey = sec_alg_skcipher_setkey_aes_cbc, 968 .decrypt = sec_alg_skcipher_decrypt, 969 .encrypt = sec_alg_skcipher_encrypt, 970 .min_keysize = AES_MIN_KEY_SIZE, 971 .max_keysize = AES_MAX_KEY_SIZE, 972 .ivsize = AES_BLOCK_SIZE, 973 }, { 974 .base = { 975 .cra_name = "ctr(aes)", 976 .cra_driver_name = "hisi_sec_aes_ctr", 977 .cra_priority = 4001, 978 .cra_flags = CRYPTO_ALG_ASYNC, 979 .cra_blocksize = AES_BLOCK_SIZE, 980 .cra_ctxsize = sizeof(struct sec_alg_tfm_ctx), 981 .cra_alignmask = 0, 982 .cra_module = THIS_MODULE, 983 }, 984 .init = sec_alg_skcipher_init_with_queue, 985 .exit = sec_alg_skcipher_exit_with_queue, 986 .setkey = sec_alg_skcipher_setkey_aes_ctr, 987 .decrypt = sec_alg_skcipher_decrypt, 988 .encrypt = sec_alg_skcipher_encrypt, 989 .min_keysize = AES_MIN_KEY_SIZE, 990 .max_keysize = AES_MAX_KEY_SIZE, 991 .ivsize = AES_BLOCK_SIZE, 992 }, { 993 .base = { 994 .cra_name = "xts(aes)", 995 .cra_driver_name = "hisi_sec_aes_xts", 996 .cra_priority = 4001, 997 .cra_flags = CRYPTO_ALG_ASYNC, 998 .cra_blocksize = AES_BLOCK_SIZE, 999 .cra_ctxsize = sizeof(struct sec_alg_tfm_ctx), 1000 .cra_alignmask = 0, 1001 .cra_module = THIS_MODULE, 1002 }, 1003 .init = sec_alg_skcipher_init, 1004 .exit = sec_alg_skcipher_exit, 1005 .setkey = sec_alg_skcipher_setkey_aes_xts, 1006 .decrypt = sec_alg_skcipher_decrypt, 1007 .encrypt = sec_alg_skcipher_encrypt, 1008 .min_keysize = 2 * AES_MIN_KEY_SIZE, 1009 .max_keysize = 2 * AES_MAX_KEY_SIZE, 1010 .ivsize = AES_BLOCK_SIZE, 1011 }, { 1012 /* Unable to find any test vectors so untested */ 1013 .base = { 1014 .cra_name = "ecb(des)", 1015 .cra_driver_name = "hisi_sec_des_ecb", 1016 .cra_priority = 4001, 1017 .cra_flags = CRYPTO_ALG_ASYNC, 1018 .cra_blocksize = DES_BLOCK_SIZE, 1019 .cra_ctxsize = sizeof(struct sec_alg_tfm_ctx), 1020 .cra_alignmask = 0, 1021 .cra_module = THIS_MODULE, 1022 }, 1023 .init = sec_alg_skcipher_init, 1024 .exit = sec_alg_skcipher_exit, 1025 .setkey = sec_alg_skcipher_setkey_des_ecb, 1026 .decrypt = sec_alg_skcipher_decrypt, 1027 .encrypt = sec_alg_skcipher_encrypt, 1028 .min_keysize = DES_KEY_SIZE, 1029 .max_keysize = DES_KEY_SIZE, 1030 .ivsize = 0, 1031 }, { 1032 .base = { 1033 .cra_name = "cbc(des)", 1034 .cra_driver_name = "hisi_sec_des_cbc", 1035 .cra_priority = 4001, 1036 .cra_flags = CRYPTO_ALG_ASYNC, 1037 .cra_blocksize = DES_BLOCK_SIZE, 1038 .cra_ctxsize = sizeof(struct sec_alg_tfm_ctx), 1039 .cra_alignmask = 0, 1040 .cra_module = THIS_MODULE, 1041 }, 1042 .init = sec_alg_skcipher_init_with_queue, 1043 .exit = sec_alg_skcipher_exit_with_queue, 1044 .setkey = sec_alg_skcipher_setkey_des_cbc, 1045 .decrypt = sec_alg_skcipher_decrypt, 1046 .encrypt = sec_alg_skcipher_encrypt, 1047 .min_keysize = DES_KEY_SIZE, 1048 .max_keysize = DES_KEY_SIZE, 1049 .ivsize = DES_BLOCK_SIZE, 1050 }, { 1051 .base = { 1052 .cra_name = "cbc(des3_ede)", 1053 .cra_driver_name = "hisi_sec_3des_cbc", 1054 .cra_priority = 4001, 1055 .cra_flags = CRYPTO_ALG_ASYNC, 1056 .cra_blocksize = DES3_EDE_BLOCK_SIZE, 1057 .cra_ctxsize = sizeof(struct sec_alg_tfm_ctx), 1058 .cra_alignmask = 0, 1059 .cra_module = THIS_MODULE, 1060 }, 1061 .init = sec_alg_skcipher_init_with_queue, 1062 .exit = sec_alg_skcipher_exit_with_queue, 1063 .setkey = sec_alg_skcipher_setkey_3des_cbc, 1064 .decrypt = sec_alg_skcipher_decrypt, 1065 .encrypt = sec_alg_skcipher_encrypt, 1066 .min_keysize = DES3_EDE_KEY_SIZE, 1067 .max_keysize = DES3_EDE_KEY_SIZE, 1068 .ivsize = DES3_EDE_BLOCK_SIZE, 1069 }, { 1070 .base = { 1071 .cra_name = "ecb(des3_ede)", 1072 .cra_driver_name = "hisi_sec_3des_ecb", 1073 .cra_priority = 4001, 1074 .cra_flags = CRYPTO_ALG_ASYNC, 1075 .cra_blocksize = DES3_EDE_BLOCK_SIZE, 1076 .cra_ctxsize = sizeof(struct sec_alg_tfm_ctx), 1077 .cra_alignmask = 0, 1078 .cra_module = THIS_MODULE, 1079 }, 1080 .init = sec_alg_skcipher_init, 1081 .exit = sec_alg_skcipher_exit, 1082 .setkey = sec_alg_skcipher_setkey_3des_ecb, 1083 .decrypt = sec_alg_skcipher_decrypt, 1084 .encrypt = sec_alg_skcipher_encrypt, 1085 .min_keysize = DES3_EDE_KEY_SIZE, 1086 .max_keysize = DES3_EDE_KEY_SIZE, 1087 .ivsize = 0, 1088 } 1089 }; 1090 1091 int sec_algs_register(void) 1092 { 1093 int ret = 0; 1094 1095 mutex_lock(&algs_lock); 1096 if (++active_devs != 1) 1097 goto unlock; 1098 1099 ret = crypto_register_skciphers(sec_algs, ARRAY_SIZE(sec_algs)); 1100 if (ret) 1101 --active_devs; 1102 unlock: 1103 mutex_unlock(&algs_lock); 1104 1105 return ret; 1106 } 1107 1108 void sec_algs_unregister(void) 1109 { 1110 mutex_lock(&algs_lock); 1111 if (--active_devs != 0) 1112 goto unlock; 1113 crypto_unregister_skciphers(sec_algs, ARRAY_SIZE(sec_algs)); 1114 1115 unlock: 1116 mutex_unlock(&algs_lock); 1117 } 1118