1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2019 HiSilicon Limited. */ 3 #include <asm/page.h> 4 #include <linux/bitmap.h> 5 #include <linux/debugfs.h> 6 #include <linux/dma-mapping.h> 7 #include <linux/io.h> 8 #include <linux/irqreturn.h> 9 #include <linux/log2.h> 10 #include <linux/seq_file.h> 11 #include <linux/slab.h> 12 #include "qm.h" 13 14 /* eq/aeq irq enable */ 15 #define QM_VF_AEQ_INT_SOURCE 0x0 16 #define QM_VF_AEQ_INT_MASK 0x4 17 #define QM_VF_EQ_INT_SOURCE 0x8 18 #define QM_VF_EQ_INT_MASK 0xc 19 #define QM_IRQ_NUM_V1 1 20 #define QM_IRQ_NUM_PF_V2 4 21 #define QM_IRQ_NUM_VF_V2 2 22 23 #define QM_EQ_EVENT_IRQ_VECTOR 0 24 #define QM_AEQ_EVENT_IRQ_VECTOR 1 25 #define QM_ABNORMAL_EVENT_IRQ_VECTOR 3 26 27 /* mailbox */ 28 #define QM_MB_CMD_SQC 0x0 29 #define QM_MB_CMD_CQC 0x1 30 #define QM_MB_CMD_EQC 0x2 31 #define QM_MB_CMD_AEQC 0x3 32 #define QM_MB_CMD_SQC_BT 0x4 33 #define QM_MB_CMD_CQC_BT 0x5 34 #define QM_MB_CMD_SQC_VFT_V2 0x6 35 36 #define QM_MB_CMD_SEND_BASE 0x300 37 #define QM_MB_EVENT_SHIFT 8 38 #define QM_MB_BUSY_SHIFT 13 39 #define QM_MB_OP_SHIFT 14 40 #define QM_MB_CMD_DATA_ADDR_L 0x304 41 #define QM_MB_CMD_DATA_ADDR_H 0x308 42 43 /* sqc shift */ 44 #define QM_SQ_HOP_NUM_SHIFT 0 45 #define QM_SQ_PAGE_SIZE_SHIFT 4 46 #define QM_SQ_BUF_SIZE_SHIFT 8 47 #define QM_SQ_SQE_SIZE_SHIFT 12 48 #define QM_SQ_PRIORITY_SHIFT 0 49 #define QM_SQ_ORDERS_SHIFT 4 50 #define QM_SQ_TYPE_SHIFT 8 51 52 #define QM_SQ_TYPE_MASK GENMASK(3, 0) 53 54 /* cqc shift */ 55 #define QM_CQ_HOP_NUM_SHIFT 0 56 #define QM_CQ_PAGE_SIZE_SHIFT 4 57 #define QM_CQ_BUF_SIZE_SHIFT 8 58 #define QM_CQ_CQE_SIZE_SHIFT 12 59 #define QM_CQ_PHASE_SHIFT 0 60 #define QM_CQ_FLAG_SHIFT 1 61 62 #define QM_CQE_PHASE(cqe) (le16_to_cpu((cqe)->w7) & 0x1) 63 #define QM_QC_CQE_SIZE 4 64 65 /* eqc shift */ 66 #define QM_EQE_AEQE_SIZE (2UL << 12) 67 #define QM_EQC_PHASE_SHIFT 16 68 69 #define QM_EQE_PHASE(eqe) ((le32_to_cpu((eqe)->dw0) >> 16) & 0x1) 70 #define QM_EQE_CQN_MASK GENMASK(15, 0) 71 72 #define QM_AEQE_PHASE(aeqe) ((le32_to_cpu((aeqe)->dw0) >> 16) & 0x1) 73 #define QM_AEQE_TYPE_SHIFT 17 74 75 #define QM_DOORBELL_CMD_SQ 0 76 #define QM_DOORBELL_CMD_CQ 1 77 #define QM_DOORBELL_CMD_EQ 2 78 #define QM_DOORBELL_CMD_AEQ 3 79 80 #define QM_DOORBELL_BASE_V1 0x340 81 #define QM_DB_CMD_SHIFT_V1 16 82 #define QM_DB_INDEX_SHIFT_V1 32 83 #define QM_DB_PRIORITY_SHIFT_V1 48 84 #define QM_DOORBELL_SQ_CQ_BASE_V2 0x1000 85 #define QM_DOORBELL_EQ_AEQ_BASE_V2 0x2000 86 #define QM_DB_CMD_SHIFT_V2 12 87 #define QM_DB_RAND_SHIFT_V2 16 88 #define QM_DB_INDEX_SHIFT_V2 32 89 #define QM_DB_PRIORITY_SHIFT_V2 48 90 91 #define QM_MEM_START_INIT 0x100040 92 #define QM_MEM_INIT_DONE 0x100044 93 #define QM_VFT_CFG_RDY 0x10006c 94 #define QM_VFT_CFG_OP_WR 0x100058 95 #define QM_VFT_CFG_TYPE 0x10005c 96 #define QM_SQC_VFT 0x0 97 #define QM_CQC_VFT 0x1 98 #define QM_VFT_CFG 0x100060 99 #define QM_VFT_CFG_OP_ENABLE 0x100054 100 101 #define QM_VFT_CFG_DATA_L 0x100064 102 #define QM_VFT_CFG_DATA_H 0x100068 103 #define QM_SQC_VFT_BUF_SIZE (7ULL << 8) 104 #define QM_SQC_VFT_SQC_SIZE (5ULL << 12) 105 #define QM_SQC_VFT_INDEX_NUMBER (1ULL << 16) 106 #define QM_SQC_VFT_START_SQN_SHIFT 28 107 #define QM_SQC_VFT_VALID (1ULL << 44) 108 #define QM_SQC_VFT_SQN_SHIFT 45 109 #define QM_CQC_VFT_BUF_SIZE (7ULL << 8) 110 #define QM_CQC_VFT_SQC_SIZE (5ULL << 12) 111 #define QM_CQC_VFT_INDEX_NUMBER (1ULL << 16) 112 #define QM_CQC_VFT_VALID (1ULL << 28) 113 114 #define QM_SQC_VFT_BASE_SHIFT_V2 28 115 #define QM_SQC_VFT_BASE_MASK_V2 GENMASK(5, 0) 116 #define QM_SQC_VFT_NUM_SHIFT_V2 45 117 #define QM_SQC_VFT_NUM_MASK_v2 GENMASK(9, 0) 118 119 #define QM_DFX_CNT_CLR_CE 0x100118 120 121 #define QM_ABNORMAL_INT_SOURCE 0x100000 122 #define QM_ABNORMAL_INT_MASK 0x100004 123 #define QM_ABNORMAL_INT_MASK_VALUE 0x1fff 124 #define QM_ABNORMAL_INT_STATUS 0x100008 125 #define QM_ABNORMAL_INF00 0x100010 126 #define QM_FIFO_OVERFLOW_TYPE 0xc0 127 #define QM_FIFO_OVERFLOW_TYPE_SHIFT 6 128 #define QM_FIFO_OVERFLOW_VF 0x3f 129 #define QM_ABNORMAL_INF01 0x100014 130 #define QM_DB_TIMEOUT_TYPE 0xc0 131 #define QM_DB_TIMEOUT_TYPE_SHIFT 6 132 #define QM_DB_TIMEOUT_VF 0x3f 133 #define QM_RAS_CE_ENABLE 0x1000ec 134 #define QM_RAS_FE_ENABLE 0x1000f0 135 #define QM_RAS_NFE_ENABLE 0x1000f4 136 #define QM_RAS_CE_THRESHOLD 0x1000f8 137 #define QM_RAS_CE_TIMES_PER_IRQ 1 138 #define QM_RAS_MSI_INT_SEL 0x1040f4 139 140 #define QM_CACHE_WB_START 0x204 141 #define QM_CACHE_WB_DONE 0x208 142 143 #define PCI_BAR_2 2 144 #define QM_SQE_DATA_ALIGN_MASK GENMASK(6, 0) 145 #define QMC_ALIGN(sz) ALIGN(sz, 32) 146 147 #define QM_DBG_TMP_BUF_LEN 22 148 149 #define QM_MK_CQC_DW3_V1(hop_num, pg_sz, buf_sz, cqe_sz) \ 150 (((hop_num) << QM_CQ_HOP_NUM_SHIFT) | \ 151 ((pg_sz) << QM_CQ_PAGE_SIZE_SHIFT) | \ 152 ((buf_sz) << QM_CQ_BUF_SIZE_SHIFT) | \ 153 ((cqe_sz) << QM_CQ_CQE_SIZE_SHIFT)) 154 155 #define QM_MK_CQC_DW3_V2(cqe_sz) \ 156 ((QM_Q_DEPTH - 1) | ((cqe_sz) << QM_CQ_CQE_SIZE_SHIFT)) 157 158 #define QM_MK_SQC_W13(priority, orders, alg_type) \ 159 (((priority) << QM_SQ_PRIORITY_SHIFT) | \ 160 ((orders) << QM_SQ_ORDERS_SHIFT) | \ 161 (((alg_type) & QM_SQ_TYPE_MASK) << QM_SQ_TYPE_SHIFT)) 162 163 #define QM_MK_SQC_DW3_V1(hop_num, pg_sz, buf_sz, sqe_sz) \ 164 (((hop_num) << QM_SQ_HOP_NUM_SHIFT) | \ 165 ((pg_sz) << QM_SQ_PAGE_SIZE_SHIFT) | \ 166 ((buf_sz) << QM_SQ_BUF_SIZE_SHIFT) | \ 167 ((u32)ilog2(sqe_sz) << QM_SQ_SQE_SIZE_SHIFT)) 168 169 #define QM_MK_SQC_DW3_V2(sqe_sz) \ 170 ((QM_Q_DEPTH - 1) | ((u32)ilog2(sqe_sz) << QM_SQ_SQE_SIZE_SHIFT)) 171 172 #define INIT_QC_COMMON(qc, base, pasid) do { \ 173 (qc)->head = 0; \ 174 (qc)->tail = 0; \ 175 (qc)->base_l = cpu_to_le32(lower_32_bits(base)); \ 176 (qc)->base_h = cpu_to_le32(upper_32_bits(base)); \ 177 (qc)->dw3 = 0; \ 178 (qc)->w8 = 0; \ 179 (qc)->rsvd0 = 0; \ 180 (qc)->pasid = cpu_to_le16(pasid); \ 181 (qc)->w11 = 0; \ 182 (qc)->rsvd1 = 0; \ 183 } while (0) 184 185 enum vft_type { 186 SQC_VFT = 0, 187 CQC_VFT, 188 }; 189 190 struct qm_cqe { 191 __le32 rsvd0; 192 __le16 cmd_id; 193 __le16 rsvd1; 194 __le16 sq_head; 195 __le16 sq_num; 196 __le16 rsvd2; 197 __le16 w7; 198 }; 199 200 struct qm_eqe { 201 __le32 dw0; 202 }; 203 204 struct qm_aeqe { 205 __le32 dw0; 206 }; 207 208 struct qm_sqc { 209 __le16 head; 210 __le16 tail; 211 __le32 base_l; 212 __le32 base_h; 213 __le32 dw3; 214 __le16 w8; 215 __le16 rsvd0; 216 __le16 pasid; 217 __le16 w11; 218 __le16 cq_num; 219 __le16 w13; 220 __le32 rsvd1; 221 }; 222 223 struct qm_cqc { 224 __le16 head; 225 __le16 tail; 226 __le32 base_l; 227 __le32 base_h; 228 __le32 dw3; 229 __le16 w8; 230 __le16 rsvd0; 231 __le16 pasid; 232 __le16 w11; 233 __le32 dw6; 234 __le32 rsvd1; 235 }; 236 237 struct qm_eqc { 238 __le16 head; 239 __le16 tail; 240 __le32 base_l; 241 __le32 base_h; 242 __le32 dw3; 243 __le32 rsvd[2]; 244 __le32 dw6; 245 }; 246 247 struct qm_aeqc { 248 __le16 head; 249 __le16 tail; 250 __le32 base_l; 251 __le32 base_h; 252 __le32 dw3; 253 __le32 rsvd[2]; 254 __le32 dw6; 255 }; 256 257 struct qm_mailbox { 258 __le16 w0; 259 __le16 queue_num; 260 __le32 base_l; 261 __le32 base_h; 262 __le32 rsvd; 263 }; 264 265 struct qm_doorbell { 266 __le16 queue_num; 267 __le16 cmd; 268 __le16 index; 269 __le16 priority; 270 }; 271 272 struct hisi_qm_hw_ops { 273 int (*get_vft)(struct hisi_qm *qm, u32 *base, u32 *number); 274 void (*qm_db)(struct hisi_qm *qm, u16 qn, 275 u8 cmd, u16 index, u8 priority); 276 u32 (*get_irq_num)(struct hisi_qm *qm); 277 int (*debug_init)(struct hisi_qm *qm); 278 void (*hw_error_init)(struct hisi_qm *qm, u32 ce, u32 nfe, u32 fe, 279 u32 msi); 280 pci_ers_result_t (*hw_error_handle)(struct hisi_qm *qm); 281 }; 282 283 static const char * const qm_debug_file_name[] = { 284 [CURRENT_Q] = "current_q", 285 [CLEAR_ENABLE] = "clear_enable", 286 }; 287 288 struct hisi_qm_hw_error { 289 u32 int_msk; 290 const char *msg; 291 }; 292 293 static const struct hisi_qm_hw_error qm_hw_error[] = { 294 { .int_msk = BIT(0), .msg = "qm_axi_rresp" }, 295 { .int_msk = BIT(1), .msg = "qm_axi_bresp" }, 296 { .int_msk = BIT(2), .msg = "qm_ecc_mbit" }, 297 { .int_msk = BIT(3), .msg = "qm_ecc_1bit" }, 298 { .int_msk = BIT(4), .msg = "qm_acc_get_task_timeout" }, 299 { .int_msk = BIT(5), .msg = "qm_acc_do_task_timeout" }, 300 { .int_msk = BIT(6), .msg = "qm_acc_wb_not_ready_timeout" }, 301 { .int_msk = BIT(7), .msg = "qm_sq_cq_vf_invalid" }, 302 { .int_msk = BIT(8), .msg = "qm_cq_vf_invalid" }, 303 { .int_msk = BIT(9), .msg = "qm_sq_vf_invalid" }, 304 { .int_msk = BIT(10), .msg = "qm_db_timeout" }, 305 { .int_msk = BIT(11), .msg = "qm_of_fifo_of" }, 306 { .int_msk = BIT(12), .msg = "qm_db_random_invalid" }, 307 { /* sentinel */ } 308 }; 309 310 static const char * const qm_db_timeout[] = { 311 "sq", "cq", "eq", "aeq", 312 }; 313 314 static const char * const qm_fifo_overflow[] = { 315 "cq", "eq", "aeq", 316 }; 317 318 /* return 0 mailbox ready, -ETIMEDOUT hardware timeout */ 319 static int qm_wait_mb_ready(struct hisi_qm *qm) 320 { 321 u32 val; 322 323 return readl_relaxed_poll_timeout(qm->io_base + QM_MB_CMD_SEND_BASE, 324 val, !((val >> QM_MB_BUSY_SHIFT) & 325 0x1), 10, 1000); 326 } 327 328 /* 128 bit should be written to hardware at one time to trigger a mailbox */ 329 static void qm_mb_write(struct hisi_qm *qm, const void *src) 330 { 331 void __iomem *fun_base = qm->io_base + QM_MB_CMD_SEND_BASE; 332 unsigned long tmp0 = 0, tmp1 = 0; 333 334 if (!IS_ENABLED(CONFIG_ARM64)) { 335 memcpy_toio(fun_base, src, 16); 336 wmb(); 337 return; 338 } 339 340 asm volatile("ldp %0, %1, %3\n" 341 "stp %0, %1, %2\n" 342 "dsb sy\n" 343 : "=&r" (tmp0), 344 "=&r" (tmp1), 345 "+Q" (*((char __iomem *)fun_base)) 346 : "Q" (*((char *)src)) 347 : "memory"); 348 } 349 350 static int qm_mb(struct hisi_qm *qm, u8 cmd, dma_addr_t dma_addr, u16 queue, 351 bool op) 352 { 353 struct qm_mailbox mailbox; 354 int ret = 0; 355 356 dev_dbg(&qm->pdev->dev, "QM mailbox request to q%u: %u-%llx\n", 357 queue, cmd, (unsigned long long)dma_addr); 358 359 mailbox.w0 = cpu_to_le16(cmd | 360 (op ? 0x1 << QM_MB_OP_SHIFT : 0) | 361 (0x1 << QM_MB_BUSY_SHIFT)); 362 mailbox.queue_num = cpu_to_le16(queue); 363 mailbox.base_l = cpu_to_le32(lower_32_bits(dma_addr)); 364 mailbox.base_h = cpu_to_le32(upper_32_bits(dma_addr)); 365 mailbox.rsvd = 0; 366 367 mutex_lock(&qm->mailbox_lock); 368 369 if (unlikely(qm_wait_mb_ready(qm))) { 370 ret = -EBUSY; 371 dev_err(&qm->pdev->dev, "QM mailbox is busy to start!\n"); 372 goto busy_unlock; 373 } 374 375 qm_mb_write(qm, &mailbox); 376 377 if (unlikely(qm_wait_mb_ready(qm))) { 378 ret = -EBUSY; 379 dev_err(&qm->pdev->dev, "QM mailbox operation timeout!\n"); 380 goto busy_unlock; 381 } 382 383 busy_unlock: 384 mutex_unlock(&qm->mailbox_lock); 385 386 return ret; 387 } 388 389 static void qm_db_v1(struct hisi_qm *qm, u16 qn, u8 cmd, u16 index, u8 priority) 390 { 391 u64 doorbell; 392 393 doorbell = qn | ((u64)cmd << QM_DB_CMD_SHIFT_V1) | 394 ((u64)index << QM_DB_INDEX_SHIFT_V1) | 395 ((u64)priority << QM_DB_PRIORITY_SHIFT_V1); 396 397 writeq(doorbell, qm->io_base + QM_DOORBELL_BASE_V1); 398 } 399 400 static void qm_db_v2(struct hisi_qm *qm, u16 qn, u8 cmd, u16 index, u8 priority) 401 { 402 u64 doorbell; 403 u64 dbase; 404 u16 randata = 0; 405 406 if (cmd == QM_DOORBELL_CMD_SQ || cmd == QM_DOORBELL_CMD_CQ) 407 dbase = QM_DOORBELL_SQ_CQ_BASE_V2; 408 else 409 dbase = QM_DOORBELL_EQ_AEQ_BASE_V2; 410 411 doorbell = qn | ((u64)cmd << QM_DB_CMD_SHIFT_V2) | 412 ((u64)randata << QM_DB_RAND_SHIFT_V2) | 413 ((u64)index << QM_DB_INDEX_SHIFT_V2) | 414 ((u64)priority << QM_DB_PRIORITY_SHIFT_V2); 415 416 writeq(doorbell, qm->io_base + dbase); 417 } 418 419 static void qm_db(struct hisi_qm *qm, u16 qn, u8 cmd, u16 index, u8 priority) 420 { 421 dev_dbg(&qm->pdev->dev, "QM doorbell request: qn=%u, cmd=%u, index=%u\n", 422 qn, cmd, index); 423 424 qm->ops->qm_db(qm, qn, cmd, index, priority); 425 } 426 427 static int qm_dev_mem_reset(struct hisi_qm *qm) 428 { 429 u32 val; 430 431 writel(0x1, qm->io_base + QM_MEM_START_INIT); 432 return readl_relaxed_poll_timeout(qm->io_base + QM_MEM_INIT_DONE, val, 433 val & BIT(0), 10, 1000); 434 } 435 436 static u32 qm_get_irq_num_v1(struct hisi_qm *qm) 437 { 438 return QM_IRQ_NUM_V1; 439 } 440 441 static u32 qm_get_irq_num_v2(struct hisi_qm *qm) 442 { 443 if (qm->fun_type == QM_HW_PF) 444 return QM_IRQ_NUM_PF_V2; 445 else 446 return QM_IRQ_NUM_VF_V2; 447 } 448 449 static struct hisi_qp *qm_to_hisi_qp(struct hisi_qm *qm, struct qm_eqe *eqe) 450 { 451 u16 cqn = le32_to_cpu(eqe->dw0) & QM_EQE_CQN_MASK; 452 453 return qm->qp_array[cqn]; 454 } 455 456 static void qm_cq_head_update(struct hisi_qp *qp) 457 { 458 if (qp->qp_status.cq_head == QM_Q_DEPTH - 1) { 459 qp->qp_status.cqc_phase = !qp->qp_status.cqc_phase; 460 qp->qp_status.cq_head = 0; 461 } else { 462 qp->qp_status.cq_head++; 463 } 464 } 465 466 static void qm_poll_qp(struct hisi_qp *qp, struct hisi_qm *qm) 467 { 468 struct qm_cqe *cqe = qp->cqe + qp->qp_status.cq_head; 469 470 if (qp->req_cb) { 471 while (QM_CQE_PHASE(cqe) == qp->qp_status.cqc_phase) { 472 dma_rmb(); 473 qp->req_cb(qp, qp->sqe + qm->sqe_size * 474 le16_to_cpu(cqe->sq_head)); 475 qm_cq_head_update(qp); 476 cqe = qp->cqe + qp->qp_status.cq_head; 477 qm_db(qm, qp->qp_id, QM_DOORBELL_CMD_CQ, 478 qp->qp_status.cq_head, 0); 479 atomic_dec(&qp->qp_status.used); 480 } 481 482 /* set c_flag */ 483 qm_db(qm, qp->qp_id, QM_DOORBELL_CMD_CQ, 484 qp->qp_status.cq_head, 1); 485 } 486 } 487 488 static void qm_qp_work_func(struct work_struct *work) 489 { 490 struct hisi_qp *qp; 491 492 qp = container_of(work, struct hisi_qp, work); 493 qm_poll_qp(qp, qp->qm); 494 } 495 496 static irqreturn_t qm_irq_handler(int irq, void *data) 497 { 498 struct hisi_qm *qm = data; 499 struct qm_eqe *eqe = qm->eqe + qm->status.eq_head; 500 struct hisi_qp *qp; 501 int eqe_num = 0; 502 503 while (QM_EQE_PHASE(eqe) == qm->status.eqc_phase) { 504 eqe_num++; 505 qp = qm_to_hisi_qp(qm, eqe); 506 if (qp) 507 queue_work(qp->wq, &qp->work); 508 509 if (qm->status.eq_head == QM_Q_DEPTH - 1) { 510 qm->status.eqc_phase = !qm->status.eqc_phase; 511 eqe = qm->eqe; 512 qm->status.eq_head = 0; 513 } else { 514 eqe++; 515 qm->status.eq_head++; 516 } 517 518 if (eqe_num == QM_Q_DEPTH / 2 - 1) { 519 eqe_num = 0; 520 qm_db(qm, 0, QM_DOORBELL_CMD_EQ, qm->status.eq_head, 0); 521 } 522 } 523 524 qm_db(qm, 0, QM_DOORBELL_CMD_EQ, qm->status.eq_head, 0); 525 526 return IRQ_HANDLED; 527 } 528 529 static irqreturn_t qm_irq(int irq, void *data) 530 { 531 struct hisi_qm *qm = data; 532 533 if (readl(qm->io_base + QM_VF_EQ_INT_SOURCE)) 534 return qm_irq_handler(irq, data); 535 536 dev_err(&qm->pdev->dev, "invalid int source\n"); 537 qm_db(qm, 0, QM_DOORBELL_CMD_EQ, qm->status.eq_head, 0); 538 539 return IRQ_NONE; 540 } 541 542 static irqreturn_t qm_aeq_irq(int irq, void *data) 543 { 544 struct hisi_qm *qm = data; 545 struct qm_aeqe *aeqe = qm->aeqe + qm->status.aeq_head; 546 u32 type; 547 548 if (!readl(qm->io_base + QM_VF_AEQ_INT_SOURCE)) 549 return IRQ_NONE; 550 551 while (QM_AEQE_PHASE(aeqe) == qm->status.aeqc_phase) { 552 type = le32_to_cpu(aeqe->dw0) >> QM_AEQE_TYPE_SHIFT; 553 if (type < ARRAY_SIZE(qm_fifo_overflow)) 554 dev_err(&qm->pdev->dev, "%s overflow\n", 555 qm_fifo_overflow[type]); 556 else 557 dev_err(&qm->pdev->dev, "unknown error type %d\n", 558 type); 559 560 if (qm->status.aeq_head == QM_Q_DEPTH - 1) { 561 qm->status.aeqc_phase = !qm->status.aeqc_phase; 562 aeqe = qm->aeqe; 563 qm->status.aeq_head = 0; 564 } else { 565 aeqe++; 566 qm->status.aeq_head++; 567 } 568 569 qm_db(qm, 0, QM_DOORBELL_CMD_AEQ, qm->status.aeq_head, 0); 570 } 571 572 return IRQ_HANDLED; 573 } 574 575 static irqreturn_t qm_abnormal_irq(int irq, void *data) 576 { 577 const struct hisi_qm_hw_error *err = qm_hw_error; 578 struct hisi_qm *qm = data; 579 struct device *dev = &qm->pdev->dev; 580 u32 error_status, tmp; 581 582 /* read err sts */ 583 tmp = readl(qm->io_base + QM_ABNORMAL_INT_STATUS); 584 error_status = qm->msi_mask & tmp; 585 586 while (err->msg) { 587 if (err->int_msk & error_status) 588 dev_err(dev, "%s [error status=0x%x] found\n", 589 err->msg, err->int_msk); 590 591 err++; 592 } 593 594 /* clear err sts */ 595 writel(error_status, qm->io_base + QM_ABNORMAL_INT_SOURCE); 596 597 return IRQ_HANDLED; 598 } 599 600 static int qm_irq_register(struct hisi_qm *qm) 601 { 602 struct pci_dev *pdev = qm->pdev; 603 int ret; 604 605 ret = request_irq(pci_irq_vector(pdev, QM_EQ_EVENT_IRQ_VECTOR), 606 qm_irq, IRQF_SHARED, qm->dev_name, qm); 607 if (ret) 608 return ret; 609 610 if (qm->ver == QM_HW_V2) { 611 ret = request_irq(pci_irq_vector(pdev, QM_AEQ_EVENT_IRQ_VECTOR), 612 qm_aeq_irq, IRQF_SHARED, qm->dev_name, qm); 613 if (ret) 614 goto err_aeq_irq; 615 616 if (qm->fun_type == QM_HW_PF) { 617 ret = request_irq(pci_irq_vector(pdev, 618 QM_ABNORMAL_EVENT_IRQ_VECTOR), 619 qm_abnormal_irq, IRQF_SHARED, 620 qm->dev_name, qm); 621 if (ret) 622 goto err_abonormal_irq; 623 } 624 } 625 626 return 0; 627 628 err_abonormal_irq: 629 free_irq(pci_irq_vector(pdev, QM_AEQ_EVENT_IRQ_VECTOR), qm); 630 err_aeq_irq: 631 free_irq(pci_irq_vector(pdev, QM_EQ_EVENT_IRQ_VECTOR), qm); 632 return ret; 633 } 634 635 static void qm_irq_unregister(struct hisi_qm *qm) 636 { 637 struct pci_dev *pdev = qm->pdev; 638 639 free_irq(pci_irq_vector(pdev, QM_EQ_EVENT_IRQ_VECTOR), qm); 640 641 if (qm->ver == QM_HW_V2) { 642 free_irq(pci_irq_vector(pdev, QM_AEQ_EVENT_IRQ_VECTOR), qm); 643 644 if (qm->fun_type == QM_HW_PF) 645 free_irq(pci_irq_vector(pdev, 646 QM_ABNORMAL_EVENT_IRQ_VECTOR), qm); 647 } 648 } 649 650 static void qm_init_qp_status(struct hisi_qp *qp) 651 { 652 struct hisi_qp_status *qp_status = &qp->qp_status; 653 654 qp_status->sq_tail = 0; 655 qp_status->cq_head = 0; 656 qp_status->cqc_phase = true; 657 qp_status->flags = 0; 658 } 659 660 static void qm_vft_data_cfg(struct hisi_qm *qm, enum vft_type type, u32 base, 661 u32 number) 662 { 663 u64 tmp = 0; 664 665 if (number > 0) { 666 switch (type) { 667 case SQC_VFT: 668 switch (qm->ver) { 669 case QM_HW_V1: 670 tmp = QM_SQC_VFT_BUF_SIZE | 671 QM_SQC_VFT_SQC_SIZE | 672 QM_SQC_VFT_INDEX_NUMBER | 673 QM_SQC_VFT_VALID | 674 (u64)base << QM_SQC_VFT_START_SQN_SHIFT; 675 break; 676 case QM_HW_V2: 677 tmp = (u64)base << QM_SQC_VFT_START_SQN_SHIFT | 678 QM_SQC_VFT_VALID | 679 (u64)(number - 1) << QM_SQC_VFT_SQN_SHIFT; 680 break; 681 case QM_HW_UNKNOWN: 682 break; 683 } 684 break; 685 case CQC_VFT: 686 switch (qm->ver) { 687 case QM_HW_V1: 688 tmp = QM_CQC_VFT_BUF_SIZE | 689 QM_CQC_VFT_SQC_SIZE | 690 QM_CQC_VFT_INDEX_NUMBER | 691 QM_CQC_VFT_VALID; 692 break; 693 case QM_HW_V2: 694 tmp = QM_CQC_VFT_VALID; 695 break; 696 case QM_HW_UNKNOWN: 697 break; 698 } 699 break; 700 } 701 } 702 703 writel(lower_32_bits(tmp), qm->io_base + QM_VFT_CFG_DATA_L); 704 writel(upper_32_bits(tmp), qm->io_base + QM_VFT_CFG_DATA_H); 705 } 706 707 static int qm_set_vft_common(struct hisi_qm *qm, enum vft_type type, 708 u32 fun_num, u32 base, u32 number) 709 { 710 unsigned int val; 711 int ret; 712 713 ret = readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val, 714 val & BIT(0), 10, 1000); 715 if (ret) 716 return ret; 717 718 writel(0x0, qm->io_base + QM_VFT_CFG_OP_WR); 719 writel(type, qm->io_base + QM_VFT_CFG_TYPE); 720 writel(fun_num, qm->io_base + QM_VFT_CFG); 721 722 qm_vft_data_cfg(qm, type, base, number); 723 724 writel(0x0, qm->io_base + QM_VFT_CFG_RDY); 725 writel(0x1, qm->io_base + QM_VFT_CFG_OP_ENABLE); 726 727 return readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val, 728 val & BIT(0), 10, 1000); 729 } 730 731 /* The config should be conducted after qm_dev_mem_reset() */ 732 static int qm_set_sqc_cqc_vft(struct hisi_qm *qm, u32 fun_num, u32 base, 733 u32 number) 734 { 735 int ret, i; 736 737 for (i = SQC_VFT; i <= CQC_VFT; i++) { 738 ret = qm_set_vft_common(qm, i, fun_num, base, number); 739 if (ret) 740 return ret; 741 } 742 743 return 0; 744 } 745 746 static int qm_get_vft_v2(struct hisi_qm *qm, u32 *base, u32 *number) 747 { 748 u64 sqc_vft; 749 int ret; 750 751 ret = qm_mb(qm, QM_MB_CMD_SQC_VFT_V2, 0, 0, 1); 752 if (ret) 753 return ret; 754 755 sqc_vft = readl(qm->io_base + QM_MB_CMD_DATA_ADDR_L) | 756 ((u64)readl(qm->io_base + QM_MB_CMD_DATA_ADDR_H) << 32); 757 *base = QM_SQC_VFT_BASE_MASK_V2 & (sqc_vft >> QM_SQC_VFT_BASE_SHIFT_V2); 758 *number = (QM_SQC_VFT_NUM_MASK_v2 & 759 (sqc_vft >> QM_SQC_VFT_NUM_SHIFT_V2)) + 1; 760 761 return 0; 762 } 763 764 static struct hisi_qm *file_to_qm(struct debugfs_file *file) 765 { 766 struct qm_debug *debug = file->debug; 767 768 return container_of(debug, struct hisi_qm, debug); 769 } 770 771 static u32 current_q_read(struct debugfs_file *file) 772 { 773 struct hisi_qm *qm = file_to_qm(file); 774 775 return readl(qm->io_base + QM_DFX_SQE_CNT_VF_SQN) >> QM_DFX_QN_SHIFT; 776 } 777 778 static int current_q_write(struct debugfs_file *file, u32 val) 779 { 780 struct hisi_qm *qm = file_to_qm(file); 781 u32 tmp; 782 783 if (val >= qm->debug.curr_qm_qp_num) 784 return -EINVAL; 785 786 tmp = val << QM_DFX_QN_SHIFT | 787 (readl(qm->io_base + QM_DFX_SQE_CNT_VF_SQN) & CURRENT_FUN_MASK); 788 writel(tmp, qm->io_base + QM_DFX_SQE_CNT_VF_SQN); 789 790 tmp = val << QM_DFX_QN_SHIFT | 791 (readl(qm->io_base + QM_DFX_CQE_CNT_VF_CQN) & CURRENT_FUN_MASK); 792 writel(tmp, qm->io_base + QM_DFX_CQE_CNT_VF_CQN); 793 794 return 0; 795 } 796 797 static u32 clear_enable_read(struct debugfs_file *file) 798 { 799 struct hisi_qm *qm = file_to_qm(file); 800 801 return readl(qm->io_base + QM_DFX_CNT_CLR_CE); 802 } 803 804 /* rd_clr_ctrl 1 enable read clear, otherwise 0 disable it */ 805 static int clear_enable_write(struct debugfs_file *file, u32 rd_clr_ctrl) 806 { 807 struct hisi_qm *qm = file_to_qm(file); 808 809 if (rd_clr_ctrl > 1) 810 return -EINVAL; 811 812 writel(rd_clr_ctrl, qm->io_base + QM_DFX_CNT_CLR_CE); 813 814 return 0; 815 } 816 817 static ssize_t qm_debug_read(struct file *filp, char __user *buf, 818 size_t count, loff_t *pos) 819 { 820 struct debugfs_file *file = filp->private_data; 821 enum qm_debug_file index = file->index; 822 char tbuf[QM_DBG_TMP_BUF_LEN]; 823 u32 val; 824 int ret; 825 826 mutex_lock(&file->lock); 827 switch (index) { 828 case CURRENT_Q: 829 val = current_q_read(file); 830 break; 831 case CLEAR_ENABLE: 832 val = clear_enable_read(file); 833 break; 834 default: 835 mutex_unlock(&file->lock); 836 return -EINVAL; 837 } 838 mutex_unlock(&file->lock); 839 ret = sprintf(tbuf, "%u\n", val); 840 return simple_read_from_buffer(buf, count, pos, tbuf, ret); 841 } 842 843 static ssize_t qm_debug_write(struct file *filp, const char __user *buf, 844 size_t count, loff_t *pos) 845 { 846 struct debugfs_file *file = filp->private_data; 847 enum qm_debug_file index = file->index; 848 unsigned long val; 849 char tbuf[QM_DBG_TMP_BUF_LEN]; 850 int len, ret; 851 852 if (*pos != 0) 853 return 0; 854 855 if (count >= QM_DBG_TMP_BUF_LEN) 856 return -ENOSPC; 857 858 len = simple_write_to_buffer(tbuf, QM_DBG_TMP_BUF_LEN - 1, pos, buf, 859 count); 860 if (len < 0) 861 return len; 862 863 tbuf[len] = '\0'; 864 if (kstrtoul(tbuf, 0, &val)) 865 return -EFAULT; 866 867 mutex_lock(&file->lock); 868 switch (index) { 869 case CURRENT_Q: 870 ret = current_q_write(file, val); 871 if (ret) 872 goto err_input; 873 break; 874 case CLEAR_ENABLE: 875 ret = clear_enable_write(file, val); 876 if (ret) 877 goto err_input; 878 break; 879 default: 880 ret = -EINVAL; 881 goto err_input; 882 } 883 mutex_unlock(&file->lock); 884 885 return count; 886 887 err_input: 888 mutex_unlock(&file->lock); 889 return ret; 890 } 891 892 static const struct file_operations qm_debug_fops = { 893 .owner = THIS_MODULE, 894 .open = simple_open, 895 .read = qm_debug_read, 896 .write = qm_debug_write, 897 }; 898 899 struct qm_dfx_registers { 900 char *reg_name; 901 u64 reg_offset; 902 }; 903 904 #define CNT_CYC_REGS_NUM 10 905 static struct qm_dfx_registers qm_dfx_regs[] = { 906 /* XXX_CNT are reading clear register */ 907 {"QM_ECC_1BIT_CNT ", 0x104000ull}, 908 {"QM_ECC_MBIT_CNT ", 0x104008ull}, 909 {"QM_DFX_MB_CNT ", 0x104018ull}, 910 {"QM_DFX_DB_CNT ", 0x104028ull}, 911 {"QM_DFX_SQE_CNT ", 0x104038ull}, 912 {"QM_DFX_CQE_CNT ", 0x104048ull}, 913 {"QM_DFX_SEND_SQE_TO_ACC_CNT ", 0x104050ull}, 914 {"QM_DFX_WB_SQE_FROM_ACC_CNT ", 0x104058ull}, 915 {"QM_DFX_ACC_FINISH_CNT ", 0x104060ull}, 916 {"QM_DFX_CQE_ERR_CNT ", 0x1040b4ull}, 917 {"QM_DFX_FUNS_ACTIVE_ST ", 0x200ull}, 918 {"QM_ECC_1BIT_INF ", 0x104004ull}, 919 {"QM_ECC_MBIT_INF ", 0x10400cull}, 920 {"QM_DFX_ACC_RDY_VLD0 ", 0x1040a0ull}, 921 {"QM_DFX_ACC_RDY_VLD1 ", 0x1040a4ull}, 922 {"QM_DFX_AXI_RDY_VLD ", 0x1040a8ull}, 923 {"QM_DFX_FF_ST0 ", 0x1040c8ull}, 924 {"QM_DFX_FF_ST1 ", 0x1040ccull}, 925 {"QM_DFX_FF_ST2 ", 0x1040d0ull}, 926 {"QM_DFX_FF_ST3 ", 0x1040d4ull}, 927 {"QM_DFX_FF_ST4 ", 0x1040d8ull}, 928 {"QM_DFX_FF_ST5 ", 0x1040dcull}, 929 {"QM_DFX_FF_ST6 ", 0x1040e0ull}, 930 {"QM_IN_IDLE_ST ", 0x1040e4ull}, 931 { NULL, 0} 932 }; 933 934 static struct qm_dfx_registers qm_vf_dfx_regs[] = { 935 {"QM_DFX_FUNS_ACTIVE_ST ", 0x200ull}, 936 { NULL, 0} 937 }; 938 939 static int qm_regs_show(struct seq_file *s, void *unused) 940 { 941 struct hisi_qm *qm = s->private; 942 struct qm_dfx_registers *regs; 943 u32 val; 944 945 if (qm->fun_type == QM_HW_PF) 946 regs = qm_dfx_regs; 947 else 948 regs = qm_vf_dfx_regs; 949 950 while (regs->reg_name) { 951 val = readl(qm->io_base + regs->reg_offset); 952 seq_printf(s, "%s= 0x%08x\n", regs->reg_name, val); 953 regs++; 954 } 955 956 return 0; 957 } 958 959 static int qm_regs_open(struct inode *inode, struct file *file) 960 { 961 return single_open(file, qm_regs_show, inode->i_private); 962 } 963 964 static const struct file_operations qm_regs_fops = { 965 .owner = THIS_MODULE, 966 .open = qm_regs_open, 967 .read = seq_read, 968 .release = single_release, 969 }; 970 971 static int qm_create_debugfs_file(struct hisi_qm *qm, enum qm_debug_file index) 972 { 973 struct dentry *qm_d = qm->debug.qm_d; 974 struct debugfs_file *file = qm->debug.files + index; 975 976 debugfs_create_file(qm_debug_file_name[index], 0600, qm_d, file, 977 &qm_debug_fops); 978 979 file->index = index; 980 mutex_init(&file->lock); 981 file->debug = &qm->debug; 982 983 return 0; 984 } 985 986 static void qm_hw_error_init_v1(struct hisi_qm *qm, u32 ce, u32 nfe, u32 fe, 987 u32 msi) 988 { 989 writel(QM_ABNORMAL_INT_MASK_VALUE, qm->io_base + QM_ABNORMAL_INT_MASK); 990 } 991 992 static void qm_hw_error_init_v2(struct hisi_qm *qm, u32 ce, u32 nfe, u32 fe, 993 u32 msi) 994 { 995 u32 irq_enable = ce | nfe | fe | msi; 996 u32 irq_unmask = ~irq_enable; 997 998 qm->error_mask = ce | nfe | fe; 999 qm->msi_mask = msi; 1000 1001 /* configure error type */ 1002 writel(ce, qm->io_base + QM_RAS_CE_ENABLE); 1003 writel(QM_RAS_CE_TIMES_PER_IRQ, qm->io_base + QM_RAS_CE_THRESHOLD); 1004 writel(nfe, qm->io_base + QM_RAS_NFE_ENABLE); 1005 writel(fe, qm->io_base + QM_RAS_FE_ENABLE); 1006 1007 /* use RAS irq default, so only set QM_RAS_MSI_INT_SEL for MSI */ 1008 writel(msi, qm->io_base + QM_RAS_MSI_INT_SEL); 1009 1010 irq_unmask &= readl(qm->io_base + QM_ABNORMAL_INT_MASK); 1011 writel(irq_unmask, qm->io_base + QM_ABNORMAL_INT_MASK); 1012 } 1013 1014 static void qm_log_hw_error(struct hisi_qm *qm, u32 error_status) 1015 { 1016 const struct hisi_qm_hw_error *err = qm_hw_error; 1017 struct device *dev = &qm->pdev->dev; 1018 u32 reg_val, type, vf_num; 1019 1020 while (err->msg) { 1021 if (err->int_msk & error_status) { 1022 dev_err(dev, "%s [error status=0x%x] found\n", 1023 err->msg, err->int_msk); 1024 1025 if (error_status & QM_DB_TIMEOUT) { 1026 reg_val = readl(qm->io_base + 1027 QM_ABNORMAL_INF01); 1028 type = (reg_val & QM_DB_TIMEOUT_TYPE) >> 1029 QM_DB_TIMEOUT_TYPE_SHIFT; 1030 vf_num = reg_val & QM_DB_TIMEOUT_VF; 1031 dev_err(dev, "qm %s doorbell timeout in function %u\n", 1032 qm_db_timeout[type], vf_num); 1033 } 1034 1035 if (error_status & QM_OF_FIFO_OF) { 1036 reg_val = readl(qm->io_base + 1037 QM_ABNORMAL_INF00); 1038 type = (reg_val & QM_FIFO_OVERFLOW_TYPE) >> 1039 QM_FIFO_OVERFLOW_TYPE_SHIFT; 1040 vf_num = reg_val & QM_FIFO_OVERFLOW_VF; 1041 1042 if (type < ARRAY_SIZE(qm_fifo_overflow)) 1043 dev_err(dev, "qm %s fifo overflow in function %u\n", 1044 qm_fifo_overflow[type], 1045 vf_num); 1046 else 1047 dev_err(dev, "unknown error type\n"); 1048 } 1049 } 1050 err++; 1051 } 1052 } 1053 1054 static pci_ers_result_t qm_hw_error_handle_v2(struct hisi_qm *qm) 1055 { 1056 u32 error_status, tmp; 1057 1058 /* read err sts */ 1059 tmp = readl(qm->io_base + QM_ABNORMAL_INT_STATUS); 1060 error_status = qm->error_mask & tmp; 1061 1062 if (error_status) { 1063 qm_log_hw_error(qm, error_status); 1064 1065 /* clear err sts */ 1066 writel(error_status, qm->io_base + QM_ABNORMAL_INT_SOURCE); 1067 1068 return PCI_ERS_RESULT_NEED_RESET; 1069 } 1070 1071 return PCI_ERS_RESULT_RECOVERED; 1072 } 1073 1074 static const struct hisi_qm_hw_ops qm_hw_ops_v1 = { 1075 .qm_db = qm_db_v1, 1076 .get_irq_num = qm_get_irq_num_v1, 1077 .hw_error_init = qm_hw_error_init_v1, 1078 }; 1079 1080 static const struct hisi_qm_hw_ops qm_hw_ops_v2 = { 1081 .get_vft = qm_get_vft_v2, 1082 .qm_db = qm_db_v2, 1083 .get_irq_num = qm_get_irq_num_v2, 1084 .hw_error_init = qm_hw_error_init_v2, 1085 .hw_error_handle = qm_hw_error_handle_v2, 1086 }; 1087 1088 static void *qm_get_avail_sqe(struct hisi_qp *qp) 1089 { 1090 struct hisi_qp_status *qp_status = &qp->qp_status; 1091 u16 sq_tail = qp_status->sq_tail; 1092 1093 if (unlikely(atomic_read(&qp->qp_status.used) == QM_Q_DEPTH)) 1094 return NULL; 1095 1096 return qp->sqe + sq_tail * qp->qm->sqe_size; 1097 } 1098 1099 /** 1100 * hisi_qm_create_qp() - Create a queue pair from qm. 1101 * @qm: The qm we create a qp from. 1102 * @alg_type: Accelerator specific algorithm type in sqc. 1103 * 1104 * return created qp, -EBUSY if all qps in qm allocated, -ENOMEM if allocating 1105 * qp memory fails. 1106 */ 1107 struct hisi_qp *hisi_qm_create_qp(struct hisi_qm *qm, u8 alg_type) 1108 { 1109 struct device *dev = &qm->pdev->dev; 1110 struct hisi_qp *qp; 1111 int qp_id, ret; 1112 1113 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 1114 if (!qp) 1115 return ERR_PTR(-ENOMEM); 1116 1117 write_lock(&qm->qps_lock); 1118 1119 qp_id = find_first_zero_bit(qm->qp_bitmap, qm->qp_num); 1120 if (qp_id >= qm->qp_num) { 1121 write_unlock(&qm->qps_lock); 1122 dev_info(&qm->pdev->dev, "QM all queues are busy!\n"); 1123 ret = -EBUSY; 1124 goto err_free_qp; 1125 } 1126 set_bit(qp_id, qm->qp_bitmap); 1127 qm->qp_array[qp_id] = qp; 1128 qm->qp_in_used++; 1129 1130 write_unlock(&qm->qps_lock); 1131 1132 qp->qm = qm; 1133 1134 if (qm->use_dma_api) { 1135 qp->qdma.size = qm->sqe_size * QM_Q_DEPTH + 1136 sizeof(struct qm_cqe) * QM_Q_DEPTH; 1137 qp->qdma.va = dma_alloc_coherent(dev, qp->qdma.size, 1138 &qp->qdma.dma, GFP_KERNEL); 1139 if (!qp->qdma.va) { 1140 ret = -ENOMEM; 1141 goto err_clear_bit; 1142 } 1143 1144 dev_dbg(dev, "allocate qp dma buf(va=%pK, dma=%pad, size=%zx)\n", 1145 qp->qdma.va, &qp->qdma.dma, qp->qdma.size); 1146 } 1147 1148 qp->qp_id = qp_id; 1149 qp->alg_type = alg_type; 1150 INIT_WORK(&qp->work, qm_qp_work_func); 1151 qp->wq = alloc_workqueue("hisi_qm", WQ_UNBOUND | WQ_HIGHPRI | 1152 WQ_CPU_INTENSIVE | WQ_MEM_RECLAIM, 0); 1153 if (!qp->wq) { 1154 ret = -EFAULT; 1155 goto err_free_qp_mem; 1156 } 1157 1158 return qp; 1159 1160 err_free_qp_mem: 1161 if (qm->use_dma_api) 1162 dma_free_coherent(dev, qp->qdma.size, qp->qdma.va, 1163 qp->qdma.dma); 1164 err_clear_bit: 1165 write_lock(&qm->qps_lock); 1166 qm->qp_array[qp_id] = NULL; 1167 clear_bit(qp_id, qm->qp_bitmap); 1168 write_unlock(&qm->qps_lock); 1169 err_free_qp: 1170 kfree(qp); 1171 return ERR_PTR(ret); 1172 } 1173 EXPORT_SYMBOL_GPL(hisi_qm_create_qp); 1174 1175 /** 1176 * hisi_qm_release_qp() - Release a qp back to its qm. 1177 * @qp: The qp we want to release. 1178 * 1179 * This function releases the resource of a qp. 1180 */ 1181 void hisi_qm_release_qp(struct hisi_qp *qp) 1182 { 1183 struct hisi_qm *qm = qp->qm; 1184 struct qm_dma *qdma = &qp->qdma; 1185 struct device *dev = &qm->pdev->dev; 1186 1187 if (qm->use_dma_api && qdma->va) 1188 dma_free_coherent(dev, qdma->size, qdma->va, qdma->dma); 1189 1190 write_lock(&qm->qps_lock); 1191 qm->qp_array[qp->qp_id] = NULL; 1192 clear_bit(qp->qp_id, qm->qp_bitmap); 1193 qm->qp_in_used--; 1194 write_unlock(&qm->qps_lock); 1195 1196 kfree(qp); 1197 } 1198 EXPORT_SYMBOL_GPL(hisi_qm_release_qp); 1199 1200 static int qm_qp_ctx_cfg(struct hisi_qp *qp, int qp_id, int pasid) 1201 { 1202 struct hisi_qm *qm = qp->qm; 1203 struct device *dev = &qm->pdev->dev; 1204 enum qm_hw_ver ver = qm->ver; 1205 struct qm_sqc *sqc; 1206 struct qm_cqc *cqc; 1207 dma_addr_t sqc_dma; 1208 dma_addr_t cqc_dma; 1209 int ret; 1210 1211 qm_init_qp_status(qp); 1212 1213 sqc = kzalloc(sizeof(struct qm_sqc), GFP_KERNEL); 1214 if (!sqc) 1215 return -ENOMEM; 1216 sqc_dma = dma_map_single(dev, sqc, sizeof(struct qm_sqc), 1217 DMA_TO_DEVICE); 1218 if (dma_mapping_error(dev, sqc_dma)) { 1219 kfree(sqc); 1220 return -ENOMEM; 1221 } 1222 1223 INIT_QC_COMMON(sqc, qp->sqe_dma, pasid); 1224 if (ver == QM_HW_V1) { 1225 sqc->dw3 = cpu_to_le32(QM_MK_SQC_DW3_V1(0, 0, 0, qm->sqe_size)); 1226 sqc->w8 = cpu_to_le16(QM_Q_DEPTH - 1); 1227 } else if (ver == QM_HW_V2) { 1228 sqc->dw3 = cpu_to_le32(QM_MK_SQC_DW3_V2(qm->sqe_size)); 1229 sqc->w8 = 0; /* rand_qc */ 1230 } 1231 sqc->cq_num = cpu_to_le16(qp_id); 1232 sqc->w13 = cpu_to_le16(QM_MK_SQC_W13(0, 1, qp->alg_type)); 1233 1234 ret = qm_mb(qm, QM_MB_CMD_SQC, sqc_dma, qp_id, 0); 1235 dma_unmap_single(dev, sqc_dma, sizeof(struct qm_sqc), DMA_TO_DEVICE); 1236 kfree(sqc); 1237 if (ret) 1238 return ret; 1239 1240 cqc = kzalloc(sizeof(struct qm_cqc), GFP_KERNEL); 1241 if (!cqc) 1242 return -ENOMEM; 1243 cqc_dma = dma_map_single(dev, cqc, sizeof(struct qm_cqc), 1244 DMA_TO_DEVICE); 1245 if (dma_mapping_error(dev, cqc_dma)) { 1246 kfree(cqc); 1247 return -ENOMEM; 1248 } 1249 1250 INIT_QC_COMMON(cqc, qp->cqe_dma, pasid); 1251 if (ver == QM_HW_V1) { 1252 cqc->dw3 = cpu_to_le32(QM_MK_CQC_DW3_V1(0, 0, 0, 4)); 1253 cqc->w8 = cpu_to_le16(QM_Q_DEPTH - 1); 1254 } else if (ver == QM_HW_V2) { 1255 cqc->dw3 = cpu_to_le32(QM_MK_CQC_DW3_V2(4)); 1256 cqc->w8 = 0; 1257 } 1258 cqc->dw6 = cpu_to_le32(1 << QM_CQ_PHASE_SHIFT | 1 << QM_CQ_FLAG_SHIFT); 1259 1260 ret = qm_mb(qm, QM_MB_CMD_CQC, cqc_dma, qp_id, 0); 1261 dma_unmap_single(dev, cqc_dma, sizeof(struct qm_cqc), DMA_TO_DEVICE); 1262 kfree(cqc); 1263 1264 return ret; 1265 } 1266 1267 /** 1268 * hisi_qm_start_qp() - Start a qp into running. 1269 * @qp: The qp we want to start to run. 1270 * @arg: Accelerator specific argument. 1271 * 1272 * After this function, qp can receive request from user. Return qp_id if 1273 * successful, Return -EBUSY if failed. 1274 */ 1275 int hisi_qm_start_qp(struct hisi_qp *qp, unsigned long arg) 1276 { 1277 struct hisi_qm *qm = qp->qm; 1278 struct device *dev = &qm->pdev->dev; 1279 enum qm_hw_ver ver = qm->ver; 1280 int qp_id = qp->qp_id; 1281 int pasid = arg; 1282 size_t off = 0; 1283 int ret; 1284 1285 #define QP_INIT_BUF(qp, type, size) do { \ 1286 (qp)->type = ((qp)->qdma.va + (off)); \ 1287 (qp)->type##_dma = (qp)->qdma.dma + (off); \ 1288 off += (size); \ 1289 } while (0) 1290 1291 if (!qp->qdma.dma) { 1292 dev_err(dev, "cannot get qm dma buffer\n"); 1293 return -EINVAL; 1294 } 1295 1296 /* sq need 128 bytes alignment */ 1297 if (qp->qdma.dma & QM_SQE_DATA_ALIGN_MASK) { 1298 dev_err(dev, "qm sq is not aligned to 128 byte\n"); 1299 return -EINVAL; 1300 } 1301 1302 QP_INIT_BUF(qp, sqe, qm->sqe_size * QM_Q_DEPTH); 1303 QP_INIT_BUF(qp, cqe, sizeof(struct qm_cqe) * QM_Q_DEPTH); 1304 1305 dev_dbg(dev, "init qp buffer(v%d):\n" 1306 " sqe (%pK, %lx)\n" 1307 " cqe (%pK, %lx)\n", 1308 ver, qp->sqe, (unsigned long)qp->sqe_dma, 1309 qp->cqe, (unsigned long)qp->cqe_dma); 1310 1311 ret = qm_qp_ctx_cfg(qp, qp_id, pasid); 1312 if (ret) 1313 return ret; 1314 1315 dev_dbg(dev, "queue %d started\n", qp_id); 1316 1317 return qp_id; 1318 } 1319 EXPORT_SYMBOL_GPL(hisi_qm_start_qp); 1320 1321 /** 1322 * hisi_qm_stop_qp() - Stop a qp in qm. 1323 * @qp: The qp we want to stop. 1324 * 1325 * This function is reverse of hisi_qm_start_qp. Return 0 if successful. 1326 */ 1327 int hisi_qm_stop_qp(struct hisi_qp *qp) 1328 { 1329 struct device *dev = &qp->qm->pdev->dev; 1330 int i = 0; 1331 1332 /* it is stopped */ 1333 if (test_bit(QP_STOP, &qp->qp_status.flags)) 1334 return 0; 1335 1336 while (atomic_read(&qp->qp_status.used)) { 1337 i++; 1338 msleep(20); 1339 if (i == 10) { 1340 dev_err(dev, "Cannot drain out data for stopping, Force to stop!\n"); 1341 return 0; 1342 } 1343 } 1344 1345 set_bit(QP_STOP, &qp->qp_status.flags); 1346 1347 dev_dbg(dev, "stop queue %u!", qp->qp_id); 1348 1349 return 0; 1350 } 1351 EXPORT_SYMBOL_GPL(hisi_qm_stop_qp); 1352 1353 /** 1354 * hisi_qp_send() - Queue up a task in the hardware queue. 1355 * @qp: The qp in which to put the message. 1356 * @msg: The message. 1357 * 1358 * This function will return -EBUSY if qp is currently full, and -EAGAIN 1359 * if qp related qm is resetting. 1360 */ 1361 int hisi_qp_send(struct hisi_qp *qp, const void *msg) 1362 { 1363 struct hisi_qp_status *qp_status = &qp->qp_status; 1364 u16 sq_tail = qp_status->sq_tail; 1365 u16 sq_tail_next = (sq_tail + 1) % QM_Q_DEPTH; 1366 void *sqe = qm_get_avail_sqe(qp); 1367 1368 if (unlikely(test_bit(QP_STOP, &qp->qp_status.flags))) { 1369 dev_info(&qp->qm->pdev->dev, "QP is stopped or resetting\n"); 1370 return -EAGAIN; 1371 } 1372 1373 if (!sqe) 1374 return -EBUSY; 1375 1376 memcpy(sqe, msg, qp->qm->sqe_size); 1377 1378 qm_db(qp->qm, qp->qp_id, QM_DOORBELL_CMD_SQ, sq_tail_next, 0); 1379 atomic_inc(&qp->qp_status.used); 1380 qp_status->sq_tail = sq_tail_next; 1381 1382 return 0; 1383 } 1384 EXPORT_SYMBOL_GPL(hisi_qp_send); 1385 1386 static void hisi_qm_cache_wb(struct hisi_qm *qm) 1387 { 1388 unsigned int val; 1389 1390 if (qm->ver == QM_HW_V2) { 1391 writel(0x1, qm->io_base + QM_CACHE_WB_START); 1392 if (readl_relaxed_poll_timeout(qm->io_base + QM_CACHE_WB_DONE, 1393 val, val & BIT(0), 10, 1000)) 1394 dev_err(&qm->pdev->dev, "QM writeback sqc cache fail!\n"); 1395 } 1396 } 1397 1398 /** 1399 * hisi_qm_get_free_qp_num() - Get free number of qp in qm. 1400 * @qm: The qm which want to get free qp. 1401 * 1402 * This function return free number of qp in qm. 1403 */ 1404 int hisi_qm_get_free_qp_num(struct hisi_qm *qm) 1405 { 1406 int ret; 1407 1408 read_lock(&qm->qps_lock); 1409 ret = qm->qp_num - qm->qp_in_used; 1410 read_unlock(&qm->qps_lock); 1411 1412 return ret; 1413 } 1414 EXPORT_SYMBOL_GPL(hisi_qm_get_free_qp_num); 1415 1416 /** 1417 * hisi_qm_init() - Initialize configures about qm. 1418 * @qm: The qm needing init. 1419 * 1420 * This function init qm, then we can call hisi_qm_start to put qm into work. 1421 */ 1422 int hisi_qm_init(struct hisi_qm *qm) 1423 { 1424 struct pci_dev *pdev = qm->pdev; 1425 struct device *dev = &pdev->dev; 1426 unsigned int num_vec; 1427 int ret; 1428 1429 switch (qm->ver) { 1430 case QM_HW_V1: 1431 qm->ops = &qm_hw_ops_v1; 1432 break; 1433 case QM_HW_V2: 1434 qm->ops = &qm_hw_ops_v2; 1435 break; 1436 default: 1437 return -EINVAL; 1438 } 1439 1440 ret = pci_enable_device_mem(pdev); 1441 if (ret < 0) { 1442 dev_err(&pdev->dev, "Failed to enable device mem!\n"); 1443 return ret; 1444 } 1445 1446 ret = pci_request_mem_regions(pdev, qm->dev_name); 1447 if (ret < 0) { 1448 dev_err(&pdev->dev, "Failed to request mem regions!\n"); 1449 goto err_disable_pcidev; 1450 } 1451 1452 qm->io_base = ioremap(pci_resource_start(pdev, PCI_BAR_2), 1453 pci_resource_len(qm->pdev, PCI_BAR_2)); 1454 if (!qm->io_base) { 1455 ret = -EIO; 1456 goto err_release_mem_regions; 1457 } 1458 1459 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); 1460 if (ret < 0) 1461 goto err_iounmap; 1462 pci_set_master(pdev); 1463 1464 if (!qm->ops->get_irq_num) { 1465 ret = -EOPNOTSUPP; 1466 goto err_iounmap; 1467 } 1468 num_vec = qm->ops->get_irq_num(qm); 1469 ret = pci_alloc_irq_vectors(pdev, num_vec, num_vec, PCI_IRQ_MSI); 1470 if (ret < 0) { 1471 dev_err(dev, "Failed to enable MSI vectors!\n"); 1472 goto err_iounmap; 1473 } 1474 1475 ret = qm_irq_register(qm); 1476 if (ret) 1477 goto err_free_irq_vectors; 1478 1479 qm->qp_in_used = 0; 1480 mutex_init(&qm->mailbox_lock); 1481 rwlock_init(&qm->qps_lock); 1482 1483 dev_dbg(dev, "init qm %s with %s\n", pdev->is_physfn ? "pf" : "vf", 1484 qm->use_dma_api ? "dma api" : "iommu api"); 1485 1486 return 0; 1487 1488 err_free_irq_vectors: 1489 pci_free_irq_vectors(pdev); 1490 err_iounmap: 1491 iounmap(qm->io_base); 1492 err_release_mem_regions: 1493 pci_release_mem_regions(pdev); 1494 err_disable_pcidev: 1495 pci_disable_device(pdev); 1496 1497 return ret; 1498 } 1499 EXPORT_SYMBOL_GPL(hisi_qm_init); 1500 1501 /** 1502 * hisi_qm_uninit() - Uninitialize qm. 1503 * @qm: The qm needed uninit. 1504 * 1505 * This function uninits qm related device resources. 1506 */ 1507 void hisi_qm_uninit(struct hisi_qm *qm) 1508 { 1509 struct pci_dev *pdev = qm->pdev; 1510 struct device *dev = &pdev->dev; 1511 1512 if (qm->use_dma_api && qm->qdma.va) { 1513 hisi_qm_cache_wb(qm); 1514 dma_free_coherent(dev, qm->qdma.size, 1515 qm->qdma.va, qm->qdma.dma); 1516 memset(&qm->qdma, 0, sizeof(qm->qdma)); 1517 } 1518 1519 qm_irq_unregister(qm); 1520 pci_free_irq_vectors(pdev); 1521 iounmap(qm->io_base); 1522 pci_release_mem_regions(pdev); 1523 pci_disable_device(pdev); 1524 } 1525 EXPORT_SYMBOL_GPL(hisi_qm_uninit); 1526 1527 /** 1528 * hisi_qm_get_vft() - Get vft from a qm. 1529 * @qm: The qm we want to get its vft. 1530 * @base: The base number of queue in vft. 1531 * @number: The number of queues in vft. 1532 * 1533 * We can allocate multiple queues to a qm by configuring virtual function 1534 * table. We get related configures by this function. Normally, we call this 1535 * function in VF driver to get the queue information. 1536 * 1537 * qm hw v1 does not support this interface. 1538 */ 1539 int hisi_qm_get_vft(struct hisi_qm *qm, u32 *base, u32 *number) 1540 { 1541 if (!base || !number) 1542 return -EINVAL; 1543 1544 if (!qm->ops->get_vft) { 1545 dev_err(&qm->pdev->dev, "Don't support vft read!\n"); 1546 return -EINVAL; 1547 } 1548 1549 return qm->ops->get_vft(qm, base, number); 1550 } 1551 EXPORT_SYMBOL_GPL(hisi_qm_get_vft); 1552 1553 /** 1554 * hisi_qm_set_vft() - Set "virtual function table" for a qm. 1555 * @fun_num: Number of operated function. 1556 * @qm: The qm in which to set vft, alway in a PF. 1557 * @base: The base number of queue in vft. 1558 * @number: The number of queues in vft. 0 means invalid vft. 1559 * 1560 * This function is alway called in PF driver, it is used to assign queues 1561 * among PF and VFs. 1562 * 1563 * Assign queues A~B to PF: hisi_qm_set_vft(qm, 0, A, B - A + 1) 1564 * Assign queues A~B to VF: hisi_qm_set_vft(qm, 2, A, B - A + 1) 1565 * (VF function number 0x2) 1566 */ 1567 int hisi_qm_set_vft(struct hisi_qm *qm, u32 fun_num, u32 base, 1568 u32 number) 1569 { 1570 u32 max_q_num = qm->ctrl_qp_num; 1571 1572 if (base >= max_q_num || number > max_q_num || 1573 (base + number) > max_q_num) 1574 return -EINVAL; 1575 1576 return qm_set_sqc_cqc_vft(qm, fun_num, base, number); 1577 } 1578 EXPORT_SYMBOL_GPL(hisi_qm_set_vft); 1579 1580 static void qm_init_eq_aeq_status(struct hisi_qm *qm) 1581 { 1582 struct hisi_qm_status *status = &qm->status; 1583 1584 status->eq_head = 0; 1585 status->aeq_head = 0; 1586 status->eqc_phase = true; 1587 status->aeqc_phase = true; 1588 } 1589 1590 static int qm_eq_ctx_cfg(struct hisi_qm *qm) 1591 { 1592 struct device *dev = &qm->pdev->dev; 1593 struct qm_eqc *eqc; 1594 struct qm_aeqc *aeqc; 1595 dma_addr_t eqc_dma; 1596 dma_addr_t aeqc_dma; 1597 int ret; 1598 1599 qm_init_eq_aeq_status(qm); 1600 1601 eqc = kzalloc(sizeof(struct qm_eqc), GFP_KERNEL); 1602 if (!eqc) 1603 return -ENOMEM; 1604 eqc_dma = dma_map_single(dev, eqc, sizeof(struct qm_eqc), 1605 DMA_TO_DEVICE); 1606 if (dma_mapping_error(dev, eqc_dma)) { 1607 kfree(eqc); 1608 return -ENOMEM; 1609 } 1610 1611 eqc->base_l = cpu_to_le32(lower_32_bits(qm->eqe_dma)); 1612 eqc->base_h = cpu_to_le32(upper_32_bits(qm->eqe_dma)); 1613 if (qm->ver == QM_HW_V1) 1614 eqc->dw3 = cpu_to_le32(QM_EQE_AEQE_SIZE); 1615 eqc->dw6 = cpu_to_le32((QM_Q_DEPTH - 1) | (1 << QM_EQC_PHASE_SHIFT)); 1616 ret = qm_mb(qm, QM_MB_CMD_EQC, eqc_dma, 0, 0); 1617 dma_unmap_single(dev, eqc_dma, sizeof(struct qm_eqc), DMA_TO_DEVICE); 1618 kfree(eqc); 1619 if (ret) 1620 return ret; 1621 1622 aeqc = kzalloc(sizeof(struct qm_aeqc), GFP_KERNEL); 1623 if (!aeqc) 1624 return -ENOMEM; 1625 aeqc_dma = dma_map_single(dev, aeqc, sizeof(struct qm_aeqc), 1626 DMA_TO_DEVICE); 1627 if (dma_mapping_error(dev, aeqc_dma)) { 1628 kfree(aeqc); 1629 return -ENOMEM; 1630 } 1631 1632 aeqc->base_l = cpu_to_le32(lower_32_bits(qm->aeqe_dma)); 1633 aeqc->base_h = cpu_to_le32(upper_32_bits(qm->aeqe_dma)); 1634 aeqc->dw6 = cpu_to_le32((QM_Q_DEPTH - 1) | (1 << QM_EQC_PHASE_SHIFT)); 1635 1636 ret = qm_mb(qm, QM_MB_CMD_AEQC, aeqc_dma, 0, 0); 1637 dma_unmap_single(dev, aeqc_dma, sizeof(struct qm_aeqc), DMA_TO_DEVICE); 1638 kfree(aeqc); 1639 1640 return ret; 1641 } 1642 1643 static int __hisi_qm_start(struct hisi_qm *qm) 1644 { 1645 struct pci_dev *pdev = qm->pdev; 1646 struct device *dev = &pdev->dev; 1647 size_t off = 0; 1648 int ret; 1649 1650 #define QM_INIT_BUF(qm, type, num) do { \ 1651 (qm)->type = ((qm)->qdma.va + (off)); \ 1652 (qm)->type##_dma = (qm)->qdma.dma + (off); \ 1653 off += QMC_ALIGN(sizeof(struct qm_##type) * (num)); \ 1654 } while (0) 1655 1656 WARN_ON(!qm->qdma.dma); 1657 1658 if (qm->qp_num == 0) 1659 return -EINVAL; 1660 1661 if (qm->fun_type == QM_HW_PF) { 1662 ret = qm_dev_mem_reset(qm); 1663 if (ret) 1664 return ret; 1665 1666 ret = hisi_qm_set_vft(qm, 0, qm->qp_base, qm->qp_num); 1667 if (ret) 1668 return ret; 1669 } 1670 1671 QM_INIT_BUF(qm, eqe, QM_Q_DEPTH); 1672 QM_INIT_BUF(qm, aeqe, QM_Q_DEPTH); 1673 QM_INIT_BUF(qm, sqc, qm->qp_num); 1674 QM_INIT_BUF(qm, cqc, qm->qp_num); 1675 1676 dev_dbg(dev, "init qm buffer:\n" 1677 " eqe (%pK, %lx)\n" 1678 " aeqe (%pK, %lx)\n" 1679 " sqc (%pK, %lx)\n" 1680 " cqc (%pK, %lx)\n", 1681 qm->eqe, (unsigned long)qm->eqe_dma, 1682 qm->aeqe, (unsigned long)qm->aeqe_dma, 1683 qm->sqc, (unsigned long)qm->sqc_dma, 1684 qm->cqc, (unsigned long)qm->cqc_dma); 1685 1686 ret = qm_eq_ctx_cfg(qm); 1687 if (ret) 1688 return ret; 1689 1690 ret = qm_mb(qm, QM_MB_CMD_SQC_BT, qm->sqc_dma, 0, 0); 1691 if (ret) 1692 return ret; 1693 1694 ret = qm_mb(qm, QM_MB_CMD_CQC_BT, qm->cqc_dma, 0, 0); 1695 if (ret) 1696 return ret; 1697 1698 writel(0x0, qm->io_base + QM_VF_EQ_INT_MASK); 1699 writel(0x0, qm->io_base + QM_VF_AEQ_INT_MASK); 1700 1701 return 0; 1702 } 1703 1704 /** 1705 * hisi_qm_start() - start qm 1706 * @qm: The qm to be started. 1707 * 1708 * This function starts a qm, then we can allocate qp from this qm. 1709 */ 1710 int hisi_qm_start(struct hisi_qm *qm) 1711 { 1712 struct device *dev = &qm->pdev->dev; 1713 1714 dev_dbg(dev, "qm start with %d queue pairs\n", qm->qp_num); 1715 1716 if (!qm->qp_num) { 1717 dev_err(dev, "qp_num should not be 0\n"); 1718 return -EINVAL; 1719 } 1720 1721 if (!qm->qp_bitmap) { 1722 qm->qp_bitmap = devm_kcalloc(dev, BITS_TO_LONGS(qm->qp_num), 1723 sizeof(long), GFP_KERNEL); 1724 qm->qp_array = devm_kcalloc(dev, qm->qp_num, 1725 sizeof(struct hisi_qp *), 1726 GFP_KERNEL); 1727 if (!qm->qp_bitmap || !qm->qp_array) 1728 return -ENOMEM; 1729 } 1730 1731 if (!qm->use_dma_api) { 1732 dev_dbg(&qm->pdev->dev, "qm delay start\n"); 1733 return 0; 1734 } else if (!qm->qdma.va) { 1735 qm->qdma.size = QMC_ALIGN(sizeof(struct qm_eqe) * QM_Q_DEPTH) + 1736 QMC_ALIGN(sizeof(struct qm_aeqe) * QM_Q_DEPTH) + 1737 QMC_ALIGN(sizeof(struct qm_sqc) * qm->qp_num) + 1738 QMC_ALIGN(sizeof(struct qm_cqc) * qm->qp_num); 1739 qm->qdma.va = dma_alloc_coherent(dev, qm->qdma.size, 1740 &qm->qdma.dma, GFP_KERNEL); 1741 dev_dbg(dev, "allocate qm dma buf(va=%pK, dma=%pad, size=%zx)\n", 1742 qm->qdma.va, &qm->qdma.dma, qm->qdma.size); 1743 if (!qm->qdma.va) 1744 return -ENOMEM; 1745 } 1746 1747 return __hisi_qm_start(qm); 1748 } 1749 EXPORT_SYMBOL_GPL(hisi_qm_start); 1750 1751 /** 1752 * hisi_qm_stop() - Stop a qm. 1753 * @qm: The qm which will be stopped. 1754 * 1755 * This function stops qm and its qps, then qm can not accept request. 1756 * Related resources are not released at this state, we can use hisi_qm_start 1757 * to let qm start again. 1758 */ 1759 int hisi_qm_stop(struct hisi_qm *qm) 1760 { 1761 struct device *dev; 1762 struct hisi_qp *qp; 1763 int ret = 0, i; 1764 1765 if (!qm || !qm->pdev) { 1766 WARN_ON(1); 1767 return -EINVAL; 1768 } 1769 1770 dev = &qm->pdev->dev; 1771 1772 /* Mask eq and aeq irq */ 1773 writel(0x1, qm->io_base + QM_VF_EQ_INT_MASK); 1774 writel(0x1, qm->io_base + QM_VF_AEQ_INT_MASK); 1775 1776 /* Stop all qps belong to this qm */ 1777 for (i = 0; i < qm->qp_num; i++) { 1778 qp = qm->qp_array[i]; 1779 if (qp) { 1780 ret = hisi_qm_stop_qp(qp); 1781 if (ret < 0) { 1782 dev_err(dev, "Failed to stop qp%d!\n", i); 1783 return -EBUSY; 1784 } 1785 } 1786 } 1787 1788 if (qm->fun_type == QM_HW_PF) { 1789 ret = hisi_qm_set_vft(qm, 0, 0, 0); 1790 if (ret < 0) 1791 dev_err(dev, "Failed to set vft!\n"); 1792 } 1793 1794 return ret; 1795 } 1796 EXPORT_SYMBOL_GPL(hisi_qm_stop); 1797 1798 /** 1799 * hisi_qm_debug_init() - Initialize qm related debugfs files. 1800 * @qm: The qm for which we want to add debugfs files. 1801 * 1802 * Create qm related debugfs files. 1803 */ 1804 int hisi_qm_debug_init(struct hisi_qm *qm) 1805 { 1806 struct dentry *qm_d; 1807 int i, ret; 1808 1809 qm_d = debugfs_create_dir("qm", qm->debug.debug_root); 1810 qm->debug.qm_d = qm_d; 1811 1812 /* only show this in PF */ 1813 if (qm->fun_type == QM_HW_PF) 1814 for (i = CURRENT_Q; i < DEBUG_FILE_NUM; i++) 1815 if (qm_create_debugfs_file(qm, i)) { 1816 ret = -ENOENT; 1817 goto failed_to_create; 1818 } 1819 1820 debugfs_create_file("qm_regs", 0444, qm->debug.qm_d, qm, &qm_regs_fops); 1821 1822 return 0; 1823 1824 failed_to_create: 1825 debugfs_remove_recursive(qm_d); 1826 return ret; 1827 } 1828 EXPORT_SYMBOL_GPL(hisi_qm_debug_init); 1829 1830 /** 1831 * hisi_qm_debug_regs_clear() - clear qm debug related registers. 1832 * @qm: The qm for which we want to clear its debug registers. 1833 */ 1834 void hisi_qm_debug_regs_clear(struct hisi_qm *qm) 1835 { 1836 struct qm_dfx_registers *regs; 1837 int i; 1838 1839 /* clear current_q */ 1840 writel(0x0, qm->io_base + QM_DFX_SQE_CNT_VF_SQN); 1841 writel(0x0, qm->io_base + QM_DFX_CQE_CNT_VF_CQN); 1842 1843 /* 1844 * these registers are reading and clearing, so clear them after 1845 * reading them. 1846 */ 1847 writel(0x1, qm->io_base + QM_DFX_CNT_CLR_CE); 1848 1849 regs = qm_dfx_regs; 1850 for (i = 0; i < CNT_CYC_REGS_NUM; i++) { 1851 readl(qm->io_base + regs->reg_offset); 1852 regs++; 1853 } 1854 1855 writel(0x0, qm->io_base + QM_DFX_CNT_CLR_CE); 1856 } 1857 EXPORT_SYMBOL_GPL(hisi_qm_debug_regs_clear); 1858 1859 /** 1860 * hisi_qm_hw_error_init() - Configure qm hardware error report method. 1861 * @qm: The qm which we want to configure. 1862 * @ce: Bit mask of correctable error configure. 1863 * @nfe: Bit mask of non-fatal error configure. 1864 * @fe: Bit mask of fatal error configure. 1865 * @msi: Bit mask of error reported by message signal interrupt. 1866 * 1867 * Hardware errors of qm can be reported either by RAS interrupts which will 1868 * be handled by UEFI and then PCIe AER or by device MSI. User can configure 1869 * each error to use either of above two methods. For RAS interrupts, we can 1870 * configure an error as one of correctable error, non-fatal error or 1871 * fatal error. 1872 * 1873 * Bits indicating errors can be configured to ce, nfe, fe and msi to enable 1874 * related report methods. Error report will be masked if related error bit 1875 * does not configure. 1876 */ 1877 void hisi_qm_hw_error_init(struct hisi_qm *qm, u32 ce, u32 nfe, u32 fe, 1878 u32 msi) 1879 { 1880 if (!qm->ops->hw_error_init) { 1881 dev_err(&qm->pdev->dev, "QM doesn't support hw error handling!\n"); 1882 return; 1883 } 1884 1885 qm->ops->hw_error_init(qm, ce, nfe, fe, msi); 1886 } 1887 EXPORT_SYMBOL_GPL(hisi_qm_hw_error_init); 1888 1889 /** 1890 * hisi_qm_hw_error_handle() - Handle qm non-fatal hardware errors. 1891 * @qm: The qm which has non-fatal hardware errors. 1892 * 1893 * Accelerators use this function to handle qm non-fatal hardware errors. 1894 */ 1895 pci_ers_result_t hisi_qm_hw_error_handle(struct hisi_qm *qm) 1896 { 1897 if (!qm->ops->hw_error_handle) { 1898 dev_err(&qm->pdev->dev, "QM doesn't support hw error report!\n"); 1899 return PCI_ERS_RESULT_NONE; 1900 } 1901 1902 return qm->ops->hw_error_handle(qm); 1903 } 1904 EXPORT_SYMBOL_GPL(hisi_qm_hw_error_handle); 1905 1906 /** 1907 * hisi_qm_get_hw_version() - Get hardware version of a qm. 1908 * @pdev: The device which hardware version we want to get. 1909 * 1910 * This function gets the hardware version of a qm. Return QM_HW_UNKNOWN 1911 * if the hardware version is not supported. 1912 */ 1913 enum qm_hw_ver hisi_qm_get_hw_version(struct pci_dev *pdev) 1914 { 1915 switch (pdev->revision) { 1916 case QM_HW_V1: 1917 case QM_HW_V2: 1918 return pdev->revision; 1919 default: 1920 return QM_HW_UNKNOWN; 1921 } 1922 } 1923 EXPORT_SYMBOL_GPL(hisi_qm_get_hw_version); 1924 1925 MODULE_LICENSE("GPL v2"); 1926 MODULE_AUTHOR("Zhou Wang <wangzhou1@hisilicon.com>"); 1927 MODULE_DESCRIPTION("HiSilicon Accelerator queue manager driver"); 1928