1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018-2019 HiSilicon Limited. */ 3 #include <linux/acpi.h> 4 #include <linux/aer.h> 5 #include <linux/bitops.h> 6 #include <linux/debugfs.h> 7 #include <linux/init.h> 8 #include <linux/io.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/topology.h> 14 #include <linux/uacce.h> 15 #include "hpre.h" 16 17 #define HPRE_QM_ABNML_INT_MASK 0x100004 18 #define HPRE_CTRL_CNT_CLR_CE_BIT BIT(0) 19 #define HPRE_COMM_CNT_CLR_CE 0x0 20 #define HPRE_CTRL_CNT_CLR_CE 0x301000 21 #define HPRE_FSM_MAX_CNT 0x301008 22 #define HPRE_VFG_AXQOS 0x30100c 23 #define HPRE_VFG_AXCACHE 0x301010 24 #define HPRE_RDCHN_INI_CFG 0x301014 25 #define HPRE_AWUSR_FP_CFG 0x301018 26 #define HPRE_BD_ENDIAN 0x301020 27 #define HPRE_ECC_BYPASS 0x301024 28 #define HPRE_RAS_WIDTH_CFG 0x301028 29 #define HPRE_POISON_BYPASS 0x30102c 30 #define HPRE_BD_ARUSR_CFG 0x301030 31 #define HPRE_BD_AWUSR_CFG 0x301034 32 #define HPRE_TYPES_ENB 0x301038 33 #define HPRE_RSA_ENB BIT(0) 34 #define HPRE_ECC_ENB BIT(1) 35 #define HPRE_DATA_RUSER_CFG 0x30103c 36 #define HPRE_DATA_WUSER_CFG 0x301040 37 #define HPRE_INT_MASK 0x301400 38 #define HPRE_INT_STATUS 0x301800 39 #define HPRE_CORE_INT_ENABLE 0 40 #define HPRE_CORE_INT_DISABLE GENMASK(21, 0) 41 #define HPRE_RDCHN_INI_ST 0x301a00 42 #define HPRE_CLSTR_BASE 0x302000 43 #define HPRE_CORE_EN_OFFSET 0x04 44 #define HPRE_CORE_INI_CFG_OFFSET 0x20 45 #define HPRE_CORE_INI_STATUS_OFFSET 0x80 46 #define HPRE_CORE_HTBT_WARN_OFFSET 0x8c 47 #define HPRE_CORE_IS_SCHD_OFFSET 0x90 48 49 #define HPRE_RAS_CE_ENB 0x301410 50 #define HPRE_HAC_RAS_CE_ENABLE (BIT(0) | BIT(22) | BIT(23)) 51 #define HPRE_RAS_NFE_ENB 0x301414 52 #define HPRE_HAC_RAS_NFE_ENABLE 0x3ffffe 53 #define HPRE_RAS_FE_ENB 0x301418 54 #define HPRE_OOO_SHUTDOWN_SEL 0x301a3c 55 #define HPRE_HAC_RAS_FE_ENABLE 0 56 57 #define HPRE_CORE_ENB (HPRE_CLSTR_BASE + HPRE_CORE_EN_OFFSET) 58 #define HPRE_CORE_INI_CFG (HPRE_CLSTR_BASE + HPRE_CORE_INI_CFG_OFFSET) 59 #define HPRE_CORE_INI_STATUS (HPRE_CLSTR_BASE + HPRE_CORE_INI_STATUS_OFFSET) 60 #define HPRE_HAC_ECC1_CNT 0x301a04 61 #define HPRE_HAC_ECC2_CNT 0x301a08 62 #define HPRE_HAC_SOURCE_INT 0x301600 63 #define HPRE_CLSTR_ADDR_INTRVL 0x1000 64 #define HPRE_CLUSTER_INQURY 0x100 65 #define HPRE_CLSTR_ADDR_INQRY_RSLT 0x104 66 #define HPRE_TIMEOUT_ABNML_BIT 6 67 #define HPRE_PASID_EN_BIT 9 68 #define HPRE_REG_RD_INTVRL_US 10 69 #define HPRE_REG_RD_TMOUT_US 1000 70 #define HPRE_DBGFS_VAL_MAX_LEN 20 71 #define PCI_DEVICE_ID_HUAWEI_HPRE_PF 0xa258 72 #define HPRE_QM_USR_CFG_MASK GENMASK(31, 1) 73 #define HPRE_QM_AXI_CFG_MASK GENMASK(15, 0) 74 #define HPRE_QM_VFG_AX_MASK GENMASK(7, 0) 75 #define HPRE_BD_USR_MASK GENMASK(1, 0) 76 #define HPRE_CLUSTER_CORE_MASK_V2 GENMASK(3, 0) 77 #define HPRE_CLUSTER_CORE_MASK_V3 GENMASK(7, 0) 78 #define HPRE_PREFETCH_CFG 0x301130 79 #define HPRE_SVA_PREFTCH_DFX 0x30115C 80 #define HPRE_PREFETCH_ENABLE (~(BIT(0) | BIT(30))) 81 #define HPRE_PREFETCH_DISABLE BIT(30) 82 #define HPRE_SVA_DISABLE_READY (BIT(4) | BIT(8)) 83 84 /* clock gate */ 85 #define HPRE_CLKGATE_CTL 0x301a10 86 #define HPRE_PEH_CFG_AUTO_GATE 0x301a2c 87 #define HPRE_CLUSTER_DYN_CTL 0x302010 88 #define HPRE_CORE_SHB_CFG 0x302088 89 #define HPRE_CLKGATE_CTL_EN BIT(0) 90 #define HPRE_PEH_CFG_AUTO_GATE_EN BIT(0) 91 #define HPRE_CLUSTER_DYN_CTL_EN BIT(0) 92 #define HPRE_CORE_GATE_EN (BIT(30) | BIT(31)) 93 94 #define HPRE_AM_OOO_SHUTDOWN_ENB 0x301044 95 #define HPRE_AM_OOO_SHUTDOWN_ENABLE BIT(0) 96 #define HPRE_WR_MSI_PORT BIT(2) 97 98 #define HPRE_CORE_ECC_2BIT_ERR BIT(1) 99 #define HPRE_OOO_ECC_2BIT_ERR BIT(5) 100 101 #define HPRE_QM_BME_FLR BIT(7) 102 #define HPRE_QM_PM_FLR BIT(11) 103 #define HPRE_QM_SRIOV_FLR BIT(12) 104 105 #define HPRE_SHAPER_TYPE_RATE 640 106 #define HPRE_VIA_MSI_DSM 1 107 #define HPRE_SQE_MASK_OFFSET 8 108 #define HPRE_SQE_MASK_LEN 24 109 110 static const char hpre_name[] = "hisi_hpre"; 111 static struct dentry *hpre_debugfs_root; 112 static const struct pci_device_id hpre_dev_ids[] = { 113 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_HPRE_PF) }, 114 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_HPRE_VF) }, 115 { 0, } 116 }; 117 118 MODULE_DEVICE_TABLE(pci, hpre_dev_ids); 119 120 struct hpre_hw_error { 121 u32 int_msk; 122 const char *msg; 123 }; 124 125 static struct hisi_qm_list hpre_devices = { 126 .register_to_crypto = hpre_algs_register, 127 .unregister_from_crypto = hpre_algs_unregister, 128 }; 129 130 static const char * const hpre_debug_file_name[] = { 131 [HPRE_CLEAR_ENABLE] = "rdclr_en", 132 [HPRE_CLUSTER_CTRL] = "cluster_ctrl", 133 }; 134 135 static const struct hpre_hw_error hpre_hw_errors[] = { 136 { 137 .int_msk = BIT(0), 138 .msg = "core_ecc_1bit_err_int_set" 139 }, { 140 .int_msk = BIT(1), 141 .msg = "core_ecc_2bit_err_int_set" 142 }, { 143 .int_msk = BIT(2), 144 .msg = "dat_wb_poison_int_set" 145 }, { 146 .int_msk = BIT(3), 147 .msg = "dat_rd_poison_int_set" 148 }, { 149 .int_msk = BIT(4), 150 .msg = "bd_rd_poison_int_set" 151 }, { 152 .int_msk = BIT(5), 153 .msg = "ooo_ecc_2bit_err_int_set" 154 }, { 155 .int_msk = BIT(6), 156 .msg = "cluster1_shb_timeout_int_set" 157 }, { 158 .int_msk = BIT(7), 159 .msg = "cluster2_shb_timeout_int_set" 160 }, { 161 .int_msk = BIT(8), 162 .msg = "cluster3_shb_timeout_int_set" 163 }, { 164 .int_msk = BIT(9), 165 .msg = "cluster4_shb_timeout_int_set" 166 }, { 167 .int_msk = GENMASK(15, 10), 168 .msg = "ooo_rdrsp_err_int_set" 169 }, { 170 .int_msk = GENMASK(21, 16), 171 .msg = "ooo_wrrsp_err_int_set" 172 }, { 173 .int_msk = BIT(22), 174 .msg = "pt_rng_timeout_int_set" 175 }, { 176 .int_msk = BIT(23), 177 .msg = "sva_fsm_timeout_int_set" 178 }, { 179 /* sentinel */ 180 } 181 }; 182 183 static const u64 hpre_cluster_offsets[] = { 184 [HPRE_CLUSTER0] = 185 HPRE_CLSTR_BASE + HPRE_CLUSTER0 * HPRE_CLSTR_ADDR_INTRVL, 186 [HPRE_CLUSTER1] = 187 HPRE_CLSTR_BASE + HPRE_CLUSTER1 * HPRE_CLSTR_ADDR_INTRVL, 188 [HPRE_CLUSTER2] = 189 HPRE_CLSTR_BASE + HPRE_CLUSTER2 * HPRE_CLSTR_ADDR_INTRVL, 190 [HPRE_CLUSTER3] = 191 HPRE_CLSTR_BASE + HPRE_CLUSTER3 * HPRE_CLSTR_ADDR_INTRVL, 192 }; 193 194 static const struct debugfs_reg32 hpre_cluster_dfx_regs[] = { 195 {"CORES_EN_STATUS ", HPRE_CORE_EN_OFFSET}, 196 {"CORES_INI_CFG ", HPRE_CORE_INI_CFG_OFFSET}, 197 {"CORES_INI_STATUS ", HPRE_CORE_INI_STATUS_OFFSET}, 198 {"CORES_HTBT_WARN ", HPRE_CORE_HTBT_WARN_OFFSET}, 199 {"CORES_IS_SCHD ", HPRE_CORE_IS_SCHD_OFFSET}, 200 }; 201 202 static const struct debugfs_reg32 hpre_com_dfx_regs[] = { 203 {"READ_CLR_EN ", HPRE_CTRL_CNT_CLR_CE}, 204 {"AXQOS ", HPRE_VFG_AXQOS}, 205 {"AWUSR_CFG ", HPRE_AWUSR_FP_CFG}, 206 {"QM_ARUSR_MCFG1 ", QM_ARUSER_M_CFG_1}, 207 {"QM_AWUSR_MCFG1 ", QM_AWUSER_M_CFG_1}, 208 {"BD_ENDIAN ", HPRE_BD_ENDIAN}, 209 {"ECC_CHECK_CTRL ", HPRE_ECC_BYPASS}, 210 {"RAS_INT_WIDTH ", HPRE_RAS_WIDTH_CFG}, 211 {"POISON_BYPASS ", HPRE_POISON_BYPASS}, 212 {"BD_ARUSER ", HPRE_BD_ARUSR_CFG}, 213 {"BD_AWUSER ", HPRE_BD_AWUSR_CFG}, 214 {"DATA_ARUSER ", HPRE_DATA_RUSER_CFG}, 215 {"DATA_AWUSER ", HPRE_DATA_WUSER_CFG}, 216 {"INT_STATUS ", HPRE_INT_STATUS}, 217 }; 218 219 static const char *hpre_dfx_files[HPRE_DFX_FILE_NUM] = { 220 "send_cnt", 221 "recv_cnt", 222 "send_fail_cnt", 223 "send_busy_cnt", 224 "over_thrhld_cnt", 225 "overtime_thrhld", 226 "invalid_req_cnt" 227 }; 228 229 static const struct kernel_param_ops hpre_uacce_mode_ops = { 230 .set = uacce_mode_set, 231 .get = param_get_int, 232 }; 233 234 /* 235 * uacce_mode = 0 means hpre only register to crypto, 236 * uacce_mode = 1 means hpre both register to crypto and uacce. 237 */ 238 static u32 uacce_mode = UACCE_MODE_NOUACCE; 239 module_param_cb(uacce_mode, &hpre_uacce_mode_ops, &uacce_mode, 0444); 240 MODULE_PARM_DESC(uacce_mode, UACCE_MODE_DESC); 241 242 static int pf_q_num_set(const char *val, const struct kernel_param *kp) 243 { 244 return q_num_set(val, kp, PCI_DEVICE_ID_HUAWEI_HPRE_PF); 245 } 246 247 static const struct kernel_param_ops hpre_pf_q_num_ops = { 248 .set = pf_q_num_set, 249 .get = param_get_int, 250 }; 251 252 static u32 pf_q_num = HPRE_PF_DEF_Q_NUM; 253 module_param_cb(pf_q_num, &hpre_pf_q_num_ops, &pf_q_num, 0444); 254 MODULE_PARM_DESC(pf_q_num, "Number of queues in PF of CS(2-1024)"); 255 256 static const struct kernel_param_ops vfs_num_ops = { 257 .set = vfs_num_set, 258 .get = param_get_int, 259 }; 260 261 static u32 vfs_num; 262 module_param_cb(vfs_num, &vfs_num_ops, &vfs_num, 0444); 263 MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)"); 264 265 static inline int hpre_cluster_num(struct hisi_qm *qm) 266 { 267 return (qm->ver >= QM_HW_V3) ? HPRE_CLUSTERS_NUM_V3 : 268 HPRE_CLUSTERS_NUM_V2; 269 } 270 271 static inline int hpre_cluster_core_mask(struct hisi_qm *qm) 272 { 273 return (qm->ver >= QM_HW_V3) ? 274 HPRE_CLUSTER_CORE_MASK_V3 : HPRE_CLUSTER_CORE_MASK_V2; 275 } 276 277 struct hisi_qp *hpre_create_qp(u8 type) 278 { 279 int node = cpu_to_node(smp_processor_id()); 280 struct hisi_qp *qp = NULL; 281 int ret; 282 283 if (type != HPRE_V2_ALG_TYPE && type != HPRE_V3_ECC_ALG_TYPE) 284 return NULL; 285 286 /* 287 * type: 0 - RSA/DH. algorithm supported in V2, 288 * 1 - ECC algorithm in V3. 289 */ 290 ret = hisi_qm_alloc_qps_node(&hpre_devices, 1, type, node, &qp); 291 if (!ret) 292 return qp; 293 294 return NULL; 295 } 296 297 static void hpre_config_pasid(struct hisi_qm *qm) 298 { 299 u32 val1, val2; 300 301 if (qm->ver >= QM_HW_V3) 302 return; 303 304 val1 = readl_relaxed(qm->io_base + HPRE_DATA_RUSER_CFG); 305 val2 = readl_relaxed(qm->io_base + HPRE_DATA_WUSER_CFG); 306 if (qm->use_sva) { 307 val1 |= BIT(HPRE_PASID_EN_BIT); 308 val2 |= BIT(HPRE_PASID_EN_BIT); 309 } else { 310 val1 &= ~BIT(HPRE_PASID_EN_BIT); 311 val2 &= ~BIT(HPRE_PASID_EN_BIT); 312 } 313 writel_relaxed(val1, qm->io_base + HPRE_DATA_RUSER_CFG); 314 writel_relaxed(val2, qm->io_base + HPRE_DATA_WUSER_CFG); 315 } 316 317 static int hpre_cfg_by_dsm(struct hisi_qm *qm) 318 { 319 struct device *dev = &qm->pdev->dev; 320 union acpi_object *obj; 321 guid_t guid; 322 323 if (guid_parse("b06b81ab-0134-4a45-9b0c-483447b95fa7", &guid)) { 324 dev_err(dev, "Hpre GUID failed\n"); 325 return -EINVAL; 326 } 327 328 /* Switch over to MSI handling due to non-standard PCI implementation */ 329 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &guid, 330 0, HPRE_VIA_MSI_DSM, NULL); 331 if (!obj) { 332 dev_err(dev, "ACPI handle failed!\n"); 333 return -EIO; 334 } 335 336 ACPI_FREE(obj); 337 338 return 0; 339 } 340 341 static int hpre_set_cluster(struct hisi_qm *qm) 342 { 343 u32 cluster_core_mask = hpre_cluster_core_mask(qm); 344 u8 clusters_num = hpre_cluster_num(qm); 345 struct device *dev = &qm->pdev->dev; 346 unsigned long offset; 347 u32 val = 0; 348 int ret, i; 349 350 for (i = 0; i < clusters_num; i++) { 351 offset = i * HPRE_CLSTR_ADDR_INTRVL; 352 353 /* clusters initiating */ 354 writel(cluster_core_mask, 355 qm->io_base + offset + HPRE_CORE_ENB); 356 writel(0x1, qm->io_base + offset + HPRE_CORE_INI_CFG); 357 ret = readl_relaxed_poll_timeout(qm->io_base + offset + 358 HPRE_CORE_INI_STATUS, val, 359 ((val & cluster_core_mask) == 360 cluster_core_mask), 361 HPRE_REG_RD_INTVRL_US, 362 HPRE_REG_RD_TMOUT_US); 363 if (ret) { 364 dev_err(dev, 365 "cluster %d int st status timeout!\n", i); 366 return -ETIMEDOUT; 367 } 368 } 369 370 return 0; 371 } 372 373 /* 374 * For Kunpeng 920, we should disable FLR triggered by hardware (BME/PM/SRIOV). 375 * Or it may stay in D3 state when we bind and unbind hpre quickly, 376 * as it does FLR triggered by hardware. 377 */ 378 static void disable_flr_of_bme(struct hisi_qm *qm) 379 { 380 u32 val; 381 382 val = readl(qm->io_base + QM_PEH_AXUSER_CFG); 383 val &= ~(HPRE_QM_BME_FLR | HPRE_QM_SRIOV_FLR); 384 val |= HPRE_QM_PM_FLR; 385 writel(val, qm->io_base + QM_PEH_AXUSER_CFG); 386 writel(PEH_AXUSER_CFG_ENABLE, qm->io_base + QM_PEH_AXUSER_CFG_ENABLE); 387 } 388 389 static void hpre_open_sva_prefetch(struct hisi_qm *qm) 390 { 391 u32 val; 392 int ret; 393 394 if (qm->ver < QM_HW_V3) 395 return; 396 397 /* Enable prefetch */ 398 val = readl_relaxed(qm->io_base + HPRE_PREFETCH_CFG); 399 val &= HPRE_PREFETCH_ENABLE; 400 writel(val, qm->io_base + HPRE_PREFETCH_CFG); 401 402 ret = readl_relaxed_poll_timeout(qm->io_base + HPRE_PREFETCH_CFG, 403 val, !(val & HPRE_PREFETCH_DISABLE), 404 HPRE_REG_RD_INTVRL_US, 405 HPRE_REG_RD_TMOUT_US); 406 if (ret) 407 pci_err(qm->pdev, "failed to open sva prefetch\n"); 408 } 409 410 static void hpre_close_sva_prefetch(struct hisi_qm *qm) 411 { 412 u32 val; 413 int ret; 414 415 if (qm->ver < QM_HW_V3) 416 return; 417 418 val = readl_relaxed(qm->io_base + HPRE_PREFETCH_CFG); 419 val |= HPRE_PREFETCH_DISABLE; 420 writel(val, qm->io_base + HPRE_PREFETCH_CFG); 421 422 ret = readl_relaxed_poll_timeout(qm->io_base + HPRE_SVA_PREFTCH_DFX, 423 val, !(val & HPRE_SVA_DISABLE_READY), 424 HPRE_REG_RD_INTVRL_US, 425 HPRE_REG_RD_TMOUT_US); 426 if (ret) 427 pci_err(qm->pdev, "failed to close sva prefetch\n"); 428 } 429 430 static void hpre_enable_clock_gate(struct hisi_qm *qm) 431 { 432 u32 val; 433 434 if (qm->ver < QM_HW_V3) 435 return; 436 437 val = readl(qm->io_base + HPRE_CLKGATE_CTL); 438 val |= HPRE_CLKGATE_CTL_EN; 439 writel(val, qm->io_base + HPRE_CLKGATE_CTL); 440 441 val = readl(qm->io_base + HPRE_PEH_CFG_AUTO_GATE); 442 val |= HPRE_PEH_CFG_AUTO_GATE_EN; 443 writel(val, qm->io_base + HPRE_PEH_CFG_AUTO_GATE); 444 445 val = readl(qm->io_base + HPRE_CLUSTER_DYN_CTL); 446 val |= HPRE_CLUSTER_DYN_CTL_EN; 447 writel(val, qm->io_base + HPRE_CLUSTER_DYN_CTL); 448 449 val = readl_relaxed(qm->io_base + HPRE_CORE_SHB_CFG); 450 val |= HPRE_CORE_GATE_EN; 451 writel(val, qm->io_base + HPRE_CORE_SHB_CFG); 452 } 453 454 static void hpre_disable_clock_gate(struct hisi_qm *qm) 455 { 456 u32 val; 457 458 if (qm->ver < QM_HW_V3) 459 return; 460 461 val = readl(qm->io_base + HPRE_CLKGATE_CTL); 462 val &= ~HPRE_CLKGATE_CTL_EN; 463 writel(val, qm->io_base + HPRE_CLKGATE_CTL); 464 465 val = readl(qm->io_base + HPRE_PEH_CFG_AUTO_GATE); 466 val &= ~HPRE_PEH_CFG_AUTO_GATE_EN; 467 writel(val, qm->io_base + HPRE_PEH_CFG_AUTO_GATE); 468 469 val = readl(qm->io_base + HPRE_CLUSTER_DYN_CTL); 470 val &= ~HPRE_CLUSTER_DYN_CTL_EN; 471 writel(val, qm->io_base + HPRE_CLUSTER_DYN_CTL); 472 473 val = readl_relaxed(qm->io_base + HPRE_CORE_SHB_CFG); 474 val &= ~HPRE_CORE_GATE_EN; 475 writel(val, qm->io_base + HPRE_CORE_SHB_CFG); 476 } 477 478 static int hpre_set_user_domain_and_cache(struct hisi_qm *qm) 479 { 480 struct device *dev = &qm->pdev->dev; 481 u32 val; 482 int ret; 483 484 /* disabel dynamic clock gate before sram init */ 485 hpre_disable_clock_gate(qm); 486 487 writel(HPRE_QM_USR_CFG_MASK, qm->io_base + QM_ARUSER_M_CFG_ENABLE); 488 writel(HPRE_QM_USR_CFG_MASK, qm->io_base + QM_AWUSER_M_CFG_ENABLE); 489 writel_relaxed(HPRE_QM_AXI_CFG_MASK, qm->io_base + QM_AXI_M_CFG); 490 491 /* HPRE need more time, we close this interrupt */ 492 val = readl_relaxed(qm->io_base + HPRE_QM_ABNML_INT_MASK); 493 val |= BIT(HPRE_TIMEOUT_ABNML_BIT); 494 writel_relaxed(val, qm->io_base + HPRE_QM_ABNML_INT_MASK); 495 496 if (qm->ver >= QM_HW_V3) 497 writel(HPRE_RSA_ENB | HPRE_ECC_ENB, 498 qm->io_base + HPRE_TYPES_ENB); 499 else 500 writel(HPRE_RSA_ENB, qm->io_base + HPRE_TYPES_ENB); 501 502 writel(HPRE_QM_VFG_AX_MASK, qm->io_base + HPRE_VFG_AXCACHE); 503 writel(0x0, qm->io_base + HPRE_BD_ENDIAN); 504 writel(0x0, qm->io_base + HPRE_INT_MASK); 505 writel(0x0, qm->io_base + HPRE_POISON_BYPASS); 506 writel(0x0, qm->io_base + HPRE_COMM_CNT_CLR_CE); 507 writel(0x0, qm->io_base + HPRE_ECC_BYPASS); 508 509 writel(HPRE_BD_USR_MASK, qm->io_base + HPRE_BD_ARUSR_CFG); 510 writel(HPRE_BD_USR_MASK, qm->io_base + HPRE_BD_AWUSR_CFG); 511 writel(0x1, qm->io_base + HPRE_RDCHN_INI_CFG); 512 ret = readl_relaxed_poll_timeout(qm->io_base + HPRE_RDCHN_INI_ST, val, 513 val & BIT(0), 514 HPRE_REG_RD_INTVRL_US, 515 HPRE_REG_RD_TMOUT_US); 516 if (ret) { 517 dev_err(dev, "read rd channel timeout fail!\n"); 518 return -ETIMEDOUT; 519 } 520 521 ret = hpre_set_cluster(qm); 522 if (ret) 523 return -ETIMEDOUT; 524 525 /* This setting is only needed by Kunpeng 920. */ 526 if (qm->ver == QM_HW_V2) { 527 ret = hpre_cfg_by_dsm(qm); 528 if (ret) 529 return ret; 530 531 disable_flr_of_bme(qm); 532 } 533 534 /* Config data buffer pasid needed by Kunpeng 920 */ 535 hpre_config_pasid(qm); 536 537 hpre_enable_clock_gate(qm); 538 539 return ret; 540 } 541 542 static void hpre_cnt_regs_clear(struct hisi_qm *qm) 543 { 544 u8 clusters_num = hpre_cluster_num(qm); 545 unsigned long offset; 546 int i; 547 548 /* clear clusterX/cluster_ctrl */ 549 for (i = 0; i < clusters_num; i++) { 550 offset = HPRE_CLSTR_BASE + i * HPRE_CLSTR_ADDR_INTRVL; 551 writel(0x0, qm->io_base + offset + HPRE_CLUSTER_INQURY); 552 } 553 554 /* clear rdclr_en */ 555 writel(0x0, qm->io_base + HPRE_CTRL_CNT_CLR_CE); 556 557 hisi_qm_debug_regs_clear(qm); 558 } 559 560 static void hpre_master_ooo_ctrl(struct hisi_qm *qm, bool enable) 561 { 562 u32 val1, val2; 563 564 val1 = readl(qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB); 565 if (enable) { 566 val1 |= HPRE_AM_OOO_SHUTDOWN_ENABLE; 567 val2 = HPRE_HAC_RAS_NFE_ENABLE; 568 } else { 569 val1 &= ~HPRE_AM_OOO_SHUTDOWN_ENABLE; 570 val2 = 0x0; 571 } 572 573 if (qm->ver > QM_HW_V2) 574 writel(val2, qm->io_base + HPRE_OOO_SHUTDOWN_SEL); 575 576 writel(val1, qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB); 577 } 578 579 static void hpre_hw_error_disable(struct hisi_qm *qm) 580 { 581 /* disable hpre hw error interrupts */ 582 writel(HPRE_CORE_INT_DISABLE, qm->io_base + HPRE_INT_MASK); 583 584 /* disable HPRE block master OOO when nfe occurs on Kunpeng930 */ 585 hpre_master_ooo_ctrl(qm, false); 586 } 587 588 static void hpre_hw_error_enable(struct hisi_qm *qm) 589 { 590 /* clear HPRE hw error source if having */ 591 writel(HPRE_CORE_INT_DISABLE, qm->io_base + HPRE_HAC_SOURCE_INT); 592 593 /* configure error type */ 594 writel(HPRE_HAC_RAS_CE_ENABLE, qm->io_base + HPRE_RAS_CE_ENB); 595 writel(HPRE_HAC_RAS_NFE_ENABLE, qm->io_base + HPRE_RAS_NFE_ENB); 596 writel(HPRE_HAC_RAS_FE_ENABLE, qm->io_base + HPRE_RAS_FE_ENB); 597 598 /* enable HPRE block master OOO when nfe occurs on Kunpeng930 */ 599 hpre_master_ooo_ctrl(qm, true); 600 601 /* enable hpre hw error interrupts */ 602 writel(HPRE_CORE_INT_ENABLE, qm->io_base + HPRE_INT_MASK); 603 } 604 605 static inline struct hisi_qm *hpre_file_to_qm(struct hpre_debugfs_file *file) 606 { 607 struct hpre *hpre = container_of(file->debug, struct hpre, debug); 608 609 return &hpre->qm; 610 } 611 612 static u32 hpre_clear_enable_read(struct hpre_debugfs_file *file) 613 { 614 struct hisi_qm *qm = hpre_file_to_qm(file); 615 616 return readl(qm->io_base + HPRE_CTRL_CNT_CLR_CE) & 617 HPRE_CTRL_CNT_CLR_CE_BIT; 618 } 619 620 static int hpre_clear_enable_write(struct hpre_debugfs_file *file, u32 val) 621 { 622 struct hisi_qm *qm = hpre_file_to_qm(file); 623 u32 tmp; 624 625 if (val != 1 && val != 0) 626 return -EINVAL; 627 628 tmp = (readl(qm->io_base + HPRE_CTRL_CNT_CLR_CE) & 629 ~HPRE_CTRL_CNT_CLR_CE_BIT) | val; 630 writel(tmp, qm->io_base + HPRE_CTRL_CNT_CLR_CE); 631 632 return 0; 633 } 634 635 static u32 hpre_cluster_inqry_read(struct hpre_debugfs_file *file) 636 { 637 struct hisi_qm *qm = hpre_file_to_qm(file); 638 int cluster_index = file->index - HPRE_CLUSTER_CTRL; 639 unsigned long offset = HPRE_CLSTR_BASE + 640 cluster_index * HPRE_CLSTR_ADDR_INTRVL; 641 642 return readl(qm->io_base + offset + HPRE_CLSTR_ADDR_INQRY_RSLT); 643 } 644 645 static int hpre_cluster_inqry_write(struct hpre_debugfs_file *file, u32 val) 646 { 647 struct hisi_qm *qm = hpre_file_to_qm(file); 648 int cluster_index = file->index - HPRE_CLUSTER_CTRL; 649 unsigned long offset = HPRE_CLSTR_BASE + cluster_index * 650 HPRE_CLSTR_ADDR_INTRVL; 651 652 writel(val, qm->io_base + offset + HPRE_CLUSTER_INQURY); 653 654 return 0; 655 } 656 657 static ssize_t hpre_ctrl_debug_read(struct file *filp, char __user *buf, 658 size_t count, loff_t *pos) 659 { 660 struct hpre_debugfs_file *file = filp->private_data; 661 struct hisi_qm *qm = hpre_file_to_qm(file); 662 char tbuf[HPRE_DBGFS_VAL_MAX_LEN]; 663 u32 val; 664 int ret; 665 666 ret = hisi_qm_get_dfx_access(qm); 667 if (ret) 668 return ret; 669 670 spin_lock_irq(&file->lock); 671 switch (file->type) { 672 case HPRE_CLEAR_ENABLE: 673 val = hpre_clear_enable_read(file); 674 break; 675 case HPRE_CLUSTER_CTRL: 676 val = hpre_cluster_inqry_read(file); 677 break; 678 default: 679 goto err_input; 680 } 681 spin_unlock_irq(&file->lock); 682 683 hisi_qm_put_dfx_access(qm); 684 ret = snprintf(tbuf, HPRE_DBGFS_VAL_MAX_LEN, "%u\n", val); 685 return simple_read_from_buffer(buf, count, pos, tbuf, ret); 686 687 err_input: 688 spin_unlock_irq(&file->lock); 689 hisi_qm_put_dfx_access(qm); 690 return -EINVAL; 691 } 692 693 static ssize_t hpre_ctrl_debug_write(struct file *filp, const char __user *buf, 694 size_t count, loff_t *pos) 695 { 696 struct hpre_debugfs_file *file = filp->private_data; 697 struct hisi_qm *qm = hpre_file_to_qm(file); 698 char tbuf[HPRE_DBGFS_VAL_MAX_LEN]; 699 unsigned long val; 700 int len, ret; 701 702 if (*pos != 0) 703 return 0; 704 705 if (count >= HPRE_DBGFS_VAL_MAX_LEN) 706 return -ENOSPC; 707 708 len = simple_write_to_buffer(tbuf, HPRE_DBGFS_VAL_MAX_LEN - 1, 709 pos, buf, count); 710 if (len < 0) 711 return len; 712 713 tbuf[len] = '\0'; 714 if (kstrtoul(tbuf, 0, &val)) 715 return -EFAULT; 716 717 ret = hisi_qm_get_dfx_access(qm); 718 if (ret) 719 return ret; 720 721 spin_lock_irq(&file->lock); 722 switch (file->type) { 723 case HPRE_CLEAR_ENABLE: 724 ret = hpre_clear_enable_write(file, val); 725 if (ret) 726 goto err_input; 727 break; 728 case HPRE_CLUSTER_CTRL: 729 ret = hpre_cluster_inqry_write(file, val); 730 if (ret) 731 goto err_input; 732 break; 733 default: 734 ret = -EINVAL; 735 goto err_input; 736 } 737 738 ret = count; 739 740 err_input: 741 spin_unlock_irq(&file->lock); 742 hisi_qm_put_dfx_access(qm); 743 return ret; 744 } 745 746 static const struct file_operations hpre_ctrl_debug_fops = { 747 .owner = THIS_MODULE, 748 .open = simple_open, 749 .read = hpre_ctrl_debug_read, 750 .write = hpre_ctrl_debug_write, 751 }; 752 753 static int hpre_debugfs_atomic64_get(void *data, u64 *val) 754 { 755 struct hpre_dfx *dfx_item = data; 756 757 *val = atomic64_read(&dfx_item->value); 758 759 return 0; 760 } 761 762 static int hpre_debugfs_atomic64_set(void *data, u64 val) 763 { 764 struct hpre_dfx *dfx_item = data; 765 struct hpre_dfx *hpre_dfx = NULL; 766 767 if (dfx_item->type == HPRE_OVERTIME_THRHLD) { 768 hpre_dfx = dfx_item - HPRE_OVERTIME_THRHLD; 769 atomic64_set(&hpre_dfx[HPRE_OVER_THRHLD_CNT].value, 0); 770 } else if (val) { 771 return -EINVAL; 772 } 773 774 atomic64_set(&dfx_item->value, val); 775 776 return 0; 777 } 778 779 DEFINE_DEBUGFS_ATTRIBUTE(hpre_atomic64_ops, hpre_debugfs_atomic64_get, 780 hpre_debugfs_atomic64_set, "%llu\n"); 781 782 static int hpre_com_regs_show(struct seq_file *s, void *unused) 783 { 784 hisi_qm_regs_dump(s, s->private); 785 786 return 0; 787 } 788 789 DEFINE_SHOW_ATTRIBUTE(hpre_com_regs); 790 791 static int hpre_cluster_regs_show(struct seq_file *s, void *unused) 792 { 793 hisi_qm_regs_dump(s, s->private); 794 795 return 0; 796 } 797 798 DEFINE_SHOW_ATTRIBUTE(hpre_cluster_regs); 799 800 static int hpre_create_debugfs_file(struct hisi_qm *qm, struct dentry *dir, 801 enum hpre_ctrl_dbgfs_file type, int indx) 802 { 803 struct hpre *hpre = container_of(qm, struct hpre, qm); 804 struct hpre_debug *dbg = &hpre->debug; 805 struct dentry *file_dir; 806 807 if (dir) 808 file_dir = dir; 809 else 810 file_dir = qm->debug.debug_root; 811 812 if (type >= HPRE_DEBUG_FILE_NUM) 813 return -EINVAL; 814 815 spin_lock_init(&dbg->files[indx].lock); 816 dbg->files[indx].debug = dbg; 817 dbg->files[indx].type = type; 818 dbg->files[indx].index = indx; 819 debugfs_create_file(hpre_debug_file_name[type], 0600, file_dir, 820 dbg->files + indx, &hpre_ctrl_debug_fops); 821 822 return 0; 823 } 824 825 static int hpre_pf_comm_regs_debugfs_init(struct hisi_qm *qm) 826 { 827 struct device *dev = &qm->pdev->dev; 828 struct debugfs_regset32 *regset; 829 830 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 831 if (!regset) 832 return -ENOMEM; 833 834 regset->regs = hpre_com_dfx_regs; 835 regset->nregs = ARRAY_SIZE(hpre_com_dfx_regs); 836 regset->base = qm->io_base; 837 regset->dev = dev; 838 839 debugfs_create_file("regs", 0444, qm->debug.debug_root, 840 regset, &hpre_com_regs_fops); 841 842 return 0; 843 } 844 845 static int hpre_cluster_debugfs_init(struct hisi_qm *qm) 846 { 847 u8 clusters_num = hpre_cluster_num(qm); 848 struct device *dev = &qm->pdev->dev; 849 char buf[HPRE_DBGFS_VAL_MAX_LEN]; 850 struct debugfs_regset32 *regset; 851 struct dentry *tmp_d; 852 int i, ret; 853 854 for (i = 0; i < clusters_num; i++) { 855 ret = snprintf(buf, HPRE_DBGFS_VAL_MAX_LEN, "cluster%d", i); 856 if (ret < 0) 857 return -EINVAL; 858 tmp_d = debugfs_create_dir(buf, qm->debug.debug_root); 859 860 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 861 if (!regset) 862 return -ENOMEM; 863 864 regset->regs = hpre_cluster_dfx_regs; 865 regset->nregs = ARRAY_SIZE(hpre_cluster_dfx_regs); 866 regset->base = qm->io_base + hpre_cluster_offsets[i]; 867 regset->dev = dev; 868 869 debugfs_create_file("regs", 0444, tmp_d, regset, 870 &hpre_cluster_regs_fops); 871 ret = hpre_create_debugfs_file(qm, tmp_d, HPRE_CLUSTER_CTRL, 872 i + HPRE_CLUSTER_CTRL); 873 if (ret) 874 return ret; 875 } 876 877 return 0; 878 } 879 880 static int hpre_ctrl_debug_init(struct hisi_qm *qm) 881 { 882 int ret; 883 884 ret = hpre_create_debugfs_file(qm, NULL, HPRE_CLEAR_ENABLE, 885 HPRE_CLEAR_ENABLE); 886 if (ret) 887 return ret; 888 889 ret = hpre_pf_comm_regs_debugfs_init(qm); 890 if (ret) 891 return ret; 892 893 return hpre_cluster_debugfs_init(qm); 894 } 895 896 static void hpre_dfx_debug_init(struct hisi_qm *qm) 897 { 898 struct hpre *hpre = container_of(qm, struct hpre, qm); 899 struct hpre_dfx *dfx = hpre->debug.dfx; 900 struct dentry *parent; 901 int i; 902 903 parent = debugfs_create_dir("hpre_dfx", qm->debug.debug_root); 904 for (i = 0; i < HPRE_DFX_FILE_NUM; i++) { 905 dfx[i].type = i; 906 debugfs_create_file(hpre_dfx_files[i], 0644, parent, &dfx[i], 907 &hpre_atomic64_ops); 908 } 909 } 910 911 static int hpre_debugfs_init(struct hisi_qm *qm) 912 { 913 struct device *dev = &qm->pdev->dev; 914 int ret; 915 916 qm->debug.debug_root = debugfs_create_dir(dev_name(dev), 917 hpre_debugfs_root); 918 919 qm->debug.sqe_mask_offset = HPRE_SQE_MASK_OFFSET; 920 qm->debug.sqe_mask_len = HPRE_SQE_MASK_LEN; 921 hisi_qm_debug_init(qm); 922 923 if (qm->pdev->device == PCI_DEVICE_ID_HUAWEI_HPRE_PF) { 924 ret = hpre_ctrl_debug_init(qm); 925 if (ret) 926 goto failed_to_create; 927 } 928 929 hpre_dfx_debug_init(qm); 930 931 return 0; 932 933 failed_to_create: 934 debugfs_remove_recursive(qm->debug.debug_root); 935 return ret; 936 } 937 938 static void hpre_debugfs_exit(struct hisi_qm *qm) 939 { 940 debugfs_remove_recursive(qm->debug.debug_root); 941 } 942 943 static int hpre_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) 944 { 945 if (pdev->revision == QM_HW_V1) { 946 pci_warn(pdev, "HPRE version 1 is not supported!\n"); 947 return -EINVAL; 948 } 949 950 if (pdev->revision >= QM_HW_V3) 951 qm->algs = "rsa\ndh\necdh\nx25519\nx448\necdsa\nsm2"; 952 else 953 qm->algs = "rsa\ndh"; 954 qm->mode = uacce_mode; 955 qm->pdev = pdev; 956 qm->ver = pdev->revision; 957 qm->sqe_size = HPRE_SQE_SIZE; 958 qm->dev_name = hpre_name; 959 960 qm->fun_type = (pdev->device == PCI_DEVICE_ID_HUAWEI_HPRE_PF) ? 961 QM_HW_PF : QM_HW_VF; 962 if (qm->fun_type == QM_HW_PF) { 963 qm->qp_base = HPRE_PF_DEF_Q_BASE; 964 qm->qp_num = pf_q_num; 965 qm->debug.curr_qm_qp_num = pf_q_num; 966 qm->qm_list = &hpre_devices; 967 } 968 969 return hisi_qm_init(qm); 970 } 971 972 static void hpre_log_hw_error(struct hisi_qm *qm, u32 err_sts) 973 { 974 const struct hpre_hw_error *err = hpre_hw_errors; 975 struct device *dev = &qm->pdev->dev; 976 977 while (err->msg) { 978 if (err->int_msk & err_sts) 979 dev_warn(dev, "%s [error status=0x%x] found\n", 980 err->msg, err->int_msk); 981 err++; 982 } 983 } 984 985 static u32 hpre_get_hw_err_status(struct hisi_qm *qm) 986 { 987 return readl(qm->io_base + HPRE_INT_STATUS); 988 } 989 990 static void hpre_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts) 991 { 992 writel(err_sts, qm->io_base + HPRE_HAC_SOURCE_INT); 993 } 994 995 static void hpre_open_axi_master_ooo(struct hisi_qm *qm) 996 { 997 u32 value; 998 999 value = readl(qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB); 1000 writel(value & ~HPRE_AM_OOO_SHUTDOWN_ENABLE, 1001 qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB); 1002 writel(value | HPRE_AM_OOO_SHUTDOWN_ENABLE, 1003 qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB); 1004 } 1005 1006 static void hpre_err_info_init(struct hisi_qm *qm) 1007 { 1008 struct hisi_qm_err_info *err_info = &qm->err_info; 1009 1010 err_info->ce = QM_BASE_CE; 1011 err_info->fe = 0; 1012 err_info->ecc_2bits_mask = HPRE_CORE_ECC_2BIT_ERR | 1013 HPRE_OOO_ECC_2BIT_ERR; 1014 err_info->dev_ce_mask = HPRE_HAC_RAS_CE_ENABLE; 1015 err_info->msi_wr_port = HPRE_WR_MSI_PORT; 1016 err_info->acpi_rst = "HRST"; 1017 err_info->nfe = QM_BASE_NFE | QM_ACC_DO_TASK_TIMEOUT; 1018 } 1019 1020 static const struct hisi_qm_err_ini hpre_err_ini = { 1021 .hw_init = hpre_set_user_domain_and_cache, 1022 .hw_err_enable = hpre_hw_error_enable, 1023 .hw_err_disable = hpre_hw_error_disable, 1024 .get_dev_hw_err_status = hpre_get_hw_err_status, 1025 .clear_dev_hw_err_status = hpre_clear_hw_err_status, 1026 .log_dev_hw_err = hpre_log_hw_error, 1027 .open_axi_master_ooo = hpre_open_axi_master_ooo, 1028 .open_sva_prefetch = hpre_open_sva_prefetch, 1029 .close_sva_prefetch = hpre_close_sva_prefetch, 1030 .err_info_init = hpre_err_info_init, 1031 }; 1032 1033 static int hpre_pf_probe_init(struct hpre *hpre) 1034 { 1035 struct hisi_qm *qm = &hpre->qm; 1036 int ret; 1037 1038 ret = hpre_set_user_domain_and_cache(qm); 1039 if (ret) 1040 return ret; 1041 1042 hpre_open_sva_prefetch(qm); 1043 1044 qm->err_ini = &hpre_err_ini; 1045 qm->err_ini->err_info_init(qm); 1046 hisi_qm_dev_err_init(qm); 1047 1048 return 0; 1049 } 1050 1051 static int hpre_probe_init(struct hpre *hpre) 1052 { 1053 u32 type_rate = HPRE_SHAPER_TYPE_RATE; 1054 struct hisi_qm *qm = &hpre->qm; 1055 int ret; 1056 1057 if (qm->fun_type == QM_HW_PF) { 1058 ret = hpre_pf_probe_init(hpre); 1059 if (ret) 1060 return ret; 1061 /* Enable shaper type 0 */ 1062 if (qm->ver >= QM_HW_V3) { 1063 type_rate |= QM_SHAPER_ENABLE; 1064 qm->type_rate = type_rate; 1065 } 1066 } 1067 1068 return 0; 1069 } 1070 1071 static int hpre_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1072 { 1073 struct hisi_qm *qm; 1074 struct hpre *hpre; 1075 int ret; 1076 1077 hpre = devm_kzalloc(&pdev->dev, sizeof(*hpre), GFP_KERNEL); 1078 if (!hpre) 1079 return -ENOMEM; 1080 1081 qm = &hpre->qm; 1082 ret = hpre_qm_init(qm, pdev); 1083 if (ret) { 1084 pci_err(pdev, "Failed to init HPRE QM (%d)!\n", ret); 1085 return ret; 1086 } 1087 1088 ret = hpre_probe_init(hpre); 1089 if (ret) { 1090 pci_err(pdev, "Failed to probe (%d)!\n", ret); 1091 goto err_with_qm_init; 1092 } 1093 1094 ret = hisi_qm_start(qm); 1095 if (ret) 1096 goto err_with_err_init; 1097 1098 ret = hpre_debugfs_init(qm); 1099 if (ret) 1100 dev_warn(&pdev->dev, "init debugfs fail!\n"); 1101 1102 ret = hisi_qm_alg_register(qm, &hpre_devices); 1103 if (ret < 0) { 1104 pci_err(pdev, "fail to register algs to crypto!\n"); 1105 goto err_with_qm_start; 1106 } 1107 1108 if (qm->uacce) { 1109 ret = uacce_register(qm->uacce); 1110 if (ret) { 1111 pci_err(pdev, "failed to register uacce (%d)!\n", ret); 1112 goto err_with_alg_register; 1113 } 1114 } 1115 1116 if (qm->fun_type == QM_HW_PF && vfs_num) { 1117 ret = hisi_qm_sriov_enable(pdev, vfs_num); 1118 if (ret < 0) 1119 goto err_with_alg_register; 1120 } 1121 1122 hisi_qm_pm_init(qm); 1123 1124 return 0; 1125 1126 err_with_alg_register: 1127 hisi_qm_alg_unregister(qm, &hpre_devices); 1128 1129 err_with_qm_start: 1130 hpre_debugfs_exit(qm); 1131 hisi_qm_stop(qm, QM_NORMAL); 1132 1133 err_with_err_init: 1134 hisi_qm_dev_err_uninit(qm); 1135 1136 err_with_qm_init: 1137 hisi_qm_uninit(qm); 1138 1139 return ret; 1140 } 1141 1142 static void hpre_remove(struct pci_dev *pdev) 1143 { 1144 struct hisi_qm *qm = pci_get_drvdata(pdev); 1145 int ret; 1146 1147 hisi_qm_pm_uninit(qm); 1148 hisi_qm_wait_task_finish(qm, &hpre_devices); 1149 hisi_qm_alg_unregister(qm, &hpre_devices); 1150 if (qm->fun_type == QM_HW_PF && qm->vfs_num) { 1151 ret = hisi_qm_sriov_disable(pdev, true); 1152 if (ret) { 1153 pci_err(pdev, "Disable SRIOV fail!\n"); 1154 return; 1155 } 1156 } 1157 1158 hpre_debugfs_exit(qm); 1159 hisi_qm_stop(qm, QM_NORMAL); 1160 1161 if (qm->fun_type == QM_HW_PF) { 1162 hpre_cnt_regs_clear(qm); 1163 qm->debug.curr_qm_qp_num = 0; 1164 hisi_qm_dev_err_uninit(qm); 1165 } 1166 1167 hisi_qm_uninit(qm); 1168 } 1169 1170 static const struct dev_pm_ops hpre_pm_ops = { 1171 SET_RUNTIME_PM_OPS(hisi_qm_suspend, hisi_qm_resume, NULL) 1172 }; 1173 1174 static const struct pci_error_handlers hpre_err_handler = { 1175 .error_detected = hisi_qm_dev_err_detected, 1176 .slot_reset = hisi_qm_dev_slot_reset, 1177 .reset_prepare = hisi_qm_reset_prepare, 1178 .reset_done = hisi_qm_reset_done, 1179 }; 1180 1181 static struct pci_driver hpre_pci_driver = { 1182 .name = hpre_name, 1183 .id_table = hpre_dev_ids, 1184 .probe = hpre_probe, 1185 .remove = hpre_remove, 1186 .sriov_configure = IS_ENABLED(CONFIG_PCI_IOV) ? 1187 hisi_qm_sriov_configure : NULL, 1188 .err_handler = &hpre_err_handler, 1189 .shutdown = hisi_qm_dev_shutdown, 1190 .driver.pm = &hpre_pm_ops, 1191 }; 1192 1193 struct pci_driver *hisi_hpre_get_pf_driver(void) 1194 { 1195 return &hpre_pci_driver; 1196 } 1197 EXPORT_SYMBOL_GPL(hisi_hpre_get_pf_driver); 1198 1199 static void hpre_register_debugfs(void) 1200 { 1201 if (!debugfs_initialized()) 1202 return; 1203 1204 hpre_debugfs_root = debugfs_create_dir(hpre_name, NULL); 1205 } 1206 1207 static void hpre_unregister_debugfs(void) 1208 { 1209 debugfs_remove_recursive(hpre_debugfs_root); 1210 } 1211 1212 static int __init hpre_init(void) 1213 { 1214 int ret; 1215 1216 hisi_qm_init_list(&hpre_devices); 1217 hpre_register_debugfs(); 1218 1219 ret = pci_register_driver(&hpre_pci_driver); 1220 if (ret) { 1221 hpre_unregister_debugfs(); 1222 pr_err("hpre: can't register hisi hpre driver.\n"); 1223 } 1224 1225 return ret; 1226 } 1227 1228 static void __exit hpre_exit(void) 1229 { 1230 pci_unregister_driver(&hpre_pci_driver); 1231 hpre_unregister_debugfs(); 1232 } 1233 1234 module_init(hpre_init); 1235 module_exit(hpre_exit); 1236 1237 MODULE_LICENSE("GPL v2"); 1238 MODULE_AUTHOR("Zaibo Xu <xuzaibo@huawei.com>"); 1239 MODULE_AUTHOR("Meng Yu <yumeng18@huawei.com>"); 1240 MODULE_DESCRIPTION("Driver for HiSilicon HPRE accelerator"); 1241