1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018-2019 HiSilicon Limited. */ 3 #include <linux/acpi.h> 4 #include <linux/aer.h> 5 #include <linux/bitops.h> 6 #include <linux/debugfs.h> 7 #include <linux/init.h> 8 #include <linux/io.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/topology.h> 13 #include "hpre.h" 14 15 #define HPRE_VF_NUM 63 16 #define HPRE_QUEUE_NUM_V2 1024 17 #define HPRE_QM_ABNML_INT_MASK 0x100004 18 #define HPRE_CTRL_CNT_CLR_CE_BIT BIT(0) 19 #define HPRE_COMM_CNT_CLR_CE 0x0 20 #define HPRE_CTRL_CNT_CLR_CE 0x301000 21 #define HPRE_FSM_MAX_CNT 0x301008 22 #define HPRE_VFG_AXQOS 0x30100c 23 #define HPRE_VFG_AXCACHE 0x301010 24 #define HPRE_RDCHN_INI_CFG 0x301014 25 #define HPRE_AWUSR_FP_CFG 0x301018 26 #define HPRE_BD_ENDIAN 0x301020 27 #define HPRE_ECC_BYPASS 0x301024 28 #define HPRE_RAS_WIDTH_CFG 0x301028 29 #define HPRE_POISON_BYPASS 0x30102c 30 #define HPRE_BD_ARUSR_CFG 0x301030 31 #define HPRE_BD_AWUSR_CFG 0x301034 32 #define HPRE_TYPES_ENB 0x301038 33 #define HPRE_DATA_RUSER_CFG 0x30103c 34 #define HPRE_DATA_WUSER_CFG 0x301040 35 #define HPRE_INT_MASK 0x301400 36 #define HPRE_INT_STATUS 0x301800 37 #define HPRE_CORE_INT_ENABLE 0 38 #define HPRE_CORE_INT_DISABLE 0x003fffff 39 #define HPRE_RAS_ECC_1BIT_TH 0x30140c 40 #define HPRE_RDCHN_INI_ST 0x301a00 41 #define HPRE_CLSTR_BASE 0x302000 42 #define HPRE_CORE_EN_OFFSET 0x04 43 #define HPRE_CORE_INI_CFG_OFFSET 0x20 44 #define HPRE_CORE_INI_STATUS_OFFSET 0x80 45 #define HPRE_CORE_HTBT_WARN_OFFSET 0x8c 46 #define HPRE_CORE_IS_SCHD_OFFSET 0x90 47 48 #define HPRE_RAS_CE_ENB 0x301410 49 #define HPRE_HAC_RAS_CE_ENABLE 0x3f 50 #define HPRE_RAS_NFE_ENB 0x301414 51 #define HPRE_HAC_RAS_NFE_ENABLE 0x3fffc0 52 #define HPRE_RAS_FE_ENB 0x301418 53 #define HPRE_HAC_RAS_FE_ENABLE 0 54 55 #define HPRE_CORE_ENB (HPRE_CLSTR_BASE + HPRE_CORE_EN_OFFSET) 56 #define HPRE_CORE_INI_CFG (HPRE_CLSTR_BASE + HPRE_CORE_INI_CFG_OFFSET) 57 #define HPRE_CORE_INI_STATUS (HPRE_CLSTR_BASE + HPRE_CORE_INI_STATUS_OFFSET) 58 #define HPRE_HAC_ECC1_CNT 0x301a04 59 #define HPRE_HAC_ECC2_CNT 0x301a08 60 #define HPRE_HAC_INT_STATUS 0x301800 61 #define HPRE_HAC_SOURCE_INT 0x301600 62 #define MASTER_GLOBAL_CTRL_SHUTDOWN 1 63 #define MASTER_TRANS_RETURN_RW 3 64 #define HPRE_MASTER_TRANS_RETURN 0x300150 65 #define HPRE_MASTER_GLOBAL_CTRL 0x300000 66 #define HPRE_CLSTR_ADDR_INTRVL 0x1000 67 #define HPRE_CLUSTER_INQURY 0x100 68 #define HPRE_CLSTR_ADDR_INQRY_RSLT 0x104 69 #define HPRE_TIMEOUT_ABNML_BIT 6 70 #define HPRE_PASID_EN_BIT 9 71 #define HPRE_REG_RD_INTVRL_US 10 72 #define HPRE_REG_RD_TMOUT_US 1000 73 #define HPRE_DBGFS_VAL_MAX_LEN 20 74 #define HPRE_PCI_DEVICE_ID 0xa258 75 #define HPRE_PCI_VF_DEVICE_ID 0xa259 76 #define HPRE_ADDR(qm, offset) ((qm)->io_base + (offset)) 77 #define HPRE_QM_USR_CFG_MASK 0xfffffffe 78 #define HPRE_QM_AXI_CFG_MASK 0xffff 79 #define HPRE_QM_VFG_AX_MASK 0xff 80 #define HPRE_BD_USR_MASK 0x3 81 #define HPRE_CLUSTER_CORE_MASK 0xf 82 83 #define HPRE_VIA_MSI_DSM 1 84 85 static LIST_HEAD(hpre_list); 86 static DEFINE_MUTEX(hpre_list_lock); 87 static const char hpre_name[] = "hisi_hpre"; 88 static struct dentry *hpre_debugfs_root; 89 static const struct pci_device_id hpre_dev_ids[] = { 90 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HPRE_PCI_DEVICE_ID) }, 91 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HPRE_PCI_VF_DEVICE_ID) }, 92 { 0, } 93 }; 94 95 MODULE_DEVICE_TABLE(pci, hpre_dev_ids); 96 97 struct hpre_hw_error { 98 u32 int_msk; 99 const char *msg; 100 }; 101 102 static const char * const hpre_debug_file_name[] = { 103 [HPRE_CURRENT_QM] = "current_qm", 104 [HPRE_CLEAR_ENABLE] = "rdclr_en", 105 [HPRE_CLUSTER_CTRL] = "cluster_ctrl", 106 }; 107 108 static const struct hpre_hw_error hpre_hw_errors[] = { 109 { .int_msk = BIT(0), .msg = "core_ecc_1bit_err_int_set" }, 110 { .int_msk = BIT(1), .msg = "core_ecc_2bit_err_int_set" }, 111 { .int_msk = BIT(2), .msg = "dat_wb_poison_int_set" }, 112 { .int_msk = BIT(3), .msg = "dat_rd_poison_int_set" }, 113 { .int_msk = BIT(4), .msg = "bd_rd_poison_int_set" }, 114 { .int_msk = BIT(5), .msg = "ooo_ecc_2bit_err_int_set" }, 115 { .int_msk = BIT(6), .msg = "cluster1_shb_timeout_int_set" }, 116 { .int_msk = BIT(7), .msg = "cluster2_shb_timeout_int_set" }, 117 { .int_msk = BIT(8), .msg = "cluster3_shb_timeout_int_set" }, 118 { .int_msk = BIT(9), .msg = "cluster4_shb_timeout_int_set" }, 119 { .int_msk = GENMASK(15, 10), .msg = "ooo_rdrsp_err_int_set" }, 120 { .int_msk = GENMASK(21, 16), .msg = "ooo_wrrsp_err_int_set" }, 121 { /* sentinel */ } 122 }; 123 124 static const u64 hpre_cluster_offsets[] = { 125 [HPRE_CLUSTER0] = 126 HPRE_CLSTR_BASE + HPRE_CLUSTER0 * HPRE_CLSTR_ADDR_INTRVL, 127 [HPRE_CLUSTER1] = 128 HPRE_CLSTR_BASE + HPRE_CLUSTER1 * HPRE_CLSTR_ADDR_INTRVL, 129 [HPRE_CLUSTER2] = 130 HPRE_CLSTR_BASE + HPRE_CLUSTER2 * HPRE_CLSTR_ADDR_INTRVL, 131 [HPRE_CLUSTER3] = 132 HPRE_CLSTR_BASE + HPRE_CLUSTER3 * HPRE_CLSTR_ADDR_INTRVL, 133 }; 134 135 static struct debugfs_reg32 hpre_cluster_dfx_regs[] = { 136 {"CORES_EN_STATUS ", HPRE_CORE_EN_OFFSET}, 137 {"CORES_INI_CFG ", HPRE_CORE_INI_CFG_OFFSET}, 138 {"CORES_INI_STATUS ", HPRE_CORE_INI_STATUS_OFFSET}, 139 {"CORES_HTBT_WARN ", HPRE_CORE_HTBT_WARN_OFFSET}, 140 {"CORES_IS_SCHD ", HPRE_CORE_IS_SCHD_OFFSET}, 141 }; 142 143 static struct debugfs_reg32 hpre_com_dfx_regs[] = { 144 {"READ_CLR_EN ", HPRE_CTRL_CNT_CLR_CE}, 145 {"AXQOS ", HPRE_VFG_AXQOS}, 146 {"AWUSR_CFG ", HPRE_AWUSR_FP_CFG}, 147 {"QM_ARUSR_MCFG1 ", QM_ARUSER_M_CFG_1}, 148 {"QM_AWUSR_MCFG1 ", QM_AWUSER_M_CFG_1}, 149 {"BD_ENDIAN ", HPRE_BD_ENDIAN}, 150 {"ECC_CHECK_CTRL ", HPRE_ECC_BYPASS}, 151 {"RAS_INT_WIDTH ", HPRE_RAS_WIDTH_CFG}, 152 {"POISON_BYPASS ", HPRE_POISON_BYPASS}, 153 {"BD_ARUSER ", HPRE_BD_ARUSR_CFG}, 154 {"BD_AWUSER ", HPRE_BD_AWUSR_CFG}, 155 {"DATA_ARUSER ", HPRE_DATA_RUSER_CFG}, 156 {"DATA_AWUSER ", HPRE_DATA_WUSER_CFG}, 157 {"INT_STATUS ", HPRE_INT_STATUS}, 158 }; 159 160 static int hpre_pf_q_num_set(const char *val, const struct kernel_param *kp) 161 { 162 struct pci_dev *pdev; 163 u32 n, q_num; 164 u8 rev_id; 165 int ret; 166 167 if (!val) 168 return -EINVAL; 169 170 pdev = pci_get_device(PCI_VENDOR_ID_HUAWEI, HPRE_PCI_DEVICE_ID, NULL); 171 if (!pdev) { 172 q_num = HPRE_QUEUE_NUM_V2; 173 pr_info("No device found currently, suppose queue number is %d\n", 174 q_num); 175 } else { 176 rev_id = pdev->revision; 177 if (rev_id != QM_HW_V2) 178 return -EINVAL; 179 180 q_num = HPRE_QUEUE_NUM_V2; 181 } 182 183 ret = kstrtou32(val, 10, &n); 184 if (ret != 0 || n == 0 || n > q_num) 185 return -EINVAL; 186 187 return param_set_int(val, kp); 188 } 189 190 static const struct kernel_param_ops hpre_pf_q_num_ops = { 191 .set = hpre_pf_q_num_set, 192 .get = param_get_int, 193 }; 194 195 static u32 hpre_pf_q_num = HPRE_PF_DEF_Q_NUM; 196 module_param_cb(hpre_pf_q_num, &hpre_pf_q_num_ops, &hpre_pf_q_num, 0444); 197 MODULE_PARM_DESC(hpre_pf_q_num, "Number of queues in PF of CS(1-1024)"); 198 199 static inline void hpre_add_to_list(struct hpre *hpre) 200 { 201 mutex_lock(&hpre_list_lock); 202 list_add_tail(&hpre->list, &hpre_list); 203 mutex_unlock(&hpre_list_lock); 204 } 205 206 static inline void hpre_remove_from_list(struct hpre *hpre) 207 { 208 mutex_lock(&hpre_list_lock); 209 list_del(&hpre->list); 210 mutex_unlock(&hpre_list_lock); 211 } 212 213 struct hpre *hpre_find_device(int node) 214 { 215 struct hpre *hpre, *ret = NULL; 216 int min_distance = INT_MAX; 217 struct device *dev; 218 int dev_node = 0; 219 220 mutex_lock(&hpre_list_lock); 221 list_for_each_entry(hpre, &hpre_list, list) { 222 dev = &hpre->qm.pdev->dev; 223 #ifdef CONFIG_NUMA 224 dev_node = dev->numa_node; 225 if (dev_node < 0) 226 dev_node = 0; 227 #endif 228 if (node_distance(dev_node, node) < min_distance) { 229 ret = hpre; 230 min_distance = node_distance(dev_node, node); 231 } 232 } 233 mutex_unlock(&hpre_list_lock); 234 235 return ret; 236 } 237 238 static int hpre_cfg_by_dsm(struct hisi_qm *qm) 239 { 240 struct device *dev = &qm->pdev->dev; 241 union acpi_object *obj; 242 guid_t guid; 243 244 if (guid_parse("b06b81ab-0134-4a45-9b0c-483447b95fa7", &guid)) { 245 dev_err(dev, "Hpre GUID failed\n"); 246 return -EINVAL; 247 } 248 249 /* Switch over to MSI handling due to non-standard PCI implementation */ 250 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &guid, 251 0, HPRE_VIA_MSI_DSM, NULL); 252 if (!obj) { 253 dev_err(dev, "ACPI handle failed!\n"); 254 return -EIO; 255 } 256 257 ACPI_FREE(obj); 258 259 return 0; 260 } 261 262 static int hpre_set_user_domain_and_cache(struct hpre *hpre) 263 { 264 struct hisi_qm *qm = &hpre->qm; 265 struct device *dev = &qm->pdev->dev; 266 unsigned long offset; 267 int ret, i; 268 u32 val; 269 270 writel(HPRE_QM_USR_CFG_MASK, HPRE_ADDR(qm, QM_ARUSER_M_CFG_ENABLE)); 271 writel(HPRE_QM_USR_CFG_MASK, HPRE_ADDR(qm, QM_AWUSER_M_CFG_ENABLE)); 272 writel_relaxed(HPRE_QM_AXI_CFG_MASK, HPRE_ADDR(qm, QM_AXI_M_CFG)); 273 274 /* disable FLR triggered by BME(bus master enable) */ 275 writel(PEH_AXUSER_CFG, HPRE_ADDR(qm, QM_PEH_AXUSER_CFG)); 276 writel(PEH_AXUSER_CFG_ENABLE, HPRE_ADDR(qm, QM_PEH_AXUSER_CFG_ENABLE)); 277 278 /* HPRE need more time, we close this interrupt */ 279 val = readl_relaxed(HPRE_ADDR(qm, HPRE_QM_ABNML_INT_MASK)); 280 val |= BIT(HPRE_TIMEOUT_ABNML_BIT); 281 writel_relaxed(val, HPRE_ADDR(qm, HPRE_QM_ABNML_INT_MASK)); 282 283 writel(0x1, HPRE_ADDR(qm, HPRE_TYPES_ENB)); 284 writel(HPRE_QM_VFG_AX_MASK, HPRE_ADDR(qm, HPRE_VFG_AXCACHE)); 285 writel(0x0, HPRE_ADDR(qm, HPRE_BD_ENDIAN)); 286 writel(0x0, HPRE_ADDR(qm, HPRE_INT_MASK)); 287 writel(0x0, HPRE_ADDR(qm, HPRE_RAS_ECC_1BIT_TH)); 288 writel(0x0, HPRE_ADDR(qm, HPRE_POISON_BYPASS)); 289 writel(0x0, HPRE_ADDR(qm, HPRE_COMM_CNT_CLR_CE)); 290 writel(0x0, HPRE_ADDR(qm, HPRE_ECC_BYPASS)); 291 292 writel(HPRE_BD_USR_MASK, HPRE_ADDR(qm, HPRE_BD_ARUSR_CFG)); 293 writel(HPRE_BD_USR_MASK, HPRE_ADDR(qm, HPRE_BD_AWUSR_CFG)); 294 writel(0x1, HPRE_ADDR(qm, HPRE_RDCHN_INI_CFG)); 295 ret = readl_relaxed_poll_timeout(HPRE_ADDR(qm, HPRE_RDCHN_INI_ST), val, 296 val & BIT(0), 297 HPRE_REG_RD_INTVRL_US, 298 HPRE_REG_RD_TMOUT_US); 299 if (ret) { 300 dev_err(dev, "read rd channel timeout fail!\n"); 301 return -ETIMEDOUT; 302 } 303 304 for (i = 0; i < HPRE_CLUSTERS_NUM; i++) { 305 offset = i * HPRE_CLSTR_ADDR_INTRVL; 306 307 /* clusters initiating */ 308 writel(HPRE_CLUSTER_CORE_MASK, 309 HPRE_ADDR(qm, offset + HPRE_CORE_ENB)); 310 writel(0x1, HPRE_ADDR(qm, offset + HPRE_CORE_INI_CFG)); 311 ret = readl_relaxed_poll_timeout(HPRE_ADDR(qm, offset + 312 HPRE_CORE_INI_STATUS), val, 313 ((val & HPRE_CLUSTER_CORE_MASK) == 314 HPRE_CLUSTER_CORE_MASK), 315 HPRE_REG_RD_INTVRL_US, 316 HPRE_REG_RD_TMOUT_US); 317 if (ret) { 318 dev_err(dev, 319 "cluster %d int st status timeout!\n", i); 320 return -ETIMEDOUT; 321 } 322 } 323 324 ret = hpre_cfg_by_dsm(qm); 325 if (ret) 326 dev_err(dev, "acpi_evaluate_dsm err.\n"); 327 328 return ret; 329 } 330 331 static void hpre_cnt_regs_clear(struct hisi_qm *qm) 332 { 333 unsigned long offset; 334 int i; 335 336 /* clear current_qm */ 337 writel(0x0, qm->io_base + QM_DFX_MB_CNT_VF); 338 writel(0x0, qm->io_base + QM_DFX_DB_CNT_VF); 339 340 /* clear clusterX/cluster_ctrl */ 341 for (i = 0; i < HPRE_CLUSTERS_NUM; i++) { 342 offset = HPRE_CLSTR_BASE + i * HPRE_CLSTR_ADDR_INTRVL; 343 writel(0x0, qm->io_base + offset + HPRE_CLUSTER_INQURY); 344 } 345 346 /* clear rdclr_en */ 347 writel(0x0, qm->io_base + HPRE_CTRL_CNT_CLR_CE); 348 349 hisi_qm_debug_regs_clear(qm); 350 } 351 352 static void hpre_hw_error_disable(struct hisi_qm *qm) 353 { 354 /* disable hpre hw error interrupts */ 355 writel(HPRE_CORE_INT_DISABLE, qm->io_base + HPRE_INT_MASK); 356 } 357 358 static void hpre_hw_error_enable(struct hisi_qm *qm) 359 { 360 /* enable hpre hw error interrupts */ 361 writel(HPRE_CORE_INT_ENABLE, qm->io_base + HPRE_INT_MASK); 362 writel(HPRE_HAC_RAS_CE_ENABLE, qm->io_base + HPRE_RAS_CE_ENB); 363 writel(HPRE_HAC_RAS_NFE_ENABLE, qm->io_base + HPRE_RAS_NFE_ENB); 364 writel(HPRE_HAC_RAS_FE_ENABLE, qm->io_base + HPRE_RAS_FE_ENB); 365 } 366 367 static inline struct hisi_qm *hpre_file_to_qm(struct hpre_debugfs_file *file) 368 { 369 struct hpre *hpre = container_of(file->debug, struct hpre, debug); 370 371 return &hpre->qm; 372 } 373 374 static u32 hpre_current_qm_read(struct hpre_debugfs_file *file) 375 { 376 struct hisi_qm *qm = hpre_file_to_qm(file); 377 378 return readl(qm->io_base + QM_DFX_MB_CNT_VF); 379 } 380 381 static int hpre_current_qm_write(struct hpre_debugfs_file *file, u32 val) 382 { 383 struct hisi_qm *qm = hpre_file_to_qm(file); 384 struct hpre_debug *debug = file->debug; 385 struct hpre *hpre = container_of(debug, struct hpre, debug); 386 u32 num_vfs = hpre->num_vfs; 387 u32 vfq_num, tmp; 388 389 390 if (val > num_vfs) 391 return -EINVAL; 392 393 /* According PF or VF Dev ID to calculation curr_qm_qp_num and store */ 394 if (val == 0) { 395 qm->debug.curr_qm_qp_num = qm->qp_num; 396 } else { 397 vfq_num = (qm->ctrl_qp_num - qm->qp_num) / num_vfs; 398 if (val == num_vfs) { 399 qm->debug.curr_qm_qp_num = 400 qm->ctrl_qp_num - qm->qp_num - (num_vfs - 1) * vfq_num; 401 } else { 402 qm->debug.curr_qm_qp_num = vfq_num; 403 } 404 } 405 406 writel(val, qm->io_base + QM_DFX_MB_CNT_VF); 407 writel(val, qm->io_base + QM_DFX_DB_CNT_VF); 408 409 tmp = val | 410 (readl(qm->io_base + QM_DFX_SQE_CNT_VF_SQN) & CURRENT_Q_MASK); 411 writel(tmp, qm->io_base + QM_DFX_SQE_CNT_VF_SQN); 412 413 tmp = val | 414 (readl(qm->io_base + QM_DFX_CQE_CNT_VF_CQN) & CURRENT_Q_MASK); 415 writel(tmp, qm->io_base + QM_DFX_CQE_CNT_VF_CQN); 416 417 return 0; 418 } 419 420 static u32 hpre_clear_enable_read(struct hpre_debugfs_file *file) 421 { 422 struct hisi_qm *qm = hpre_file_to_qm(file); 423 424 return readl(qm->io_base + HPRE_CTRL_CNT_CLR_CE) & 425 HPRE_CTRL_CNT_CLR_CE_BIT; 426 } 427 428 static int hpre_clear_enable_write(struct hpre_debugfs_file *file, u32 val) 429 { 430 struct hisi_qm *qm = hpre_file_to_qm(file); 431 u32 tmp; 432 433 if (val != 1 && val != 0) 434 return -EINVAL; 435 436 tmp = (readl(qm->io_base + HPRE_CTRL_CNT_CLR_CE) & 437 ~HPRE_CTRL_CNT_CLR_CE_BIT) | val; 438 writel(tmp, qm->io_base + HPRE_CTRL_CNT_CLR_CE); 439 440 return 0; 441 } 442 443 static u32 hpre_cluster_inqry_read(struct hpre_debugfs_file *file) 444 { 445 struct hisi_qm *qm = hpre_file_to_qm(file); 446 int cluster_index = file->index - HPRE_CLUSTER_CTRL; 447 unsigned long offset = HPRE_CLSTR_BASE + 448 cluster_index * HPRE_CLSTR_ADDR_INTRVL; 449 450 return readl(qm->io_base + offset + HPRE_CLSTR_ADDR_INQRY_RSLT); 451 } 452 453 static int hpre_cluster_inqry_write(struct hpre_debugfs_file *file, u32 val) 454 { 455 struct hisi_qm *qm = hpre_file_to_qm(file); 456 int cluster_index = file->index - HPRE_CLUSTER_CTRL; 457 unsigned long offset = HPRE_CLSTR_BASE + cluster_index * 458 HPRE_CLSTR_ADDR_INTRVL; 459 460 writel(val, qm->io_base + offset + HPRE_CLUSTER_INQURY); 461 462 return 0; 463 } 464 465 static ssize_t hpre_ctrl_debug_read(struct file *filp, char __user *buf, 466 size_t count, loff_t *pos) 467 { 468 struct hpre_debugfs_file *file = filp->private_data; 469 char tbuf[HPRE_DBGFS_VAL_MAX_LEN]; 470 u32 val; 471 int ret; 472 473 spin_lock_irq(&file->lock); 474 switch (file->type) { 475 case HPRE_CURRENT_QM: 476 val = hpre_current_qm_read(file); 477 break; 478 case HPRE_CLEAR_ENABLE: 479 val = hpre_clear_enable_read(file); 480 break; 481 case HPRE_CLUSTER_CTRL: 482 val = hpre_cluster_inqry_read(file); 483 break; 484 default: 485 spin_unlock_irq(&file->lock); 486 return -EINVAL; 487 } 488 spin_unlock_irq(&file->lock); 489 ret = snprintf(tbuf, HPRE_DBGFS_VAL_MAX_LEN, "%u\n", val); 490 return simple_read_from_buffer(buf, count, pos, tbuf, ret); 491 } 492 493 static ssize_t hpre_ctrl_debug_write(struct file *filp, const char __user *buf, 494 size_t count, loff_t *pos) 495 { 496 struct hpre_debugfs_file *file = filp->private_data; 497 char tbuf[HPRE_DBGFS_VAL_MAX_LEN]; 498 unsigned long val; 499 int len, ret; 500 501 if (*pos != 0) 502 return 0; 503 504 if (count >= HPRE_DBGFS_VAL_MAX_LEN) 505 return -ENOSPC; 506 507 len = simple_write_to_buffer(tbuf, HPRE_DBGFS_VAL_MAX_LEN - 1, 508 pos, buf, count); 509 if (len < 0) 510 return len; 511 512 tbuf[len] = '\0'; 513 if (kstrtoul(tbuf, 0, &val)) 514 return -EFAULT; 515 516 spin_lock_irq(&file->lock); 517 switch (file->type) { 518 case HPRE_CURRENT_QM: 519 ret = hpre_current_qm_write(file, val); 520 if (ret) 521 goto err_input; 522 break; 523 case HPRE_CLEAR_ENABLE: 524 ret = hpre_clear_enable_write(file, val); 525 if (ret) 526 goto err_input; 527 break; 528 case HPRE_CLUSTER_CTRL: 529 ret = hpre_cluster_inqry_write(file, val); 530 if (ret) 531 goto err_input; 532 break; 533 default: 534 ret = -EINVAL; 535 goto err_input; 536 } 537 spin_unlock_irq(&file->lock); 538 539 return count; 540 541 err_input: 542 spin_unlock_irq(&file->lock); 543 return ret; 544 } 545 546 static const struct file_operations hpre_ctrl_debug_fops = { 547 .owner = THIS_MODULE, 548 .open = simple_open, 549 .read = hpre_ctrl_debug_read, 550 .write = hpre_ctrl_debug_write, 551 }; 552 553 static int hpre_create_debugfs_file(struct hpre_debug *dbg, struct dentry *dir, 554 enum hpre_ctrl_dbgfs_file type, int indx) 555 { 556 struct dentry *file_dir; 557 558 if (dir) 559 file_dir = dir; 560 else 561 file_dir = dbg->debug_root; 562 563 if (type >= HPRE_DEBUG_FILE_NUM) 564 return -EINVAL; 565 566 spin_lock_init(&dbg->files[indx].lock); 567 dbg->files[indx].debug = dbg; 568 dbg->files[indx].type = type; 569 dbg->files[indx].index = indx; 570 debugfs_create_file(hpre_debug_file_name[type], 0600, file_dir, 571 dbg->files + indx, &hpre_ctrl_debug_fops); 572 573 return 0; 574 } 575 576 static int hpre_pf_comm_regs_debugfs_init(struct hpre_debug *debug) 577 { 578 struct hpre *hpre = container_of(debug, struct hpre, debug); 579 struct hisi_qm *qm = &hpre->qm; 580 struct device *dev = &qm->pdev->dev; 581 struct debugfs_regset32 *regset; 582 583 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 584 if (!regset) 585 return -ENOMEM; 586 587 regset->regs = hpre_com_dfx_regs; 588 regset->nregs = ARRAY_SIZE(hpre_com_dfx_regs); 589 regset->base = qm->io_base; 590 591 debugfs_create_regset32("regs", 0444, debug->debug_root, regset); 592 return 0; 593 } 594 595 static int hpre_cluster_debugfs_init(struct hpre_debug *debug) 596 { 597 struct hpre *hpre = container_of(debug, struct hpre, debug); 598 struct hisi_qm *qm = &hpre->qm; 599 struct device *dev = &qm->pdev->dev; 600 char buf[HPRE_DBGFS_VAL_MAX_LEN]; 601 struct debugfs_regset32 *regset; 602 struct dentry *tmp_d; 603 int i, ret; 604 605 for (i = 0; i < HPRE_CLUSTERS_NUM; i++) { 606 ret = snprintf(buf, HPRE_DBGFS_VAL_MAX_LEN, "cluster%d", i); 607 if (ret < 0) 608 return -EINVAL; 609 tmp_d = debugfs_create_dir(buf, debug->debug_root); 610 611 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 612 if (!regset) 613 return -ENOMEM; 614 615 regset->regs = hpre_cluster_dfx_regs; 616 regset->nregs = ARRAY_SIZE(hpre_cluster_dfx_regs); 617 regset->base = qm->io_base + hpre_cluster_offsets[i]; 618 619 debugfs_create_regset32("regs", 0444, tmp_d, regset); 620 ret = hpre_create_debugfs_file(debug, tmp_d, HPRE_CLUSTER_CTRL, 621 i + HPRE_CLUSTER_CTRL); 622 if (ret) 623 return ret; 624 } 625 626 return 0; 627 } 628 629 static int hpre_ctrl_debug_init(struct hpre_debug *debug) 630 { 631 int ret; 632 633 ret = hpre_create_debugfs_file(debug, NULL, HPRE_CURRENT_QM, 634 HPRE_CURRENT_QM); 635 if (ret) 636 return ret; 637 638 ret = hpre_create_debugfs_file(debug, NULL, HPRE_CLEAR_ENABLE, 639 HPRE_CLEAR_ENABLE); 640 if (ret) 641 return ret; 642 643 ret = hpre_pf_comm_regs_debugfs_init(debug); 644 if (ret) 645 return ret; 646 647 return hpre_cluster_debugfs_init(debug); 648 } 649 650 static int hpre_debugfs_init(struct hpre *hpre) 651 { 652 struct hisi_qm *qm = &hpre->qm; 653 struct device *dev = &qm->pdev->dev; 654 struct dentry *dir; 655 int ret; 656 657 dir = debugfs_create_dir(dev_name(dev), hpre_debugfs_root); 658 qm->debug.debug_root = dir; 659 660 ret = hisi_qm_debug_init(qm); 661 if (ret) 662 goto failed_to_create; 663 664 if (qm->pdev->device == HPRE_PCI_DEVICE_ID) { 665 hpre->debug.debug_root = dir; 666 ret = hpre_ctrl_debug_init(&hpre->debug); 667 if (ret) 668 goto failed_to_create; 669 } 670 return 0; 671 672 failed_to_create: 673 debugfs_remove_recursive(qm->debug.debug_root); 674 return ret; 675 } 676 677 static void hpre_debugfs_exit(struct hpre *hpre) 678 { 679 struct hisi_qm *qm = &hpre->qm; 680 681 debugfs_remove_recursive(qm->debug.debug_root); 682 } 683 684 static int hpre_qm_pre_init(struct hisi_qm *qm, struct pci_dev *pdev) 685 { 686 enum qm_hw_ver rev_id; 687 688 rev_id = hisi_qm_get_hw_version(pdev); 689 if (rev_id < 0) 690 return -ENODEV; 691 692 if (rev_id == QM_HW_V1) { 693 pci_warn(pdev, "HPRE version 1 is not supported!\n"); 694 return -EINVAL; 695 } 696 697 qm->pdev = pdev; 698 qm->ver = rev_id; 699 qm->sqe_size = HPRE_SQE_SIZE; 700 qm->dev_name = hpre_name; 701 qm->fun_type = (pdev->device == HPRE_PCI_DEVICE_ID) ? 702 QM_HW_PF : QM_HW_VF; 703 if (pdev->is_physfn) { 704 qm->qp_base = HPRE_PF_DEF_Q_BASE; 705 qm->qp_num = hpre_pf_q_num; 706 } 707 qm->use_dma_api = true; 708 709 return 0; 710 } 711 712 static void hpre_log_hw_error(struct hisi_qm *qm, u32 err_sts) 713 { 714 const struct hpre_hw_error *err = hpre_hw_errors; 715 struct device *dev = &qm->pdev->dev; 716 717 while (err->msg) { 718 if (err->int_msk & err_sts) 719 dev_warn(dev, "%s [error status=0x%x] found\n", 720 err->msg, err->int_msk); 721 err++; 722 } 723 724 writel(err_sts, qm->io_base + HPRE_HAC_SOURCE_INT); 725 } 726 727 static u32 hpre_get_hw_err_status(struct hisi_qm *qm) 728 { 729 return readl(qm->io_base + HPRE_HAC_INT_STATUS); 730 } 731 732 static const struct hisi_qm_err_ini hpre_err_ini = { 733 .hw_err_enable = hpre_hw_error_enable, 734 .hw_err_disable = hpre_hw_error_disable, 735 .get_dev_hw_err_status = hpre_get_hw_err_status, 736 .log_dev_hw_err = hpre_log_hw_error, 737 .err_info = { 738 .ce = QM_BASE_CE, 739 .nfe = QM_BASE_NFE | QM_ACC_DO_TASK_TIMEOUT, 740 .fe = 0, 741 .msi = QM_DB_RANDOM_INVALID, 742 } 743 }; 744 745 static int hpre_pf_probe_init(struct hpre *hpre) 746 { 747 struct hisi_qm *qm = &hpre->qm; 748 int ret; 749 750 qm->ctrl_qp_num = HPRE_QUEUE_NUM_V2; 751 752 ret = hpre_set_user_domain_and_cache(hpre); 753 if (ret) 754 return ret; 755 756 qm->err_ini = &hpre_err_ini; 757 hisi_qm_dev_err_init(qm); 758 759 return 0; 760 } 761 762 static int hpre_probe(struct pci_dev *pdev, const struct pci_device_id *id) 763 { 764 struct hisi_qm *qm; 765 struct hpre *hpre; 766 int ret; 767 768 hpre = devm_kzalloc(&pdev->dev, sizeof(*hpre), GFP_KERNEL); 769 if (!hpre) 770 return -ENOMEM; 771 772 pci_set_drvdata(pdev, hpre); 773 774 qm = &hpre->qm; 775 ret = hpre_qm_pre_init(qm, pdev); 776 if (ret) 777 return ret; 778 779 ret = hisi_qm_init(qm); 780 if (ret) 781 return ret; 782 783 if (pdev->is_physfn) { 784 ret = hpre_pf_probe_init(hpre); 785 if (ret) 786 goto err_with_qm_init; 787 } else if (qm->fun_type == QM_HW_VF && qm->ver == QM_HW_V2) { 788 /* v2 starts to support get vft by mailbox */ 789 ret = hisi_qm_get_vft(qm, &qm->qp_base, &qm->qp_num); 790 if (ret) 791 goto err_with_qm_init; 792 } 793 794 ret = hisi_qm_start(qm); 795 if (ret) 796 goto err_with_err_init; 797 798 ret = hpre_debugfs_init(hpre); 799 if (ret) 800 dev_warn(&pdev->dev, "init debugfs fail!\n"); 801 802 hpre_add_to_list(hpre); 803 804 ret = hpre_algs_register(); 805 if (ret < 0) { 806 hpre_remove_from_list(hpre); 807 pci_err(pdev, "fail to register algs to crypto!\n"); 808 goto err_with_qm_start; 809 } 810 return 0; 811 812 err_with_qm_start: 813 hisi_qm_stop(qm); 814 815 err_with_err_init: 816 hisi_qm_dev_err_uninit(qm); 817 818 err_with_qm_init: 819 hisi_qm_uninit(qm); 820 821 return ret; 822 } 823 824 static int hpre_vf_q_assign(struct hpre *hpre, int num_vfs) 825 { 826 struct hisi_qm *qm = &hpre->qm; 827 u32 qp_num = qm->qp_num; 828 int q_num, remain_q_num, i; 829 u32 q_base = qp_num; 830 int ret; 831 832 if (!num_vfs) 833 return -EINVAL; 834 835 remain_q_num = qm->ctrl_qp_num - qp_num; 836 837 /* If remaining queues are not enough, return error. */ 838 if (remain_q_num < num_vfs) 839 return -EINVAL; 840 841 q_num = remain_q_num / num_vfs; 842 for (i = 1; i <= num_vfs; i++) { 843 if (i == num_vfs) 844 q_num += remain_q_num % num_vfs; 845 ret = hisi_qm_set_vft(qm, i, q_base, (u32)q_num); 846 if (ret) 847 return ret; 848 q_base += q_num; 849 } 850 851 return 0; 852 } 853 854 static int hpre_clear_vft_config(struct hpre *hpre) 855 { 856 struct hisi_qm *qm = &hpre->qm; 857 u32 num_vfs = hpre->num_vfs; 858 int ret; 859 u32 i; 860 861 for (i = 1; i <= num_vfs; i++) { 862 ret = hisi_qm_set_vft(qm, i, 0, 0); 863 if (ret) 864 return ret; 865 } 866 hpre->num_vfs = 0; 867 868 return 0; 869 } 870 871 static int hpre_sriov_enable(struct pci_dev *pdev, int max_vfs) 872 { 873 struct hpre *hpre = pci_get_drvdata(pdev); 874 int pre_existing_vfs, num_vfs, ret; 875 876 pre_existing_vfs = pci_num_vf(pdev); 877 if (pre_existing_vfs) { 878 pci_err(pdev, 879 "Can't enable VF. Please disable pre-enabled VFs!\n"); 880 return 0; 881 } 882 883 num_vfs = min_t(int, max_vfs, HPRE_VF_NUM); 884 ret = hpre_vf_q_assign(hpre, num_vfs); 885 if (ret) { 886 pci_err(pdev, "Can't assign queues for VF!\n"); 887 return ret; 888 } 889 890 hpre->num_vfs = num_vfs; 891 892 ret = pci_enable_sriov(pdev, num_vfs); 893 if (ret) { 894 pci_err(pdev, "Can't enable VF!\n"); 895 hpre_clear_vft_config(hpre); 896 return ret; 897 } 898 899 return num_vfs; 900 } 901 902 static int hpre_sriov_disable(struct pci_dev *pdev) 903 { 904 struct hpre *hpre = pci_get_drvdata(pdev); 905 906 if (pci_vfs_assigned(pdev)) { 907 pci_err(pdev, "Failed to disable VFs while VFs are assigned!\n"); 908 return -EPERM; 909 } 910 911 /* remove in hpre_pci_driver will be called to free VF resources */ 912 pci_disable_sriov(pdev); 913 914 return hpre_clear_vft_config(hpre); 915 } 916 917 static int hpre_sriov_configure(struct pci_dev *pdev, int num_vfs) 918 { 919 if (num_vfs) 920 return hpre_sriov_enable(pdev, num_vfs); 921 else 922 return hpre_sriov_disable(pdev); 923 } 924 925 static void hpre_remove(struct pci_dev *pdev) 926 { 927 struct hpre *hpre = pci_get_drvdata(pdev); 928 struct hisi_qm *qm = &hpre->qm; 929 int ret; 930 931 hpre_algs_unregister(); 932 hpre_remove_from_list(hpre); 933 if (qm->fun_type == QM_HW_PF && hpre->num_vfs != 0) { 934 ret = hpre_sriov_disable(pdev); 935 if (ret) { 936 pci_err(pdev, "Disable SRIOV fail!\n"); 937 return; 938 } 939 } 940 if (qm->fun_type == QM_HW_PF) { 941 hpre_cnt_regs_clear(qm); 942 qm->debug.curr_qm_qp_num = 0; 943 } 944 945 hpre_debugfs_exit(hpre); 946 hisi_qm_stop(qm); 947 hisi_qm_dev_err_uninit(qm); 948 hisi_qm_uninit(qm); 949 } 950 951 952 static const struct pci_error_handlers hpre_err_handler = { 953 .error_detected = hisi_qm_dev_err_detected, 954 }; 955 956 static struct pci_driver hpre_pci_driver = { 957 .name = hpre_name, 958 .id_table = hpre_dev_ids, 959 .probe = hpre_probe, 960 .remove = hpre_remove, 961 .sriov_configure = hpre_sriov_configure, 962 .err_handler = &hpre_err_handler, 963 }; 964 965 static void hpre_register_debugfs(void) 966 { 967 if (!debugfs_initialized()) 968 return; 969 970 hpre_debugfs_root = debugfs_create_dir(hpre_name, NULL); 971 } 972 973 static void hpre_unregister_debugfs(void) 974 { 975 debugfs_remove_recursive(hpre_debugfs_root); 976 } 977 978 static int __init hpre_init(void) 979 { 980 int ret; 981 982 hpre_register_debugfs(); 983 984 ret = pci_register_driver(&hpre_pci_driver); 985 if (ret) { 986 hpre_unregister_debugfs(); 987 pr_err("hpre: can't register hisi hpre driver.\n"); 988 } 989 990 return ret; 991 } 992 993 static void __exit hpre_exit(void) 994 { 995 pci_unregister_driver(&hpre_pci_driver); 996 hpre_unregister_debugfs(); 997 } 998 999 module_init(hpre_init); 1000 module_exit(hpre_exit); 1001 1002 MODULE_LICENSE("GPL v2"); 1003 MODULE_AUTHOR("Zaibo Xu <xuzaibo@huawei.com>"); 1004 MODULE_DESCRIPTION("Driver for HiSilicon HPRE accelerator"); 1005