1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018-2019 HiSilicon Limited. */ 3 #include <linux/acpi.h> 4 #include <linux/bitops.h> 5 #include <linux/debugfs.h> 6 #include <linux/init.h> 7 #include <linux/io.h> 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/pci.h> 11 #include <linux/pm_runtime.h> 12 #include <linux/topology.h> 13 #include <linux/uacce.h> 14 #include "hpre.h" 15 16 #define HPRE_QM_ABNML_INT_MASK 0x100004 17 #define HPRE_CTRL_CNT_CLR_CE_BIT BIT(0) 18 #define HPRE_COMM_CNT_CLR_CE 0x0 19 #define HPRE_CTRL_CNT_CLR_CE 0x301000 20 #define HPRE_FSM_MAX_CNT 0x301008 21 #define HPRE_VFG_AXQOS 0x30100c 22 #define HPRE_VFG_AXCACHE 0x301010 23 #define HPRE_RDCHN_INI_CFG 0x301014 24 #define HPRE_AWUSR_FP_CFG 0x301018 25 #define HPRE_BD_ENDIAN 0x301020 26 #define HPRE_ECC_BYPASS 0x301024 27 #define HPRE_RAS_WIDTH_CFG 0x301028 28 #define HPRE_POISON_BYPASS 0x30102c 29 #define HPRE_BD_ARUSR_CFG 0x301030 30 #define HPRE_BD_AWUSR_CFG 0x301034 31 #define HPRE_TYPES_ENB 0x301038 32 #define HPRE_RSA_ENB BIT(0) 33 #define HPRE_ECC_ENB BIT(1) 34 #define HPRE_DATA_RUSER_CFG 0x30103c 35 #define HPRE_DATA_WUSER_CFG 0x301040 36 #define HPRE_INT_MASK 0x301400 37 #define HPRE_INT_STATUS 0x301800 38 #define HPRE_HAC_INT_MSK 0x301400 39 #define HPRE_HAC_RAS_CE_ENB 0x301410 40 #define HPRE_HAC_RAS_NFE_ENB 0x301414 41 #define HPRE_HAC_RAS_FE_ENB 0x301418 42 #define HPRE_HAC_INT_SET 0x301500 43 #define HPRE_RNG_TIMEOUT_NUM 0x301A34 44 #define HPRE_CORE_INT_ENABLE 0 45 #define HPRE_CORE_INT_DISABLE GENMASK(21, 0) 46 #define HPRE_RDCHN_INI_ST 0x301a00 47 #define HPRE_CLSTR_BASE 0x302000 48 #define HPRE_CORE_EN_OFFSET 0x04 49 #define HPRE_CORE_INI_CFG_OFFSET 0x20 50 #define HPRE_CORE_INI_STATUS_OFFSET 0x80 51 #define HPRE_CORE_HTBT_WARN_OFFSET 0x8c 52 #define HPRE_CORE_IS_SCHD_OFFSET 0x90 53 54 #define HPRE_RAS_CE_ENB 0x301410 55 #define HPRE_RAS_NFE_ENB 0x301414 56 #define HPRE_RAS_FE_ENB 0x301418 57 #define HPRE_OOO_SHUTDOWN_SEL 0x301a3c 58 #define HPRE_HAC_RAS_FE_ENABLE 0 59 60 #define HPRE_CORE_ENB (HPRE_CLSTR_BASE + HPRE_CORE_EN_OFFSET) 61 #define HPRE_CORE_INI_CFG (HPRE_CLSTR_BASE + HPRE_CORE_INI_CFG_OFFSET) 62 #define HPRE_CORE_INI_STATUS (HPRE_CLSTR_BASE + HPRE_CORE_INI_STATUS_OFFSET) 63 #define HPRE_HAC_ECC1_CNT 0x301a04 64 #define HPRE_HAC_ECC2_CNT 0x301a08 65 #define HPRE_HAC_SOURCE_INT 0x301600 66 #define HPRE_CLSTR_ADDR_INTRVL 0x1000 67 #define HPRE_CLUSTER_INQURY 0x100 68 #define HPRE_CLSTR_ADDR_INQRY_RSLT 0x104 69 #define HPRE_TIMEOUT_ABNML_BIT 6 70 #define HPRE_PASID_EN_BIT 9 71 #define HPRE_REG_RD_INTVRL_US 10 72 #define HPRE_REG_RD_TMOUT_US 1000 73 #define HPRE_DBGFS_VAL_MAX_LEN 20 74 #define PCI_DEVICE_ID_HUAWEI_HPRE_PF 0xa258 75 #define HPRE_QM_USR_CFG_MASK GENMASK(31, 1) 76 #define HPRE_QM_AXI_CFG_MASK GENMASK(15, 0) 77 #define HPRE_QM_VFG_AX_MASK GENMASK(7, 0) 78 #define HPRE_BD_USR_MASK GENMASK(1, 0) 79 #define HPRE_PREFETCH_CFG 0x301130 80 #define HPRE_SVA_PREFTCH_DFX 0x30115C 81 #define HPRE_PREFETCH_ENABLE (~(BIT(0) | BIT(30))) 82 #define HPRE_PREFETCH_DISABLE BIT(30) 83 #define HPRE_SVA_DISABLE_READY (BIT(4) | BIT(8)) 84 85 /* clock gate */ 86 #define HPRE_CLKGATE_CTL 0x301a10 87 #define HPRE_PEH_CFG_AUTO_GATE 0x301a2c 88 #define HPRE_CLUSTER_DYN_CTL 0x302010 89 #define HPRE_CORE_SHB_CFG 0x302088 90 #define HPRE_CLKGATE_CTL_EN BIT(0) 91 #define HPRE_PEH_CFG_AUTO_GATE_EN BIT(0) 92 #define HPRE_CLUSTER_DYN_CTL_EN BIT(0) 93 #define HPRE_CORE_GATE_EN (BIT(30) | BIT(31)) 94 95 #define HPRE_AM_OOO_SHUTDOWN_ENB 0x301044 96 #define HPRE_AM_OOO_SHUTDOWN_ENABLE BIT(0) 97 #define HPRE_WR_MSI_PORT BIT(2) 98 99 #define HPRE_CORE_ECC_2BIT_ERR BIT(1) 100 #define HPRE_OOO_ECC_2BIT_ERR BIT(5) 101 102 #define HPRE_QM_BME_FLR BIT(7) 103 #define HPRE_QM_PM_FLR BIT(11) 104 #define HPRE_QM_SRIOV_FLR BIT(12) 105 106 #define HPRE_SHAPER_TYPE_RATE 640 107 #define HPRE_VIA_MSI_DSM 1 108 #define HPRE_SQE_MASK_OFFSET 8 109 #define HPRE_SQE_MASK_LEN 24 110 111 #define HPRE_DFX_BASE 0x301000 112 #define HPRE_DFX_COMMON1 0x301400 113 #define HPRE_DFX_COMMON2 0x301A00 114 #define HPRE_DFX_CORE 0x302000 115 #define HPRE_DFX_BASE_LEN 0x55 116 #define HPRE_DFX_COMMON1_LEN 0x41 117 #define HPRE_DFX_COMMON2_LEN 0xE 118 #define HPRE_DFX_CORE_LEN 0x43 119 120 #define HPRE_DEV_ALG_MAX_LEN 256 121 122 static const char hpre_name[] = "hisi_hpre"; 123 static struct dentry *hpre_debugfs_root; 124 static const struct pci_device_id hpre_dev_ids[] = { 125 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_HPRE_PF) }, 126 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_HPRE_VF) }, 127 { 0, } 128 }; 129 130 MODULE_DEVICE_TABLE(pci, hpre_dev_ids); 131 132 struct hpre_hw_error { 133 u32 int_msk; 134 const char *msg; 135 }; 136 137 struct hpre_dev_alg { 138 u32 alg_msk; 139 const char *alg; 140 }; 141 142 static const struct hpre_dev_alg hpre_dev_algs[] = { 143 { 144 .alg_msk = BIT(0), 145 .alg = "rsa\n" 146 }, { 147 .alg_msk = BIT(1), 148 .alg = "dh\n" 149 }, { 150 .alg_msk = BIT(2), 151 .alg = "ecdh\n" 152 }, { 153 .alg_msk = BIT(3), 154 .alg = "ecdsa\n" 155 }, { 156 .alg_msk = BIT(4), 157 .alg = "sm2\n" 158 }, { 159 .alg_msk = BIT(5), 160 .alg = "x25519\n" 161 }, { 162 .alg_msk = BIT(6), 163 .alg = "x448\n" 164 }, { 165 /* sentinel */ 166 } 167 }; 168 169 static struct hisi_qm_list hpre_devices = { 170 .register_to_crypto = hpre_algs_register, 171 .unregister_from_crypto = hpre_algs_unregister, 172 }; 173 174 static const char * const hpre_debug_file_name[] = { 175 [HPRE_CLEAR_ENABLE] = "rdclr_en", 176 [HPRE_CLUSTER_CTRL] = "cluster_ctrl", 177 }; 178 179 enum hpre_cap_type { 180 HPRE_QM_NFE_MASK_CAP, 181 HPRE_QM_RESET_MASK_CAP, 182 HPRE_QM_OOO_SHUTDOWN_MASK_CAP, 183 HPRE_QM_CE_MASK_CAP, 184 HPRE_NFE_MASK_CAP, 185 HPRE_RESET_MASK_CAP, 186 HPRE_OOO_SHUTDOWN_MASK_CAP, 187 HPRE_CE_MASK_CAP, 188 HPRE_CLUSTER_NUM_CAP, 189 HPRE_CORE_TYPE_NUM_CAP, 190 HPRE_CORE_NUM_CAP, 191 HPRE_CLUSTER_CORE_NUM_CAP, 192 HPRE_CORE_ENABLE_BITMAP_CAP, 193 HPRE_DRV_ALG_BITMAP_CAP, 194 HPRE_DEV_ALG_BITMAP_CAP, 195 HPRE_CORE1_ALG_BITMAP_CAP, 196 HPRE_CORE2_ALG_BITMAP_CAP, 197 HPRE_CORE3_ALG_BITMAP_CAP, 198 HPRE_CORE4_ALG_BITMAP_CAP, 199 HPRE_CORE5_ALG_BITMAP_CAP, 200 HPRE_CORE6_ALG_BITMAP_CAP, 201 HPRE_CORE7_ALG_BITMAP_CAP, 202 HPRE_CORE8_ALG_BITMAP_CAP, 203 HPRE_CORE9_ALG_BITMAP_CAP, 204 HPRE_CORE10_ALG_BITMAP_CAP 205 }; 206 207 static const struct hisi_qm_cap_info hpre_basic_info[] = { 208 {HPRE_QM_NFE_MASK_CAP, 0x3124, 0, GENMASK(31, 0), 0x0, 0x1C37, 0x7C37}, 209 {HPRE_QM_RESET_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0xC37, 0x6C37}, 210 {HPRE_QM_OOO_SHUTDOWN_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0x4, 0x6C37}, 211 {HPRE_QM_CE_MASK_CAP, 0x312C, 0, GENMASK(31, 0), 0x0, 0x8, 0x8}, 212 {HPRE_NFE_MASK_CAP, 0x3130, 0, GENMASK(31, 0), 0x0, 0x3FFFFE, 0xFFFFFE}, 213 {HPRE_RESET_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x3FFFFE, 0xBFFFFE}, 214 {HPRE_OOO_SHUTDOWN_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x22, 0xBFFFFE}, 215 {HPRE_CE_MASK_CAP, 0x3138, 0, GENMASK(31, 0), 0x0, 0x1, 0x1}, 216 {HPRE_CLUSTER_NUM_CAP, 0x313c, 20, GENMASK(3, 0), 0x0, 0x4, 0x1}, 217 {HPRE_CORE_TYPE_NUM_CAP, 0x313c, 16, GENMASK(3, 0), 0x0, 0x2, 0x2}, 218 {HPRE_CORE_NUM_CAP, 0x313c, 8, GENMASK(7, 0), 0x0, 0x8, 0xA}, 219 {HPRE_CLUSTER_CORE_NUM_CAP, 0x313c, 0, GENMASK(7, 0), 0x0, 0x2, 0xA}, 220 {HPRE_CORE_ENABLE_BITMAP_CAP, 0x3140, 0, GENMASK(31, 0), 0x0, 0xF, 0x3FF}, 221 {HPRE_DRV_ALG_BITMAP_CAP, 0x3144, 0, GENMASK(31, 0), 0x0, 0x03, 0x27}, 222 {HPRE_DEV_ALG_BITMAP_CAP, 0x3148, 0, GENMASK(31, 0), 0x0, 0x03, 0x7F}, 223 {HPRE_CORE1_ALG_BITMAP_CAP, 0x314c, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F}, 224 {HPRE_CORE2_ALG_BITMAP_CAP, 0x3150, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F}, 225 {HPRE_CORE3_ALG_BITMAP_CAP, 0x3154, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F}, 226 {HPRE_CORE4_ALG_BITMAP_CAP, 0x3158, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F}, 227 {HPRE_CORE5_ALG_BITMAP_CAP, 0x315c, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F}, 228 {HPRE_CORE6_ALG_BITMAP_CAP, 0x3160, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F}, 229 {HPRE_CORE7_ALG_BITMAP_CAP, 0x3164, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F}, 230 {HPRE_CORE8_ALG_BITMAP_CAP, 0x3168, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F}, 231 {HPRE_CORE9_ALG_BITMAP_CAP, 0x316c, 0, GENMASK(31, 0), 0x0, 0x10, 0x10}, 232 {HPRE_CORE10_ALG_BITMAP_CAP, 0x3170, 0, GENMASK(31, 0), 0x0, 0x10, 0x10} 233 }; 234 235 static const struct hpre_hw_error hpre_hw_errors[] = { 236 { 237 .int_msk = BIT(0), 238 .msg = "core_ecc_1bit_err_int_set" 239 }, { 240 .int_msk = BIT(1), 241 .msg = "core_ecc_2bit_err_int_set" 242 }, { 243 .int_msk = BIT(2), 244 .msg = "dat_wb_poison_int_set" 245 }, { 246 .int_msk = BIT(3), 247 .msg = "dat_rd_poison_int_set" 248 }, { 249 .int_msk = BIT(4), 250 .msg = "bd_rd_poison_int_set" 251 }, { 252 .int_msk = BIT(5), 253 .msg = "ooo_ecc_2bit_err_int_set" 254 }, { 255 .int_msk = BIT(6), 256 .msg = "cluster1_shb_timeout_int_set" 257 }, { 258 .int_msk = BIT(7), 259 .msg = "cluster2_shb_timeout_int_set" 260 }, { 261 .int_msk = BIT(8), 262 .msg = "cluster3_shb_timeout_int_set" 263 }, { 264 .int_msk = BIT(9), 265 .msg = "cluster4_shb_timeout_int_set" 266 }, { 267 .int_msk = GENMASK(15, 10), 268 .msg = "ooo_rdrsp_err_int_set" 269 }, { 270 .int_msk = GENMASK(21, 16), 271 .msg = "ooo_wrrsp_err_int_set" 272 }, { 273 .int_msk = BIT(22), 274 .msg = "pt_rng_timeout_int_set" 275 }, { 276 .int_msk = BIT(23), 277 .msg = "sva_fsm_timeout_int_set" 278 }, { 279 /* sentinel */ 280 } 281 }; 282 283 static const u64 hpre_cluster_offsets[] = { 284 [HPRE_CLUSTER0] = 285 HPRE_CLSTR_BASE + HPRE_CLUSTER0 * HPRE_CLSTR_ADDR_INTRVL, 286 [HPRE_CLUSTER1] = 287 HPRE_CLSTR_BASE + HPRE_CLUSTER1 * HPRE_CLSTR_ADDR_INTRVL, 288 [HPRE_CLUSTER2] = 289 HPRE_CLSTR_BASE + HPRE_CLUSTER2 * HPRE_CLSTR_ADDR_INTRVL, 290 [HPRE_CLUSTER3] = 291 HPRE_CLSTR_BASE + HPRE_CLUSTER3 * HPRE_CLSTR_ADDR_INTRVL, 292 }; 293 294 static const struct debugfs_reg32 hpre_cluster_dfx_regs[] = { 295 {"CORES_EN_STATUS ", HPRE_CORE_EN_OFFSET}, 296 {"CORES_INI_CFG ", HPRE_CORE_INI_CFG_OFFSET}, 297 {"CORES_INI_STATUS ", HPRE_CORE_INI_STATUS_OFFSET}, 298 {"CORES_HTBT_WARN ", HPRE_CORE_HTBT_WARN_OFFSET}, 299 {"CORES_IS_SCHD ", HPRE_CORE_IS_SCHD_OFFSET}, 300 }; 301 302 static const struct debugfs_reg32 hpre_com_dfx_regs[] = { 303 {"READ_CLR_EN ", HPRE_CTRL_CNT_CLR_CE}, 304 {"AXQOS ", HPRE_VFG_AXQOS}, 305 {"AWUSR_CFG ", HPRE_AWUSR_FP_CFG}, 306 {"BD_ENDIAN ", HPRE_BD_ENDIAN}, 307 {"ECC_CHECK_CTRL ", HPRE_ECC_BYPASS}, 308 {"RAS_INT_WIDTH ", HPRE_RAS_WIDTH_CFG}, 309 {"POISON_BYPASS ", HPRE_POISON_BYPASS}, 310 {"BD_ARUSER ", HPRE_BD_ARUSR_CFG}, 311 {"BD_AWUSER ", HPRE_BD_AWUSR_CFG}, 312 {"DATA_ARUSER ", HPRE_DATA_RUSER_CFG}, 313 {"DATA_AWUSER ", HPRE_DATA_WUSER_CFG}, 314 {"INT_STATUS ", HPRE_INT_STATUS}, 315 {"INT_MASK ", HPRE_HAC_INT_MSK}, 316 {"RAS_CE_ENB ", HPRE_HAC_RAS_CE_ENB}, 317 {"RAS_NFE_ENB ", HPRE_HAC_RAS_NFE_ENB}, 318 {"RAS_FE_ENB ", HPRE_HAC_RAS_FE_ENB}, 319 {"INT_SET ", HPRE_HAC_INT_SET}, 320 {"RNG_TIMEOUT_NUM ", HPRE_RNG_TIMEOUT_NUM}, 321 }; 322 323 static const char *hpre_dfx_files[HPRE_DFX_FILE_NUM] = { 324 "send_cnt", 325 "recv_cnt", 326 "send_fail_cnt", 327 "send_busy_cnt", 328 "over_thrhld_cnt", 329 "overtime_thrhld", 330 "invalid_req_cnt" 331 }; 332 333 /* define the HPRE's dfx regs region and region length */ 334 static struct dfx_diff_registers hpre_diff_regs[] = { 335 { 336 .reg_offset = HPRE_DFX_BASE, 337 .reg_len = HPRE_DFX_BASE_LEN, 338 }, { 339 .reg_offset = HPRE_DFX_COMMON1, 340 .reg_len = HPRE_DFX_COMMON1_LEN, 341 }, { 342 .reg_offset = HPRE_DFX_COMMON2, 343 .reg_len = HPRE_DFX_COMMON2_LEN, 344 }, { 345 .reg_offset = HPRE_DFX_CORE, 346 .reg_len = HPRE_DFX_CORE_LEN, 347 }, 348 }; 349 350 bool hpre_check_alg_support(struct hisi_qm *qm, u32 alg) 351 { 352 u32 cap_val; 353 354 cap_val = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_DRV_ALG_BITMAP_CAP, qm->cap_ver); 355 if (alg & cap_val) 356 return true; 357 358 return false; 359 } 360 361 static int hpre_set_qm_algs(struct hisi_qm *qm) 362 { 363 struct device *dev = &qm->pdev->dev; 364 char *algs, *ptr; 365 u32 alg_msk; 366 int i; 367 368 if (!qm->use_sva) 369 return 0; 370 371 algs = devm_kzalloc(dev, HPRE_DEV_ALG_MAX_LEN * sizeof(char), GFP_KERNEL); 372 if (!algs) 373 return -ENOMEM; 374 375 alg_msk = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_DEV_ALG_BITMAP_CAP, qm->cap_ver); 376 377 for (i = 0; i < ARRAY_SIZE(hpre_dev_algs); i++) 378 if (alg_msk & hpre_dev_algs[i].alg_msk) 379 strcat(algs, hpre_dev_algs[i].alg); 380 381 ptr = strrchr(algs, '\n'); 382 if (ptr) 383 *ptr = '\0'; 384 385 qm->uacce->algs = algs; 386 387 return 0; 388 } 389 390 static int hpre_diff_regs_show(struct seq_file *s, void *unused) 391 { 392 struct hisi_qm *qm = s->private; 393 394 hisi_qm_acc_diff_regs_dump(qm, s, qm->debug.acc_diff_regs, 395 ARRAY_SIZE(hpre_diff_regs)); 396 397 return 0; 398 } 399 400 DEFINE_SHOW_ATTRIBUTE(hpre_diff_regs); 401 402 static int hpre_com_regs_show(struct seq_file *s, void *unused) 403 { 404 hisi_qm_regs_dump(s, s->private); 405 406 return 0; 407 } 408 409 DEFINE_SHOW_ATTRIBUTE(hpre_com_regs); 410 411 static int hpre_cluster_regs_show(struct seq_file *s, void *unused) 412 { 413 hisi_qm_regs_dump(s, s->private); 414 415 return 0; 416 } 417 418 DEFINE_SHOW_ATTRIBUTE(hpre_cluster_regs); 419 420 static const struct kernel_param_ops hpre_uacce_mode_ops = { 421 .set = uacce_mode_set, 422 .get = param_get_int, 423 }; 424 425 /* 426 * uacce_mode = 0 means hpre only register to crypto, 427 * uacce_mode = 1 means hpre both register to crypto and uacce. 428 */ 429 static u32 uacce_mode = UACCE_MODE_NOUACCE; 430 module_param_cb(uacce_mode, &hpre_uacce_mode_ops, &uacce_mode, 0444); 431 MODULE_PARM_DESC(uacce_mode, UACCE_MODE_DESC); 432 433 static int pf_q_num_set(const char *val, const struct kernel_param *kp) 434 { 435 return q_num_set(val, kp, PCI_DEVICE_ID_HUAWEI_HPRE_PF); 436 } 437 438 static const struct kernel_param_ops hpre_pf_q_num_ops = { 439 .set = pf_q_num_set, 440 .get = param_get_int, 441 }; 442 443 static u32 pf_q_num = HPRE_PF_DEF_Q_NUM; 444 module_param_cb(pf_q_num, &hpre_pf_q_num_ops, &pf_q_num, 0444); 445 MODULE_PARM_DESC(pf_q_num, "Number of queues in PF of CS(2-1024)"); 446 447 static const struct kernel_param_ops vfs_num_ops = { 448 .set = vfs_num_set, 449 .get = param_get_int, 450 }; 451 452 static u32 vfs_num; 453 module_param_cb(vfs_num, &vfs_num_ops, &vfs_num, 0444); 454 MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)"); 455 456 static inline int hpre_cluster_num(struct hisi_qm *qm) 457 { 458 return hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_CLUSTER_NUM_CAP, qm->cap_ver); 459 } 460 461 static inline int hpre_cluster_core_mask(struct hisi_qm *qm) 462 { 463 return hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_CORE_ENABLE_BITMAP_CAP, qm->cap_ver); 464 } 465 466 struct hisi_qp *hpre_create_qp(u8 type) 467 { 468 int node = cpu_to_node(smp_processor_id()); 469 struct hisi_qp *qp = NULL; 470 int ret; 471 472 if (type != HPRE_V2_ALG_TYPE && type != HPRE_V3_ECC_ALG_TYPE) 473 return NULL; 474 475 /* 476 * type: 0 - RSA/DH. algorithm supported in V2, 477 * 1 - ECC algorithm in V3. 478 */ 479 ret = hisi_qm_alloc_qps_node(&hpre_devices, 1, type, node, &qp); 480 if (!ret) 481 return qp; 482 483 return NULL; 484 } 485 486 static void hpre_config_pasid(struct hisi_qm *qm) 487 { 488 u32 val1, val2; 489 490 if (qm->ver >= QM_HW_V3) 491 return; 492 493 val1 = readl_relaxed(qm->io_base + HPRE_DATA_RUSER_CFG); 494 val2 = readl_relaxed(qm->io_base + HPRE_DATA_WUSER_CFG); 495 if (qm->use_sva) { 496 val1 |= BIT(HPRE_PASID_EN_BIT); 497 val2 |= BIT(HPRE_PASID_EN_BIT); 498 } else { 499 val1 &= ~BIT(HPRE_PASID_EN_BIT); 500 val2 &= ~BIT(HPRE_PASID_EN_BIT); 501 } 502 writel_relaxed(val1, qm->io_base + HPRE_DATA_RUSER_CFG); 503 writel_relaxed(val2, qm->io_base + HPRE_DATA_WUSER_CFG); 504 } 505 506 static int hpre_cfg_by_dsm(struct hisi_qm *qm) 507 { 508 struct device *dev = &qm->pdev->dev; 509 union acpi_object *obj; 510 guid_t guid; 511 512 if (guid_parse("b06b81ab-0134-4a45-9b0c-483447b95fa7", &guid)) { 513 dev_err(dev, "Hpre GUID failed\n"); 514 return -EINVAL; 515 } 516 517 /* Switch over to MSI handling due to non-standard PCI implementation */ 518 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &guid, 519 0, HPRE_VIA_MSI_DSM, NULL); 520 if (!obj) { 521 dev_err(dev, "ACPI handle failed!\n"); 522 return -EIO; 523 } 524 525 ACPI_FREE(obj); 526 527 return 0; 528 } 529 530 static int hpre_set_cluster(struct hisi_qm *qm) 531 { 532 u32 cluster_core_mask = hpre_cluster_core_mask(qm); 533 u8 clusters_num = hpre_cluster_num(qm); 534 struct device *dev = &qm->pdev->dev; 535 unsigned long offset; 536 u32 val = 0; 537 int ret, i; 538 539 for (i = 0; i < clusters_num; i++) { 540 offset = i * HPRE_CLSTR_ADDR_INTRVL; 541 542 /* clusters initiating */ 543 writel(cluster_core_mask, 544 qm->io_base + offset + HPRE_CORE_ENB); 545 writel(0x1, qm->io_base + offset + HPRE_CORE_INI_CFG); 546 ret = readl_relaxed_poll_timeout(qm->io_base + offset + 547 HPRE_CORE_INI_STATUS, val, 548 ((val & cluster_core_mask) == 549 cluster_core_mask), 550 HPRE_REG_RD_INTVRL_US, 551 HPRE_REG_RD_TMOUT_US); 552 if (ret) { 553 dev_err(dev, 554 "cluster %d int st status timeout!\n", i); 555 return -ETIMEDOUT; 556 } 557 } 558 559 return 0; 560 } 561 562 /* 563 * For Kunpeng 920, we should disable FLR triggered by hardware (BME/PM/SRIOV). 564 * Or it may stay in D3 state when we bind and unbind hpre quickly, 565 * as it does FLR triggered by hardware. 566 */ 567 static void disable_flr_of_bme(struct hisi_qm *qm) 568 { 569 u32 val; 570 571 val = readl(qm->io_base + QM_PEH_AXUSER_CFG); 572 val &= ~(HPRE_QM_BME_FLR | HPRE_QM_SRIOV_FLR); 573 val |= HPRE_QM_PM_FLR; 574 writel(val, qm->io_base + QM_PEH_AXUSER_CFG); 575 writel(PEH_AXUSER_CFG_ENABLE, qm->io_base + QM_PEH_AXUSER_CFG_ENABLE); 576 } 577 578 static void hpre_open_sva_prefetch(struct hisi_qm *qm) 579 { 580 u32 val; 581 int ret; 582 583 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) 584 return; 585 586 /* Enable prefetch */ 587 val = readl_relaxed(qm->io_base + HPRE_PREFETCH_CFG); 588 val &= HPRE_PREFETCH_ENABLE; 589 writel(val, qm->io_base + HPRE_PREFETCH_CFG); 590 591 ret = readl_relaxed_poll_timeout(qm->io_base + HPRE_PREFETCH_CFG, 592 val, !(val & HPRE_PREFETCH_DISABLE), 593 HPRE_REG_RD_INTVRL_US, 594 HPRE_REG_RD_TMOUT_US); 595 if (ret) 596 pci_err(qm->pdev, "failed to open sva prefetch\n"); 597 } 598 599 static void hpre_close_sva_prefetch(struct hisi_qm *qm) 600 { 601 u32 val; 602 int ret; 603 604 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) 605 return; 606 607 val = readl_relaxed(qm->io_base + HPRE_PREFETCH_CFG); 608 val |= HPRE_PREFETCH_DISABLE; 609 writel(val, qm->io_base + HPRE_PREFETCH_CFG); 610 611 ret = readl_relaxed_poll_timeout(qm->io_base + HPRE_SVA_PREFTCH_DFX, 612 val, !(val & HPRE_SVA_DISABLE_READY), 613 HPRE_REG_RD_INTVRL_US, 614 HPRE_REG_RD_TMOUT_US); 615 if (ret) 616 pci_err(qm->pdev, "failed to close sva prefetch\n"); 617 } 618 619 static void hpre_enable_clock_gate(struct hisi_qm *qm) 620 { 621 u32 val; 622 623 if (qm->ver < QM_HW_V3) 624 return; 625 626 val = readl(qm->io_base + HPRE_CLKGATE_CTL); 627 val |= HPRE_CLKGATE_CTL_EN; 628 writel(val, qm->io_base + HPRE_CLKGATE_CTL); 629 630 val = readl(qm->io_base + HPRE_PEH_CFG_AUTO_GATE); 631 val |= HPRE_PEH_CFG_AUTO_GATE_EN; 632 writel(val, qm->io_base + HPRE_PEH_CFG_AUTO_GATE); 633 634 val = readl(qm->io_base + HPRE_CLUSTER_DYN_CTL); 635 val |= HPRE_CLUSTER_DYN_CTL_EN; 636 writel(val, qm->io_base + HPRE_CLUSTER_DYN_CTL); 637 638 val = readl_relaxed(qm->io_base + HPRE_CORE_SHB_CFG); 639 val |= HPRE_CORE_GATE_EN; 640 writel(val, qm->io_base + HPRE_CORE_SHB_CFG); 641 } 642 643 static void hpre_disable_clock_gate(struct hisi_qm *qm) 644 { 645 u32 val; 646 647 if (qm->ver < QM_HW_V3) 648 return; 649 650 val = readl(qm->io_base + HPRE_CLKGATE_CTL); 651 val &= ~HPRE_CLKGATE_CTL_EN; 652 writel(val, qm->io_base + HPRE_CLKGATE_CTL); 653 654 val = readl(qm->io_base + HPRE_PEH_CFG_AUTO_GATE); 655 val &= ~HPRE_PEH_CFG_AUTO_GATE_EN; 656 writel(val, qm->io_base + HPRE_PEH_CFG_AUTO_GATE); 657 658 val = readl(qm->io_base + HPRE_CLUSTER_DYN_CTL); 659 val &= ~HPRE_CLUSTER_DYN_CTL_EN; 660 writel(val, qm->io_base + HPRE_CLUSTER_DYN_CTL); 661 662 val = readl_relaxed(qm->io_base + HPRE_CORE_SHB_CFG); 663 val &= ~HPRE_CORE_GATE_EN; 664 writel(val, qm->io_base + HPRE_CORE_SHB_CFG); 665 } 666 667 static int hpre_set_user_domain_and_cache(struct hisi_qm *qm) 668 { 669 struct device *dev = &qm->pdev->dev; 670 u32 val; 671 int ret; 672 673 /* disabel dynamic clock gate before sram init */ 674 hpre_disable_clock_gate(qm); 675 676 writel(HPRE_QM_USR_CFG_MASK, qm->io_base + QM_ARUSER_M_CFG_ENABLE); 677 writel(HPRE_QM_USR_CFG_MASK, qm->io_base + QM_AWUSER_M_CFG_ENABLE); 678 writel_relaxed(HPRE_QM_AXI_CFG_MASK, qm->io_base + QM_AXI_M_CFG); 679 680 /* HPRE need more time, we close this interrupt */ 681 val = readl_relaxed(qm->io_base + HPRE_QM_ABNML_INT_MASK); 682 val |= BIT(HPRE_TIMEOUT_ABNML_BIT); 683 writel_relaxed(val, qm->io_base + HPRE_QM_ABNML_INT_MASK); 684 685 if (qm->ver >= QM_HW_V3) 686 writel(HPRE_RSA_ENB | HPRE_ECC_ENB, 687 qm->io_base + HPRE_TYPES_ENB); 688 else 689 writel(HPRE_RSA_ENB, qm->io_base + HPRE_TYPES_ENB); 690 691 writel(HPRE_QM_VFG_AX_MASK, qm->io_base + HPRE_VFG_AXCACHE); 692 writel(0x0, qm->io_base + HPRE_BD_ENDIAN); 693 writel(0x0, qm->io_base + HPRE_INT_MASK); 694 writel(0x0, qm->io_base + HPRE_POISON_BYPASS); 695 writel(0x0, qm->io_base + HPRE_COMM_CNT_CLR_CE); 696 writel(0x0, qm->io_base + HPRE_ECC_BYPASS); 697 698 writel(HPRE_BD_USR_MASK, qm->io_base + HPRE_BD_ARUSR_CFG); 699 writel(HPRE_BD_USR_MASK, qm->io_base + HPRE_BD_AWUSR_CFG); 700 writel(0x1, qm->io_base + HPRE_RDCHN_INI_CFG); 701 ret = readl_relaxed_poll_timeout(qm->io_base + HPRE_RDCHN_INI_ST, val, 702 val & BIT(0), 703 HPRE_REG_RD_INTVRL_US, 704 HPRE_REG_RD_TMOUT_US); 705 if (ret) { 706 dev_err(dev, "read rd channel timeout fail!\n"); 707 return -ETIMEDOUT; 708 } 709 710 ret = hpre_set_cluster(qm); 711 if (ret) 712 return -ETIMEDOUT; 713 714 /* This setting is only needed by Kunpeng 920. */ 715 if (qm->ver == QM_HW_V2) { 716 ret = hpre_cfg_by_dsm(qm); 717 if (ret) 718 return ret; 719 720 disable_flr_of_bme(qm); 721 } 722 723 /* Config data buffer pasid needed by Kunpeng 920 */ 724 hpre_config_pasid(qm); 725 726 hpre_enable_clock_gate(qm); 727 728 return ret; 729 } 730 731 static void hpre_cnt_regs_clear(struct hisi_qm *qm) 732 { 733 u8 clusters_num = hpre_cluster_num(qm); 734 unsigned long offset; 735 int i; 736 737 /* clear clusterX/cluster_ctrl */ 738 for (i = 0; i < clusters_num; i++) { 739 offset = HPRE_CLSTR_BASE + i * HPRE_CLSTR_ADDR_INTRVL; 740 writel(0x0, qm->io_base + offset + HPRE_CLUSTER_INQURY); 741 } 742 743 /* clear rdclr_en */ 744 writel(0x0, qm->io_base + HPRE_CTRL_CNT_CLR_CE); 745 746 hisi_qm_debug_regs_clear(qm); 747 } 748 749 static void hpre_master_ooo_ctrl(struct hisi_qm *qm, bool enable) 750 { 751 u32 val1, val2; 752 753 val1 = readl(qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB); 754 if (enable) { 755 val1 |= HPRE_AM_OOO_SHUTDOWN_ENABLE; 756 val2 = hisi_qm_get_hw_info(qm, hpre_basic_info, 757 HPRE_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 758 } else { 759 val1 &= ~HPRE_AM_OOO_SHUTDOWN_ENABLE; 760 val2 = 0x0; 761 } 762 763 if (qm->ver > QM_HW_V2) 764 writel(val2, qm->io_base + HPRE_OOO_SHUTDOWN_SEL); 765 766 writel(val1, qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB); 767 } 768 769 static void hpre_hw_error_disable(struct hisi_qm *qm) 770 { 771 u32 ce, nfe; 772 773 ce = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_CE_MASK_CAP, qm->cap_ver); 774 nfe = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_NFE_MASK_CAP, qm->cap_ver); 775 776 /* disable hpre hw error interrupts */ 777 writel(ce | nfe | HPRE_HAC_RAS_FE_ENABLE, qm->io_base + HPRE_INT_MASK); 778 /* disable HPRE block master OOO when nfe occurs on Kunpeng930 */ 779 hpre_master_ooo_ctrl(qm, false); 780 } 781 782 static void hpre_hw_error_enable(struct hisi_qm *qm) 783 { 784 u32 ce, nfe; 785 786 ce = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_CE_MASK_CAP, qm->cap_ver); 787 nfe = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_NFE_MASK_CAP, qm->cap_ver); 788 789 /* clear HPRE hw error source if having */ 790 writel(ce | nfe | HPRE_HAC_RAS_FE_ENABLE, qm->io_base + HPRE_HAC_SOURCE_INT); 791 792 /* configure error type */ 793 writel(ce, qm->io_base + HPRE_RAS_CE_ENB); 794 writel(nfe, qm->io_base + HPRE_RAS_NFE_ENB); 795 writel(HPRE_HAC_RAS_FE_ENABLE, qm->io_base + HPRE_RAS_FE_ENB); 796 797 /* enable HPRE block master OOO when nfe occurs on Kunpeng930 */ 798 hpre_master_ooo_ctrl(qm, true); 799 800 /* enable hpre hw error interrupts */ 801 writel(HPRE_CORE_INT_ENABLE, qm->io_base + HPRE_INT_MASK); 802 } 803 804 static inline struct hisi_qm *hpre_file_to_qm(struct hpre_debugfs_file *file) 805 { 806 struct hpre *hpre = container_of(file->debug, struct hpre, debug); 807 808 return &hpre->qm; 809 } 810 811 static u32 hpre_clear_enable_read(struct hpre_debugfs_file *file) 812 { 813 struct hisi_qm *qm = hpre_file_to_qm(file); 814 815 return readl(qm->io_base + HPRE_CTRL_CNT_CLR_CE) & 816 HPRE_CTRL_CNT_CLR_CE_BIT; 817 } 818 819 static int hpre_clear_enable_write(struct hpre_debugfs_file *file, u32 val) 820 { 821 struct hisi_qm *qm = hpre_file_to_qm(file); 822 u32 tmp; 823 824 if (val != 1 && val != 0) 825 return -EINVAL; 826 827 tmp = (readl(qm->io_base + HPRE_CTRL_CNT_CLR_CE) & 828 ~HPRE_CTRL_CNT_CLR_CE_BIT) | val; 829 writel(tmp, qm->io_base + HPRE_CTRL_CNT_CLR_CE); 830 831 return 0; 832 } 833 834 static u32 hpre_cluster_inqry_read(struct hpre_debugfs_file *file) 835 { 836 struct hisi_qm *qm = hpre_file_to_qm(file); 837 int cluster_index = file->index - HPRE_CLUSTER_CTRL; 838 unsigned long offset = HPRE_CLSTR_BASE + 839 cluster_index * HPRE_CLSTR_ADDR_INTRVL; 840 841 return readl(qm->io_base + offset + HPRE_CLSTR_ADDR_INQRY_RSLT); 842 } 843 844 static void hpre_cluster_inqry_write(struct hpre_debugfs_file *file, u32 val) 845 { 846 struct hisi_qm *qm = hpre_file_to_qm(file); 847 int cluster_index = file->index - HPRE_CLUSTER_CTRL; 848 unsigned long offset = HPRE_CLSTR_BASE + cluster_index * 849 HPRE_CLSTR_ADDR_INTRVL; 850 851 writel(val, qm->io_base + offset + HPRE_CLUSTER_INQURY); 852 } 853 854 static ssize_t hpre_ctrl_debug_read(struct file *filp, char __user *buf, 855 size_t count, loff_t *pos) 856 { 857 struct hpre_debugfs_file *file = filp->private_data; 858 struct hisi_qm *qm = hpre_file_to_qm(file); 859 char tbuf[HPRE_DBGFS_VAL_MAX_LEN]; 860 u32 val; 861 int ret; 862 863 ret = hisi_qm_get_dfx_access(qm); 864 if (ret) 865 return ret; 866 867 spin_lock_irq(&file->lock); 868 switch (file->type) { 869 case HPRE_CLEAR_ENABLE: 870 val = hpre_clear_enable_read(file); 871 break; 872 case HPRE_CLUSTER_CTRL: 873 val = hpre_cluster_inqry_read(file); 874 break; 875 default: 876 goto err_input; 877 } 878 spin_unlock_irq(&file->lock); 879 880 hisi_qm_put_dfx_access(qm); 881 ret = snprintf(tbuf, HPRE_DBGFS_VAL_MAX_LEN, "%u\n", val); 882 return simple_read_from_buffer(buf, count, pos, tbuf, ret); 883 884 err_input: 885 spin_unlock_irq(&file->lock); 886 hisi_qm_put_dfx_access(qm); 887 return -EINVAL; 888 } 889 890 static ssize_t hpre_ctrl_debug_write(struct file *filp, const char __user *buf, 891 size_t count, loff_t *pos) 892 { 893 struct hpre_debugfs_file *file = filp->private_data; 894 struct hisi_qm *qm = hpre_file_to_qm(file); 895 char tbuf[HPRE_DBGFS_VAL_MAX_LEN]; 896 unsigned long val; 897 int len, ret; 898 899 if (*pos != 0) 900 return 0; 901 902 if (count >= HPRE_DBGFS_VAL_MAX_LEN) 903 return -ENOSPC; 904 905 len = simple_write_to_buffer(tbuf, HPRE_DBGFS_VAL_MAX_LEN - 1, 906 pos, buf, count); 907 if (len < 0) 908 return len; 909 910 tbuf[len] = '\0'; 911 if (kstrtoul(tbuf, 0, &val)) 912 return -EFAULT; 913 914 ret = hisi_qm_get_dfx_access(qm); 915 if (ret) 916 return ret; 917 918 spin_lock_irq(&file->lock); 919 switch (file->type) { 920 case HPRE_CLEAR_ENABLE: 921 ret = hpre_clear_enable_write(file, val); 922 if (ret) 923 goto err_input; 924 break; 925 case HPRE_CLUSTER_CTRL: 926 hpre_cluster_inqry_write(file, val); 927 break; 928 default: 929 ret = -EINVAL; 930 goto err_input; 931 } 932 933 ret = count; 934 935 err_input: 936 spin_unlock_irq(&file->lock); 937 hisi_qm_put_dfx_access(qm); 938 return ret; 939 } 940 941 static const struct file_operations hpre_ctrl_debug_fops = { 942 .owner = THIS_MODULE, 943 .open = simple_open, 944 .read = hpre_ctrl_debug_read, 945 .write = hpre_ctrl_debug_write, 946 }; 947 948 static int hpre_debugfs_atomic64_get(void *data, u64 *val) 949 { 950 struct hpre_dfx *dfx_item = data; 951 952 *val = atomic64_read(&dfx_item->value); 953 954 return 0; 955 } 956 957 static int hpre_debugfs_atomic64_set(void *data, u64 val) 958 { 959 struct hpre_dfx *dfx_item = data; 960 struct hpre_dfx *hpre_dfx = NULL; 961 962 if (dfx_item->type == HPRE_OVERTIME_THRHLD) { 963 hpre_dfx = dfx_item - HPRE_OVERTIME_THRHLD; 964 atomic64_set(&hpre_dfx[HPRE_OVER_THRHLD_CNT].value, 0); 965 } else if (val) { 966 return -EINVAL; 967 } 968 969 atomic64_set(&dfx_item->value, val); 970 971 return 0; 972 } 973 974 DEFINE_DEBUGFS_ATTRIBUTE(hpre_atomic64_ops, hpre_debugfs_atomic64_get, 975 hpre_debugfs_atomic64_set, "%llu\n"); 976 977 static int hpre_create_debugfs_file(struct hisi_qm *qm, struct dentry *dir, 978 enum hpre_ctrl_dbgfs_file type, int indx) 979 { 980 struct hpre *hpre = container_of(qm, struct hpre, qm); 981 struct hpre_debug *dbg = &hpre->debug; 982 struct dentry *file_dir; 983 984 if (dir) 985 file_dir = dir; 986 else 987 file_dir = qm->debug.debug_root; 988 989 if (type >= HPRE_DEBUG_FILE_NUM) 990 return -EINVAL; 991 992 spin_lock_init(&dbg->files[indx].lock); 993 dbg->files[indx].debug = dbg; 994 dbg->files[indx].type = type; 995 dbg->files[indx].index = indx; 996 debugfs_create_file(hpre_debug_file_name[type], 0600, file_dir, 997 dbg->files + indx, &hpre_ctrl_debug_fops); 998 999 return 0; 1000 } 1001 1002 static int hpre_pf_comm_regs_debugfs_init(struct hisi_qm *qm) 1003 { 1004 struct device *dev = &qm->pdev->dev; 1005 struct debugfs_regset32 *regset; 1006 1007 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 1008 if (!regset) 1009 return -ENOMEM; 1010 1011 regset->regs = hpre_com_dfx_regs; 1012 regset->nregs = ARRAY_SIZE(hpre_com_dfx_regs); 1013 regset->base = qm->io_base; 1014 regset->dev = dev; 1015 1016 debugfs_create_file("regs", 0444, qm->debug.debug_root, 1017 regset, &hpre_com_regs_fops); 1018 1019 return 0; 1020 } 1021 1022 static int hpre_cluster_debugfs_init(struct hisi_qm *qm) 1023 { 1024 u8 clusters_num = hpre_cluster_num(qm); 1025 struct device *dev = &qm->pdev->dev; 1026 char buf[HPRE_DBGFS_VAL_MAX_LEN]; 1027 struct debugfs_regset32 *regset; 1028 struct dentry *tmp_d; 1029 int i, ret; 1030 1031 for (i = 0; i < clusters_num; i++) { 1032 ret = snprintf(buf, HPRE_DBGFS_VAL_MAX_LEN, "cluster%d", i); 1033 if (ret < 0) 1034 return -EINVAL; 1035 tmp_d = debugfs_create_dir(buf, qm->debug.debug_root); 1036 1037 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 1038 if (!regset) 1039 return -ENOMEM; 1040 1041 regset->regs = hpre_cluster_dfx_regs; 1042 regset->nregs = ARRAY_SIZE(hpre_cluster_dfx_regs); 1043 regset->base = qm->io_base + hpre_cluster_offsets[i]; 1044 regset->dev = dev; 1045 1046 debugfs_create_file("regs", 0444, tmp_d, regset, 1047 &hpre_cluster_regs_fops); 1048 ret = hpre_create_debugfs_file(qm, tmp_d, HPRE_CLUSTER_CTRL, 1049 i + HPRE_CLUSTER_CTRL); 1050 if (ret) 1051 return ret; 1052 } 1053 1054 return 0; 1055 } 1056 1057 static int hpre_ctrl_debug_init(struct hisi_qm *qm) 1058 { 1059 int ret; 1060 1061 ret = hpre_create_debugfs_file(qm, NULL, HPRE_CLEAR_ENABLE, 1062 HPRE_CLEAR_ENABLE); 1063 if (ret) 1064 return ret; 1065 1066 ret = hpre_pf_comm_regs_debugfs_init(qm); 1067 if (ret) 1068 return ret; 1069 1070 return hpre_cluster_debugfs_init(qm); 1071 } 1072 1073 static void hpre_dfx_debug_init(struct hisi_qm *qm) 1074 { 1075 struct dfx_diff_registers *hpre_regs = qm->debug.acc_diff_regs; 1076 struct hpre *hpre = container_of(qm, struct hpre, qm); 1077 struct hpre_dfx *dfx = hpre->debug.dfx; 1078 struct dentry *parent; 1079 int i; 1080 1081 parent = debugfs_create_dir("hpre_dfx", qm->debug.debug_root); 1082 for (i = 0; i < HPRE_DFX_FILE_NUM; i++) { 1083 dfx[i].type = i; 1084 debugfs_create_file(hpre_dfx_files[i], 0644, parent, &dfx[i], 1085 &hpre_atomic64_ops); 1086 } 1087 1088 if (qm->fun_type == QM_HW_PF && hpre_regs) 1089 debugfs_create_file("diff_regs", 0444, parent, 1090 qm, &hpre_diff_regs_fops); 1091 } 1092 1093 static int hpre_debugfs_init(struct hisi_qm *qm) 1094 { 1095 struct device *dev = &qm->pdev->dev; 1096 int ret; 1097 1098 qm->debug.debug_root = debugfs_create_dir(dev_name(dev), 1099 hpre_debugfs_root); 1100 1101 qm->debug.sqe_mask_offset = HPRE_SQE_MASK_OFFSET; 1102 qm->debug.sqe_mask_len = HPRE_SQE_MASK_LEN; 1103 ret = hisi_qm_regs_debugfs_init(qm, hpre_diff_regs, ARRAY_SIZE(hpre_diff_regs)); 1104 if (ret) { 1105 dev_warn(dev, "Failed to init HPRE diff regs!\n"); 1106 goto debugfs_remove; 1107 } 1108 1109 hisi_qm_debug_init(qm); 1110 1111 if (qm->pdev->device == PCI_DEVICE_ID_HUAWEI_HPRE_PF) { 1112 ret = hpre_ctrl_debug_init(qm); 1113 if (ret) 1114 goto failed_to_create; 1115 } 1116 1117 hpre_dfx_debug_init(qm); 1118 1119 return 0; 1120 1121 failed_to_create: 1122 hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(hpre_diff_regs)); 1123 debugfs_remove: 1124 debugfs_remove_recursive(qm->debug.debug_root); 1125 return ret; 1126 } 1127 1128 static void hpre_debugfs_exit(struct hisi_qm *qm) 1129 { 1130 hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(hpre_diff_regs)); 1131 1132 debugfs_remove_recursive(qm->debug.debug_root); 1133 } 1134 1135 static int hpre_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) 1136 { 1137 int ret; 1138 1139 if (pdev->revision == QM_HW_V1) { 1140 pci_warn(pdev, "HPRE version 1 is not supported!\n"); 1141 return -EINVAL; 1142 } 1143 1144 qm->mode = uacce_mode; 1145 qm->pdev = pdev; 1146 qm->ver = pdev->revision; 1147 qm->sqe_size = HPRE_SQE_SIZE; 1148 qm->dev_name = hpre_name; 1149 1150 qm->fun_type = (pdev->device == PCI_DEVICE_ID_HUAWEI_HPRE_PF) ? 1151 QM_HW_PF : QM_HW_VF; 1152 if (qm->fun_type == QM_HW_PF) { 1153 qm->qp_base = HPRE_PF_DEF_Q_BASE; 1154 qm->qp_num = pf_q_num; 1155 qm->debug.curr_qm_qp_num = pf_q_num; 1156 qm->qm_list = &hpre_devices; 1157 } 1158 1159 ret = hisi_qm_init(qm); 1160 if (ret) { 1161 pci_err(pdev, "Failed to init hpre qm configures!\n"); 1162 return ret; 1163 } 1164 1165 ret = hpre_set_qm_algs(qm); 1166 if (ret) { 1167 pci_err(pdev, "Failed to set hpre algs!\n"); 1168 hisi_qm_uninit(qm); 1169 } 1170 1171 return ret; 1172 } 1173 1174 static int hpre_show_last_regs_init(struct hisi_qm *qm) 1175 { 1176 int cluster_dfx_regs_num = ARRAY_SIZE(hpre_cluster_dfx_regs); 1177 int com_dfx_regs_num = ARRAY_SIZE(hpre_com_dfx_regs); 1178 u8 clusters_num = hpre_cluster_num(qm); 1179 struct qm_debug *debug = &qm->debug; 1180 void __iomem *io_base; 1181 int i, j, idx; 1182 1183 debug->last_words = kcalloc(cluster_dfx_regs_num * clusters_num + 1184 com_dfx_regs_num, sizeof(unsigned int), GFP_KERNEL); 1185 if (!debug->last_words) 1186 return -ENOMEM; 1187 1188 for (i = 0; i < com_dfx_regs_num; i++) 1189 debug->last_words[i] = readl_relaxed(qm->io_base + 1190 hpre_com_dfx_regs[i].offset); 1191 1192 for (i = 0; i < clusters_num; i++) { 1193 io_base = qm->io_base + hpre_cluster_offsets[i]; 1194 for (j = 0; j < cluster_dfx_regs_num; j++) { 1195 idx = com_dfx_regs_num + i * cluster_dfx_regs_num + j; 1196 debug->last_words[idx] = readl_relaxed( 1197 io_base + hpre_cluster_dfx_regs[j].offset); 1198 } 1199 } 1200 1201 return 0; 1202 } 1203 1204 static void hpre_show_last_regs_uninit(struct hisi_qm *qm) 1205 { 1206 struct qm_debug *debug = &qm->debug; 1207 1208 if (qm->fun_type == QM_HW_VF || !debug->last_words) 1209 return; 1210 1211 kfree(debug->last_words); 1212 debug->last_words = NULL; 1213 } 1214 1215 static void hpre_show_last_dfx_regs(struct hisi_qm *qm) 1216 { 1217 int cluster_dfx_regs_num = ARRAY_SIZE(hpre_cluster_dfx_regs); 1218 int com_dfx_regs_num = ARRAY_SIZE(hpre_com_dfx_regs); 1219 u8 clusters_num = hpre_cluster_num(qm); 1220 struct qm_debug *debug = &qm->debug; 1221 struct pci_dev *pdev = qm->pdev; 1222 void __iomem *io_base; 1223 int i, j, idx; 1224 u32 val; 1225 1226 if (qm->fun_type == QM_HW_VF || !debug->last_words) 1227 return; 1228 1229 /* dumps last word of the debugging registers during controller reset */ 1230 for (i = 0; i < com_dfx_regs_num; i++) { 1231 val = readl_relaxed(qm->io_base + hpre_com_dfx_regs[i].offset); 1232 if (debug->last_words[i] != val) 1233 pci_info(pdev, "Common_core:%s \t= 0x%08x => 0x%08x\n", 1234 hpre_com_dfx_regs[i].name, debug->last_words[i], val); 1235 } 1236 1237 for (i = 0; i < clusters_num; i++) { 1238 io_base = qm->io_base + hpre_cluster_offsets[i]; 1239 for (j = 0; j < cluster_dfx_regs_num; j++) { 1240 val = readl_relaxed(io_base + 1241 hpre_cluster_dfx_regs[j].offset); 1242 idx = com_dfx_regs_num + i * cluster_dfx_regs_num + j; 1243 if (debug->last_words[idx] != val) 1244 pci_info(pdev, "cluster-%d:%s \t= 0x%08x => 0x%08x\n", 1245 i, hpre_cluster_dfx_regs[j].name, debug->last_words[idx], val); 1246 } 1247 } 1248 } 1249 1250 static void hpre_log_hw_error(struct hisi_qm *qm, u32 err_sts) 1251 { 1252 const struct hpre_hw_error *err = hpre_hw_errors; 1253 struct device *dev = &qm->pdev->dev; 1254 1255 while (err->msg) { 1256 if (err->int_msk & err_sts) 1257 dev_warn(dev, "%s [error status=0x%x] found\n", 1258 err->msg, err->int_msk); 1259 err++; 1260 } 1261 } 1262 1263 static u32 hpre_get_hw_err_status(struct hisi_qm *qm) 1264 { 1265 return readl(qm->io_base + HPRE_INT_STATUS); 1266 } 1267 1268 static void hpre_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts) 1269 { 1270 u32 nfe; 1271 1272 writel(err_sts, qm->io_base + HPRE_HAC_SOURCE_INT); 1273 nfe = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_NFE_MASK_CAP, qm->cap_ver); 1274 writel(nfe, qm->io_base + HPRE_RAS_NFE_ENB); 1275 } 1276 1277 static void hpre_open_axi_master_ooo(struct hisi_qm *qm) 1278 { 1279 u32 value; 1280 1281 value = readl(qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB); 1282 writel(value & ~HPRE_AM_OOO_SHUTDOWN_ENABLE, 1283 qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB); 1284 writel(value | HPRE_AM_OOO_SHUTDOWN_ENABLE, 1285 qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB); 1286 } 1287 1288 static void hpre_err_info_init(struct hisi_qm *qm) 1289 { 1290 struct hisi_qm_err_info *err_info = &qm->err_info; 1291 1292 err_info->fe = HPRE_HAC_RAS_FE_ENABLE; 1293 err_info->ce = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_QM_CE_MASK_CAP, qm->cap_ver); 1294 err_info->nfe = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_QM_NFE_MASK_CAP, qm->cap_ver); 1295 err_info->ecc_2bits_mask = HPRE_CORE_ECC_2BIT_ERR | HPRE_OOO_ECC_2BIT_ERR; 1296 err_info->dev_shutdown_mask = hisi_qm_get_hw_info(qm, hpre_basic_info, 1297 HPRE_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 1298 err_info->qm_shutdown_mask = hisi_qm_get_hw_info(qm, hpre_basic_info, 1299 HPRE_QM_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 1300 err_info->qm_reset_mask = hisi_qm_get_hw_info(qm, hpre_basic_info, 1301 HPRE_QM_RESET_MASK_CAP, qm->cap_ver); 1302 err_info->dev_reset_mask = hisi_qm_get_hw_info(qm, hpre_basic_info, 1303 HPRE_RESET_MASK_CAP, qm->cap_ver); 1304 err_info->msi_wr_port = HPRE_WR_MSI_PORT; 1305 err_info->acpi_rst = "HRST"; 1306 } 1307 1308 static const struct hisi_qm_err_ini hpre_err_ini = { 1309 .hw_init = hpre_set_user_domain_and_cache, 1310 .hw_err_enable = hpre_hw_error_enable, 1311 .hw_err_disable = hpre_hw_error_disable, 1312 .get_dev_hw_err_status = hpre_get_hw_err_status, 1313 .clear_dev_hw_err_status = hpre_clear_hw_err_status, 1314 .log_dev_hw_err = hpre_log_hw_error, 1315 .open_axi_master_ooo = hpre_open_axi_master_ooo, 1316 .open_sva_prefetch = hpre_open_sva_prefetch, 1317 .close_sva_prefetch = hpre_close_sva_prefetch, 1318 .show_last_dfx_regs = hpre_show_last_dfx_regs, 1319 .err_info_init = hpre_err_info_init, 1320 }; 1321 1322 static int hpre_pf_probe_init(struct hpre *hpre) 1323 { 1324 struct hisi_qm *qm = &hpre->qm; 1325 int ret; 1326 1327 ret = hpre_set_user_domain_and_cache(qm); 1328 if (ret) 1329 return ret; 1330 1331 hpre_open_sva_prefetch(qm); 1332 1333 qm->err_ini = &hpre_err_ini; 1334 qm->err_ini->err_info_init(qm); 1335 hisi_qm_dev_err_init(qm); 1336 ret = hpre_show_last_regs_init(qm); 1337 if (ret) 1338 pci_err(qm->pdev, "Failed to init last word regs!\n"); 1339 1340 return ret; 1341 } 1342 1343 static int hpre_probe_init(struct hpre *hpre) 1344 { 1345 u32 type_rate = HPRE_SHAPER_TYPE_RATE; 1346 struct hisi_qm *qm = &hpre->qm; 1347 int ret; 1348 1349 if (qm->fun_type == QM_HW_PF) { 1350 ret = hpre_pf_probe_init(hpre); 1351 if (ret) 1352 return ret; 1353 /* Enable shaper type 0 */ 1354 if (qm->ver >= QM_HW_V3) { 1355 type_rate |= QM_SHAPER_ENABLE; 1356 qm->type_rate = type_rate; 1357 } 1358 } 1359 1360 return 0; 1361 } 1362 1363 static int hpre_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1364 { 1365 struct hisi_qm *qm; 1366 struct hpre *hpre; 1367 int ret; 1368 1369 hpre = devm_kzalloc(&pdev->dev, sizeof(*hpre), GFP_KERNEL); 1370 if (!hpre) 1371 return -ENOMEM; 1372 1373 qm = &hpre->qm; 1374 ret = hpre_qm_init(qm, pdev); 1375 if (ret) { 1376 pci_err(pdev, "Failed to init HPRE QM (%d)!\n", ret); 1377 return ret; 1378 } 1379 1380 ret = hpre_probe_init(hpre); 1381 if (ret) { 1382 pci_err(pdev, "Failed to probe (%d)!\n", ret); 1383 goto err_with_qm_init; 1384 } 1385 1386 ret = hisi_qm_start(qm); 1387 if (ret) 1388 goto err_with_err_init; 1389 1390 ret = hpre_debugfs_init(qm); 1391 if (ret) 1392 dev_warn(&pdev->dev, "init debugfs fail!\n"); 1393 1394 ret = hisi_qm_alg_register(qm, &hpre_devices); 1395 if (ret < 0) { 1396 pci_err(pdev, "fail to register algs to crypto!\n"); 1397 goto err_with_qm_start; 1398 } 1399 1400 if (qm->uacce) { 1401 ret = uacce_register(qm->uacce); 1402 if (ret) { 1403 pci_err(pdev, "failed to register uacce (%d)!\n", ret); 1404 goto err_with_alg_register; 1405 } 1406 } 1407 1408 if (qm->fun_type == QM_HW_PF && vfs_num) { 1409 ret = hisi_qm_sriov_enable(pdev, vfs_num); 1410 if (ret < 0) 1411 goto err_with_alg_register; 1412 } 1413 1414 hisi_qm_pm_init(qm); 1415 1416 return 0; 1417 1418 err_with_alg_register: 1419 hisi_qm_alg_unregister(qm, &hpre_devices); 1420 1421 err_with_qm_start: 1422 hpre_debugfs_exit(qm); 1423 hisi_qm_stop(qm, QM_NORMAL); 1424 1425 err_with_err_init: 1426 hpre_show_last_regs_uninit(qm); 1427 hisi_qm_dev_err_uninit(qm); 1428 1429 err_with_qm_init: 1430 hisi_qm_uninit(qm); 1431 1432 return ret; 1433 } 1434 1435 static void hpre_remove(struct pci_dev *pdev) 1436 { 1437 struct hisi_qm *qm = pci_get_drvdata(pdev); 1438 1439 hisi_qm_pm_uninit(qm); 1440 hisi_qm_wait_task_finish(qm, &hpre_devices); 1441 hisi_qm_alg_unregister(qm, &hpre_devices); 1442 if (qm->fun_type == QM_HW_PF && qm->vfs_num) 1443 hisi_qm_sriov_disable(pdev, true); 1444 1445 hpre_debugfs_exit(qm); 1446 hisi_qm_stop(qm, QM_NORMAL); 1447 1448 if (qm->fun_type == QM_HW_PF) { 1449 hpre_cnt_regs_clear(qm); 1450 qm->debug.curr_qm_qp_num = 0; 1451 hpre_show_last_regs_uninit(qm); 1452 hisi_qm_dev_err_uninit(qm); 1453 } 1454 1455 hisi_qm_uninit(qm); 1456 } 1457 1458 static const struct dev_pm_ops hpre_pm_ops = { 1459 SET_RUNTIME_PM_OPS(hisi_qm_suspend, hisi_qm_resume, NULL) 1460 }; 1461 1462 static const struct pci_error_handlers hpre_err_handler = { 1463 .error_detected = hisi_qm_dev_err_detected, 1464 .slot_reset = hisi_qm_dev_slot_reset, 1465 .reset_prepare = hisi_qm_reset_prepare, 1466 .reset_done = hisi_qm_reset_done, 1467 }; 1468 1469 static struct pci_driver hpre_pci_driver = { 1470 .name = hpre_name, 1471 .id_table = hpre_dev_ids, 1472 .probe = hpre_probe, 1473 .remove = hpre_remove, 1474 .sriov_configure = IS_ENABLED(CONFIG_PCI_IOV) ? 1475 hisi_qm_sriov_configure : NULL, 1476 .err_handler = &hpre_err_handler, 1477 .shutdown = hisi_qm_dev_shutdown, 1478 .driver.pm = &hpre_pm_ops, 1479 }; 1480 1481 struct pci_driver *hisi_hpre_get_pf_driver(void) 1482 { 1483 return &hpre_pci_driver; 1484 } 1485 EXPORT_SYMBOL_GPL(hisi_hpre_get_pf_driver); 1486 1487 static void hpre_register_debugfs(void) 1488 { 1489 if (!debugfs_initialized()) 1490 return; 1491 1492 hpre_debugfs_root = debugfs_create_dir(hpre_name, NULL); 1493 } 1494 1495 static void hpre_unregister_debugfs(void) 1496 { 1497 debugfs_remove_recursive(hpre_debugfs_root); 1498 } 1499 1500 static int __init hpre_init(void) 1501 { 1502 int ret; 1503 1504 hisi_qm_init_list(&hpre_devices); 1505 hpre_register_debugfs(); 1506 1507 ret = pci_register_driver(&hpre_pci_driver); 1508 if (ret) { 1509 hpre_unregister_debugfs(); 1510 pr_err("hpre: can't register hisi hpre driver.\n"); 1511 } 1512 1513 return ret; 1514 } 1515 1516 static void __exit hpre_exit(void) 1517 { 1518 pci_unregister_driver(&hpre_pci_driver); 1519 hpre_unregister_debugfs(); 1520 } 1521 1522 module_init(hpre_init); 1523 module_exit(hpre_exit); 1524 1525 MODULE_LICENSE("GPL v2"); 1526 MODULE_AUTHOR("Zaibo Xu <xuzaibo@huawei.com>"); 1527 MODULE_AUTHOR("Meng Yu <yumeng18@huawei.com>"); 1528 MODULE_DESCRIPTION("Driver for HiSilicon HPRE accelerator"); 1529