1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018-2019 HiSilicon Limited. */ 3 #include <linux/acpi.h> 4 #include <linux/bitops.h> 5 #include <linux/debugfs.h> 6 #include <linux/init.h> 7 #include <linux/io.h> 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/pci.h> 11 #include <linux/pm_runtime.h> 12 #include <linux/topology.h> 13 #include <linux/uacce.h> 14 #include "hpre.h" 15 16 #define HPRE_QM_ABNML_INT_MASK 0x100004 17 #define HPRE_CTRL_CNT_CLR_CE_BIT BIT(0) 18 #define HPRE_COMM_CNT_CLR_CE 0x0 19 #define HPRE_CTRL_CNT_CLR_CE 0x301000 20 #define HPRE_FSM_MAX_CNT 0x301008 21 #define HPRE_VFG_AXQOS 0x30100c 22 #define HPRE_VFG_AXCACHE 0x301010 23 #define HPRE_RDCHN_INI_CFG 0x301014 24 #define HPRE_AWUSR_FP_CFG 0x301018 25 #define HPRE_BD_ENDIAN 0x301020 26 #define HPRE_ECC_BYPASS 0x301024 27 #define HPRE_RAS_WIDTH_CFG 0x301028 28 #define HPRE_POISON_BYPASS 0x30102c 29 #define HPRE_BD_ARUSR_CFG 0x301030 30 #define HPRE_BD_AWUSR_CFG 0x301034 31 #define HPRE_TYPES_ENB 0x301038 32 #define HPRE_RSA_ENB BIT(0) 33 #define HPRE_ECC_ENB BIT(1) 34 #define HPRE_DATA_RUSER_CFG 0x30103c 35 #define HPRE_DATA_WUSER_CFG 0x301040 36 #define HPRE_INT_MASK 0x301400 37 #define HPRE_INT_STATUS 0x301800 38 #define HPRE_HAC_INT_MSK 0x301400 39 #define HPRE_HAC_RAS_CE_ENB 0x301410 40 #define HPRE_HAC_RAS_NFE_ENB 0x301414 41 #define HPRE_HAC_RAS_FE_ENB 0x301418 42 #define HPRE_HAC_INT_SET 0x301500 43 #define HPRE_RNG_TIMEOUT_NUM 0x301A34 44 #define HPRE_CORE_INT_ENABLE 0 45 #define HPRE_CORE_INT_DISABLE GENMASK(21, 0) 46 #define HPRE_RDCHN_INI_ST 0x301a00 47 #define HPRE_CLSTR_BASE 0x302000 48 #define HPRE_CORE_EN_OFFSET 0x04 49 #define HPRE_CORE_INI_CFG_OFFSET 0x20 50 #define HPRE_CORE_INI_STATUS_OFFSET 0x80 51 #define HPRE_CORE_HTBT_WARN_OFFSET 0x8c 52 #define HPRE_CORE_IS_SCHD_OFFSET 0x90 53 54 #define HPRE_RAS_CE_ENB 0x301410 55 #define HPRE_RAS_NFE_ENB 0x301414 56 #define HPRE_RAS_FE_ENB 0x301418 57 #define HPRE_OOO_SHUTDOWN_SEL 0x301a3c 58 #define HPRE_HAC_RAS_FE_ENABLE 0 59 60 #define HPRE_CORE_ENB (HPRE_CLSTR_BASE + HPRE_CORE_EN_OFFSET) 61 #define HPRE_CORE_INI_CFG (HPRE_CLSTR_BASE + HPRE_CORE_INI_CFG_OFFSET) 62 #define HPRE_CORE_INI_STATUS (HPRE_CLSTR_BASE + HPRE_CORE_INI_STATUS_OFFSET) 63 #define HPRE_HAC_ECC1_CNT 0x301a04 64 #define HPRE_HAC_ECC2_CNT 0x301a08 65 #define HPRE_HAC_SOURCE_INT 0x301600 66 #define HPRE_CLSTR_ADDR_INTRVL 0x1000 67 #define HPRE_CLUSTER_INQURY 0x100 68 #define HPRE_CLSTR_ADDR_INQRY_RSLT 0x104 69 #define HPRE_TIMEOUT_ABNML_BIT 6 70 #define HPRE_PASID_EN_BIT 9 71 #define HPRE_REG_RD_INTVRL_US 10 72 #define HPRE_REG_RD_TMOUT_US 1000 73 #define HPRE_DBGFS_VAL_MAX_LEN 20 74 #define PCI_DEVICE_ID_HUAWEI_HPRE_PF 0xa258 75 #define HPRE_QM_USR_CFG_MASK GENMASK(31, 1) 76 #define HPRE_QM_AXI_CFG_MASK GENMASK(15, 0) 77 #define HPRE_QM_VFG_AX_MASK GENMASK(7, 0) 78 #define HPRE_BD_USR_MASK GENMASK(1, 0) 79 #define HPRE_PREFETCH_CFG 0x301130 80 #define HPRE_SVA_PREFTCH_DFX 0x30115C 81 #define HPRE_PREFETCH_ENABLE (~(BIT(0) | BIT(30))) 82 #define HPRE_PREFETCH_DISABLE BIT(30) 83 #define HPRE_SVA_DISABLE_READY (BIT(4) | BIT(8)) 84 85 /* clock gate */ 86 #define HPRE_CLKGATE_CTL 0x301a10 87 #define HPRE_PEH_CFG_AUTO_GATE 0x301a2c 88 #define HPRE_CLUSTER_DYN_CTL 0x302010 89 #define HPRE_CORE_SHB_CFG 0x302088 90 #define HPRE_CLKGATE_CTL_EN BIT(0) 91 #define HPRE_PEH_CFG_AUTO_GATE_EN BIT(0) 92 #define HPRE_CLUSTER_DYN_CTL_EN BIT(0) 93 #define HPRE_CORE_GATE_EN (BIT(30) | BIT(31)) 94 95 #define HPRE_AM_OOO_SHUTDOWN_ENB 0x301044 96 #define HPRE_AM_OOO_SHUTDOWN_ENABLE BIT(0) 97 #define HPRE_WR_MSI_PORT BIT(2) 98 99 #define HPRE_CORE_ECC_2BIT_ERR BIT(1) 100 #define HPRE_OOO_ECC_2BIT_ERR BIT(5) 101 102 #define HPRE_QM_BME_FLR BIT(7) 103 #define HPRE_QM_PM_FLR BIT(11) 104 #define HPRE_QM_SRIOV_FLR BIT(12) 105 106 #define HPRE_SHAPER_TYPE_RATE 640 107 #define HPRE_VIA_MSI_DSM 1 108 #define HPRE_SQE_MASK_OFFSET 8 109 #define HPRE_SQE_MASK_LEN 24 110 111 #define HPRE_DFX_BASE 0x301000 112 #define HPRE_DFX_COMMON1 0x301400 113 #define HPRE_DFX_COMMON2 0x301A00 114 #define HPRE_DFX_CORE 0x302000 115 #define HPRE_DFX_BASE_LEN 0x55 116 #define HPRE_DFX_COMMON1_LEN 0x41 117 #define HPRE_DFX_COMMON2_LEN 0xE 118 #define HPRE_DFX_CORE_LEN 0x43 119 120 #define HPRE_DEV_ALG_MAX_LEN 256 121 122 static const char hpre_name[] = "hisi_hpre"; 123 static struct dentry *hpre_debugfs_root; 124 static const struct pci_device_id hpre_dev_ids[] = { 125 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_HPRE_PF) }, 126 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_HPRE_VF) }, 127 { 0, } 128 }; 129 130 MODULE_DEVICE_TABLE(pci, hpre_dev_ids); 131 132 struct hpre_hw_error { 133 u32 int_msk; 134 const char *msg; 135 }; 136 137 struct hpre_dev_alg { 138 u32 alg_msk; 139 const char *alg; 140 }; 141 142 static const struct hpre_dev_alg hpre_dev_algs[] = { 143 { 144 .alg_msk = BIT(0), 145 .alg = "rsa\n" 146 }, { 147 .alg_msk = BIT(1), 148 .alg = "dh\n" 149 }, { 150 .alg_msk = BIT(2), 151 .alg = "ecdh\n" 152 }, { 153 .alg_msk = BIT(3), 154 .alg = "ecdsa\n" 155 }, { 156 .alg_msk = BIT(4), 157 .alg = "sm2\n" 158 }, { 159 .alg_msk = BIT(5), 160 .alg = "x25519\n" 161 }, { 162 .alg_msk = BIT(6), 163 .alg = "x448\n" 164 }, { 165 /* sentinel */ 166 } 167 }; 168 169 static struct hisi_qm_list hpre_devices = { 170 .register_to_crypto = hpre_algs_register, 171 .unregister_from_crypto = hpre_algs_unregister, 172 }; 173 174 static const char * const hpre_debug_file_name[] = { 175 [HPRE_CLEAR_ENABLE] = "rdclr_en", 176 [HPRE_CLUSTER_CTRL] = "cluster_ctrl", 177 }; 178 179 enum hpre_cap_type { 180 HPRE_QM_NFE_MASK_CAP, 181 HPRE_QM_RESET_MASK_CAP, 182 HPRE_QM_OOO_SHUTDOWN_MASK_CAP, 183 HPRE_QM_CE_MASK_CAP, 184 HPRE_NFE_MASK_CAP, 185 HPRE_RESET_MASK_CAP, 186 HPRE_OOO_SHUTDOWN_MASK_CAP, 187 HPRE_CE_MASK_CAP, 188 HPRE_CLUSTER_NUM_CAP, 189 HPRE_CORE_TYPE_NUM_CAP, 190 HPRE_CORE_NUM_CAP, 191 HPRE_CLUSTER_CORE_NUM_CAP, 192 HPRE_CORE_ENABLE_BITMAP_CAP, 193 HPRE_DRV_ALG_BITMAP_CAP, 194 HPRE_DEV_ALG_BITMAP_CAP, 195 HPRE_CORE1_ALG_BITMAP_CAP, 196 HPRE_CORE2_ALG_BITMAP_CAP, 197 HPRE_CORE3_ALG_BITMAP_CAP, 198 HPRE_CORE4_ALG_BITMAP_CAP, 199 HPRE_CORE5_ALG_BITMAP_CAP, 200 HPRE_CORE6_ALG_BITMAP_CAP, 201 HPRE_CORE7_ALG_BITMAP_CAP, 202 HPRE_CORE8_ALG_BITMAP_CAP, 203 HPRE_CORE9_ALG_BITMAP_CAP, 204 HPRE_CORE10_ALG_BITMAP_CAP 205 }; 206 207 static const struct hisi_qm_cap_info hpre_basic_info[] = { 208 {HPRE_QM_NFE_MASK_CAP, 0x3124, 0, GENMASK(31, 0), 0x0, 0x1C37, 0x7C37}, 209 {HPRE_QM_RESET_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0xC37, 0x6C37}, 210 {HPRE_QM_OOO_SHUTDOWN_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0x4, 0x6C37}, 211 {HPRE_QM_CE_MASK_CAP, 0x312C, 0, GENMASK(31, 0), 0x0, 0x8, 0x8}, 212 {HPRE_NFE_MASK_CAP, 0x3130, 0, GENMASK(31, 0), 0x0, 0x3FFFFE, 0x1FFFFFE}, 213 {HPRE_RESET_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x3FFFFE, 0xBFFFFE}, 214 {HPRE_OOO_SHUTDOWN_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x22, 0xBFFFFE}, 215 {HPRE_CE_MASK_CAP, 0x3138, 0, GENMASK(31, 0), 0x0, 0x1, 0x1}, 216 {HPRE_CLUSTER_NUM_CAP, 0x313c, 20, GENMASK(3, 0), 0x0, 0x4, 0x1}, 217 {HPRE_CORE_TYPE_NUM_CAP, 0x313c, 16, GENMASK(3, 0), 0x0, 0x2, 0x2}, 218 {HPRE_CORE_NUM_CAP, 0x313c, 8, GENMASK(7, 0), 0x0, 0x8, 0xA}, 219 {HPRE_CLUSTER_CORE_NUM_CAP, 0x313c, 0, GENMASK(7, 0), 0x0, 0x2, 0xA}, 220 {HPRE_CORE_ENABLE_BITMAP_CAP, 0x3140, 0, GENMASK(31, 0), 0x0, 0xF, 0x3FF}, 221 {HPRE_DRV_ALG_BITMAP_CAP, 0x3144, 0, GENMASK(31, 0), 0x0, 0x03, 0x27}, 222 {HPRE_DEV_ALG_BITMAP_CAP, 0x3148, 0, GENMASK(31, 0), 0x0, 0x03, 0x7F}, 223 {HPRE_CORE1_ALG_BITMAP_CAP, 0x314c, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F}, 224 {HPRE_CORE2_ALG_BITMAP_CAP, 0x3150, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F}, 225 {HPRE_CORE3_ALG_BITMAP_CAP, 0x3154, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F}, 226 {HPRE_CORE4_ALG_BITMAP_CAP, 0x3158, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F}, 227 {HPRE_CORE5_ALG_BITMAP_CAP, 0x315c, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F}, 228 {HPRE_CORE6_ALG_BITMAP_CAP, 0x3160, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F}, 229 {HPRE_CORE7_ALG_BITMAP_CAP, 0x3164, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F}, 230 {HPRE_CORE8_ALG_BITMAP_CAP, 0x3168, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F}, 231 {HPRE_CORE9_ALG_BITMAP_CAP, 0x316c, 0, GENMASK(31, 0), 0x0, 0x10, 0x10}, 232 {HPRE_CORE10_ALG_BITMAP_CAP, 0x3170, 0, GENMASK(31, 0), 0x0, 0x10, 0x10} 233 }; 234 235 static const struct hpre_hw_error hpre_hw_errors[] = { 236 { 237 .int_msk = BIT(0), 238 .msg = "core_ecc_1bit_err_int_set" 239 }, { 240 .int_msk = BIT(1), 241 .msg = "core_ecc_2bit_err_int_set" 242 }, { 243 .int_msk = BIT(2), 244 .msg = "dat_wb_poison_int_set" 245 }, { 246 .int_msk = BIT(3), 247 .msg = "dat_rd_poison_int_set" 248 }, { 249 .int_msk = BIT(4), 250 .msg = "bd_rd_poison_int_set" 251 }, { 252 .int_msk = BIT(5), 253 .msg = "ooo_ecc_2bit_err_int_set" 254 }, { 255 .int_msk = BIT(6), 256 .msg = "cluster1_shb_timeout_int_set" 257 }, { 258 .int_msk = BIT(7), 259 .msg = "cluster2_shb_timeout_int_set" 260 }, { 261 .int_msk = BIT(8), 262 .msg = "cluster3_shb_timeout_int_set" 263 }, { 264 .int_msk = BIT(9), 265 .msg = "cluster4_shb_timeout_int_set" 266 }, { 267 .int_msk = GENMASK(15, 10), 268 .msg = "ooo_rdrsp_err_int_set" 269 }, { 270 .int_msk = GENMASK(21, 16), 271 .msg = "ooo_wrrsp_err_int_set" 272 }, { 273 .int_msk = BIT(22), 274 .msg = "pt_rng_timeout_int_set" 275 }, { 276 .int_msk = BIT(23), 277 .msg = "sva_fsm_timeout_int_set" 278 }, { 279 .int_msk = BIT(24), 280 .msg = "sva_int_set" 281 }, { 282 /* sentinel */ 283 } 284 }; 285 286 static const u64 hpre_cluster_offsets[] = { 287 [HPRE_CLUSTER0] = 288 HPRE_CLSTR_BASE + HPRE_CLUSTER0 * HPRE_CLSTR_ADDR_INTRVL, 289 [HPRE_CLUSTER1] = 290 HPRE_CLSTR_BASE + HPRE_CLUSTER1 * HPRE_CLSTR_ADDR_INTRVL, 291 [HPRE_CLUSTER2] = 292 HPRE_CLSTR_BASE + HPRE_CLUSTER2 * HPRE_CLSTR_ADDR_INTRVL, 293 [HPRE_CLUSTER3] = 294 HPRE_CLSTR_BASE + HPRE_CLUSTER3 * HPRE_CLSTR_ADDR_INTRVL, 295 }; 296 297 static const struct debugfs_reg32 hpre_cluster_dfx_regs[] = { 298 {"CORES_EN_STATUS ", HPRE_CORE_EN_OFFSET}, 299 {"CORES_INI_CFG ", HPRE_CORE_INI_CFG_OFFSET}, 300 {"CORES_INI_STATUS ", HPRE_CORE_INI_STATUS_OFFSET}, 301 {"CORES_HTBT_WARN ", HPRE_CORE_HTBT_WARN_OFFSET}, 302 {"CORES_IS_SCHD ", HPRE_CORE_IS_SCHD_OFFSET}, 303 }; 304 305 static const struct debugfs_reg32 hpre_com_dfx_regs[] = { 306 {"READ_CLR_EN ", HPRE_CTRL_CNT_CLR_CE}, 307 {"AXQOS ", HPRE_VFG_AXQOS}, 308 {"AWUSR_CFG ", HPRE_AWUSR_FP_CFG}, 309 {"BD_ENDIAN ", HPRE_BD_ENDIAN}, 310 {"ECC_CHECK_CTRL ", HPRE_ECC_BYPASS}, 311 {"RAS_INT_WIDTH ", HPRE_RAS_WIDTH_CFG}, 312 {"POISON_BYPASS ", HPRE_POISON_BYPASS}, 313 {"BD_ARUSER ", HPRE_BD_ARUSR_CFG}, 314 {"BD_AWUSER ", HPRE_BD_AWUSR_CFG}, 315 {"DATA_ARUSER ", HPRE_DATA_RUSER_CFG}, 316 {"DATA_AWUSER ", HPRE_DATA_WUSER_CFG}, 317 {"INT_STATUS ", HPRE_INT_STATUS}, 318 {"INT_MASK ", HPRE_HAC_INT_MSK}, 319 {"RAS_CE_ENB ", HPRE_HAC_RAS_CE_ENB}, 320 {"RAS_NFE_ENB ", HPRE_HAC_RAS_NFE_ENB}, 321 {"RAS_FE_ENB ", HPRE_HAC_RAS_FE_ENB}, 322 {"INT_SET ", HPRE_HAC_INT_SET}, 323 {"RNG_TIMEOUT_NUM ", HPRE_RNG_TIMEOUT_NUM}, 324 }; 325 326 static const char *hpre_dfx_files[HPRE_DFX_FILE_NUM] = { 327 "send_cnt", 328 "recv_cnt", 329 "send_fail_cnt", 330 "send_busy_cnt", 331 "over_thrhld_cnt", 332 "overtime_thrhld", 333 "invalid_req_cnt" 334 }; 335 336 /* define the HPRE's dfx regs region and region length */ 337 static struct dfx_diff_registers hpre_diff_regs[] = { 338 { 339 .reg_offset = HPRE_DFX_BASE, 340 .reg_len = HPRE_DFX_BASE_LEN, 341 }, { 342 .reg_offset = HPRE_DFX_COMMON1, 343 .reg_len = HPRE_DFX_COMMON1_LEN, 344 }, { 345 .reg_offset = HPRE_DFX_COMMON2, 346 .reg_len = HPRE_DFX_COMMON2_LEN, 347 }, { 348 .reg_offset = HPRE_DFX_CORE, 349 .reg_len = HPRE_DFX_CORE_LEN, 350 }, 351 }; 352 353 bool hpre_check_alg_support(struct hisi_qm *qm, u32 alg) 354 { 355 u32 cap_val; 356 357 cap_val = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_DRV_ALG_BITMAP_CAP, qm->cap_ver); 358 if (alg & cap_val) 359 return true; 360 361 return false; 362 } 363 364 static int hpre_set_qm_algs(struct hisi_qm *qm) 365 { 366 struct device *dev = &qm->pdev->dev; 367 char *algs, *ptr; 368 u32 alg_msk; 369 int i; 370 371 if (!qm->use_sva) 372 return 0; 373 374 algs = devm_kzalloc(dev, HPRE_DEV_ALG_MAX_LEN * sizeof(char), GFP_KERNEL); 375 if (!algs) 376 return -ENOMEM; 377 378 alg_msk = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_DEV_ALG_BITMAP_CAP, qm->cap_ver); 379 380 for (i = 0; i < ARRAY_SIZE(hpre_dev_algs); i++) 381 if (alg_msk & hpre_dev_algs[i].alg_msk) 382 strcat(algs, hpre_dev_algs[i].alg); 383 384 ptr = strrchr(algs, '\n'); 385 if (ptr) 386 *ptr = '\0'; 387 388 qm->uacce->algs = algs; 389 390 return 0; 391 } 392 393 static int hpre_diff_regs_show(struct seq_file *s, void *unused) 394 { 395 struct hisi_qm *qm = s->private; 396 397 hisi_qm_acc_diff_regs_dump(qm, s, qm->debug.acc_diff_regs, 398 ARRAY_SIZE(hpre_diff_regs)); 399 400 return 0; 401 } 402 403 DEFINE_SHOW_ATTRIBUTE(hpre_diff_regs); 404 405 static int hpre_com_regs_show(struct seq_file *s, void *unused) 406 { 407 hisi_qm_regs_dump(s, s->private); 408 409 return 0; 410 } 411 412 DEFINE_SHOW_ATTRIBUTE(hpre_com_regs); 413 414 static int hpre_cluster_regs_show(struct seq_file *s, void *unused) 415 { 416 hisi_qm_regs_dump(s, s->private); 417 418 return 0; 419 } 420 421 DEFINE_SHOW_ATTRIBUTE(hpre_cluster_regs); 422 423 static const struct kernel_param_ops hpre_uacce_mode_ops = { 424 .set = uacce_mode_set, 425 .get = param_get_int, 426 }; 427 428 /* 429 * uacce_mode = 0 means hpre only register to crypto, 430 * uacce_mode = 1 means hpre both register to crypto and uacce. 431 */ 432 static u32 uacce_mode = UACCE_MODE_NOUACCE; 433 module_param_cb(uacce_mode, &hpre_uacce_mode_ops, &uacce_mode, 0444); 434 MODULE_PARM_DESC(uacce_mode, UACCE_MODE_DESC); 435 436 static bool pf_q_num_flag; 437 static int pf_q_num_set(const char *val, const struct kernel_param *kp) 438 { 439 pf_q_num_flag = true; 440 441 return q_num_set(val, kp, PCI_DEVICE_ID_HUAWEI_HPRE_PF); 442 } 443 444 static const struct kernel_param_ops hpre_pf_q_num_ops = { 445 .set = pf_q_num_set, 446 .get = param_get_int, 447 }; 448 449 static u32 pf_q_num = HPRE_PF_DEF_Q_NUM; 450 module_param_cb(pf_q_num, &hpre_pf_q_num_ops, &pf_q_num, 0444); 451 MODULE_PARM_DESC(pf_q_num, "Number of queues in PF of CS(2-1024)"); 452 453 static const struct kernel_param_ops vfs_num_ops = { 454 .set = vfs_num_set, 455 .get = param_get_int, 456 }; 457 458 static u32 vfs_num; 459 module_param_cb(vfs_num, &vfs_num_ops, &vfs_num, 0444); 460 MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)"); 461 462 static inline int hpre_cluster_num(struct hisi_qm *qm) 463 { 464 return hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_CLUSTER_NUM_CAP, qm->cap_ver); 465 } 466 467 static inline int hpre_cluster_core_mask(struct hisi_qm *qm) 468 { 469 return hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_CORE_ENABLE_BITMAP_CAP, qm->cap_ver); 470 } 471 472 struct hisi_qp *hpre_create_qp(u8 type) 473 { 474 int node = cpu_to_node(smp_processor_id()); 475 struct hisi_qp *qp = NULL; 476 int ret; 477 478 if (type != HPRE_V2_ALG_TYPE && type != HPRE_V3_ECC_ALG_TYPE) 479 return NULL; 480 481 /* 482 * type: 0 - RSA/DH. algorithm supported in V2, 483 * 1 - ECC algorithm in V3. 484 */ 485 ret = hisi_qm_alloc_qps_node(&hpre_devices, 1, type, node, &qp); 486 if (!ret) 487 return qp; 488 489 return NULL; 490 } 491 492 static void hpre_config_pasid(struct hisi_qm *qm) 493 { 494 u32 val1, val2; 495 496 if (qm->ver >= QM_HW_V3) 497 return; 498 499 val1 = readl_relaxed(qm->io_base + HPRE_DATA_RUSER_CFG); 500 val2 = readl_relaxed(qm->io_base + HPRE_DATA_WUSER_CFG); 501 if (qm->use_sva) { 502 val1 |= BIT(HPRE_PASID_EN_BIT); 503 val2 |= BIT(HPRE_PASID_EN_BIT); 504 } else { 505 val1 &= ~BIT(HPRE_PASID_EN_BIT); 506 val2 &= ~BIT(HPRE_PASID_EN_BIT); 507 } 508 writel_relaxed(val1, qm->io_base + HPRE_DATA_RUSER_CFG); 509 writel_relaxed(val2, qm->io_base + HPRE_DATA_WUSER_CFG); 510 } 511 512 static int hpre_cfg_by_dsm(struct hisi_qm *qm) 513 { 514 struct device *dev = &qm->pdev->dev; 515 union acpi_object *obj; 516 guid_t guid; 517 518 if (guid_parse("b06b81ab-0134-4a45-9b0c-483447b95fa7", &guid)) { 519 dev_err(dev, "Hpre GUID failed\n"); 520 return -EINVAL; 521 } 522 523 /* Switch over to MSI handling due to non-standard PCI implementation */ 524 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &guid, 525 0, HPRE_VIA_MSI_DSM, NULL); 526 if (!obj) { 527 dev_err(dev, "ACPI handle failed!\n"); 528 return -EIO; 529 } 530 531 ACPI_FREE(obj); 532 533 return 0; 534 } 535 536 static int hpre_set_cluster(struct hisi_qm *qm) 537 { 538 u32 cluster_core_mask = hpre_cluster_core_mask(qm); 539 u8 clusters_num = hpre_cluster_num(qm); 540 struct device *dev = &qm->pdev->dev; 541 unsigned long offset; 542 u32 val = 0; 543 int ret, i; 544 545 for (i = 0; i < clusters_num; i++) { 546 offset = i * HPRE_CLSTR_ADDR_INTRVL; 547 548 /* clusters initiating */ 549 writel(cluster_core_mask, 550 qm->io_base + offset + HPRE_CORE_ENB); 551 writel(0x1, qm->io_base + offset + HPRE_CORE_INI_CFG); 552 ret = readl_relaxed_poll_timeout(qm->io_base + offset + 553 HPRE_CORE_INI_STATUS, val, 554 ((val & cluster_core_mask) == 555 cluster_core_mask), 556 HPRE_REG_RD_INTVRL_US, 557 HPRE_REG_RD_TMOUT_US); 558 if (ret) { 559 dev_err(dev, 560 "cluster %d int st status timeout!\n", i); 561 return -ETIMEDOUT; 562 } 563 } 564 565 return 0; 566 } 567 568 /* 569 * For Kunpeng 920, we should disable FLR triggered by hardware (BME/PM/SRIOV). 570 * Or it may stay in D3 state when we bind and unbind hpre quickly, 571 * as it does FLR triggered by hardware. 572 */ 573 static void disable_flr_of_bme(struct hisi_qm *qm) 574 { 575 u32 val; 576 577 val = readl(qm->io_base + QM_PEH_AXUSER_CFG); 578 val &= ~(HPRE_QM_BME_FLR | HPRE_QM_SRIOV_FLR); 579 val |= HPRE_QM_PM_FLR; 580 writel(val, qm->io_base + QM_PEH_AXUSER_CFG); 581 writel(PEH_AXUSER_CFG_ENABLE, qm->io_base + QM_PEH_AXUSER_CFG_ENABLE); 582 } 583 584 static void hpre_open_sva_prefetch(struct hisi_qm *qm) 585 { 586 u32 val; 587 int ret; 588 589 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) 590 return; 591 592 /* Enable prefetch */ 593 val = readl_relaxed(qm->io_base + HPRE_PREFETCH_CFG); 594 val &= HPRE_PREFETCH_ENABLE; 595 writel(val, qm->io_base + HPRE_PREFETCH_CFG); 596 597 ret = readl_relaxed_poll_timeout(qm->io_base + HPRE_PREFETCH_CFG, 598 val, !(val & HPRE_PREFETCH_DISABLE), 599 HPRE_REG_RD_INTVRL_US, 600 HPRE_REG_RD_TMOUT_US); 601 if (ret) 602 pci_err(qm->pdev, "failed to open sva prefetch\n"); 603 } 604 605 static void hpre_close_sva_prefetch(struct hisi_qm *qm) 606 { 607 u32 val; 608 int ret; 609 610 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) 611 return; 612 613 val = readl_relaxed(qm->io_base + HPRE_PREFETCH_CFG); 614 val |= HPRE_PREFETCH_DISABLE; 615 writel(val, qm->io_base + HPRE_PREFETCH_CFG); 616 617 ret = readl_relaxed_poll_timeout(qm->io_base + HPRE_SVA_PREFTCH_DFX, 618 val, !(val & HPRE_SVA_DISABLE_READY), 619 HPRE_REG_RD_INTVRL_US, 620 HPRE_REG_RD_TMOUT_US); 621 if (ret) 622 pci_err(qm->pdev, "failed to close sva prefetch\n"); 623 } 624 625 static void hpre_enable_clock_gate(struct hisi_qm *qm) 626 { 627 u32 val; 628 629 if (qm->ver < QM_HW_V3) 630 return; 631 632 val = readl(qm->io_base + HPRE_CLKGATE_CTL); 633 val |= HPRE_CLKGATE_CTL_EN; 634 writel(val, qm->io_base + HPRE_CLKGATE_CTL); 635 636 val = readl(qm->io_base + HPRE_PEH_CFG_AUTO_GATE); 637 val |= HPRE_PEH_CFG_AUTO_GATE_EN; 638 writel(val, qm->io_base + HPRE_PEH_CFG_AUTO_GATE); 639 640 val = readl(qm->io_base + HPRE_CLUSTER_DYN_CTL); 641 val |= HPRE_CLUSTER_DYN_CTL_EN; 642 writel(val, qm->io_base + HPRE_CLUSTER_DYN_CTL); 643 644 val = readl_relaxed(qm->io_base + HPRE_CORE_SHB_CFG); 645 val |= HPRE_CORE_GATE_EN; 646 writel(val, qm->io_base + HPRE_CORE_SHB_CFG); 647 } 648 649 static void hpre_disable_clock_gate(struct hisi_qm *qm) 650 { 651 u32 val; 652 653 if (qm->ver < QM_HW_V3) 654 return; 655 656 val = readl(qm->io_base + HPRE_CLKGATE_CTL); 657 val &= ~HPRE_CLKGATE_CTL_EN; 658 writel(val, qm->io_base + HPRE_CLKGATE_CTL); 659 660 val = readl(qm->io_base + HPRE_PEH_CFG_AUTO_GATE); 661 val &= ~HPRE_PEH_CFG_AUTO_GATE_EN; 662 writel(val, qm->io_base + HPRE_PEH_CFG_AUTO_GATE); 663 664 val = readl(qm->io_base + HPRE_CLUSTER_DYN_CTL); 665 val &= ~HPRE_CLUSTER_DYN_CTL_EN; 666 writel(val, qm->io_base + HPRE_CLUSTER_DYN_CTL); 667 668 val = readl_relaxed(qm->io_base + HPRE_CORE_SHB_CFG); 669 val &= ~HPRE_CORE_GATE_EN; 670 writel(val, qm->io_base + HPRE_CORE_SHB_CFG); 671 } 672 673 static int hpre_set_user_domain_and_cache(struct hisi_qm *qm) 674 { 675 struct device *dev = &qm->pdev->dev; 676 u32 val; 677 int ret; 678 679 /* disabel dynamic clock gate before sram init */ 680 hpre_disable_clock_gate(qm); 681 682 writel(HPRE_QM_USR_CFG_MASK, qm->io_base + QM_ARUSER_M_CFG_ENABLE); 683 writel(HPRE_QM_USR_CFG_MASK, qm->io_base + QM_AWUSER_M_CFG_ENABLE); 684 writel_relaxed(HPRE_QM_AXI_CFG_MASK, qm->io_base + QM_AXI_M_CFG); 685 686 /* HPRE need more time, we close this interrupt */ 687 val = readl_relaxed(qm->io_base + HPRE_QM_ABNML_INT_MASK); 688 val |= BIT(HPRE_TIMEOUT_ABNML_BIT); 689 writel_relaxed(val, qm->io_base + HPRE_QM_ABNML_INT_MASK); 690 691 if (qm->ver >= QM_HW_V3) 692 writel(HPRE_RSA_ENB | HPRE_ECC_ENB, 693 qm->io_base + HPRE_TYPES_ENB); 694 else 695 writel(HPRE_RSA_ENB, qm->io_base + HPRE_TYPES_ENB); 696 697 writel(HPRE_QM_VFG_AX_MASK, qm->io_base + HPRE_VFG_AXCACHE); 698 writel(0x0, qm->io_base + HPRE_BD_ENDIAN); 699 writel(0x0, qm->io_base + HPRE_INT_MASK); 700 writel(0x0, qm->io_base + HPRE_POISON_BYPASS); 701 writel(0x0, qm->io_base + HPRE_COMM_CNT_CLR_CE); 702 writel(0x0, qm->io_base + HPRE_ECC_BYPASS); 703 704 writel(HPRE_BD_USR_MASK, qm->io_base + HPRE_BD_ARUSR_CFG); 705 writel(HPRE_BD_USR_MASK, qm->io_base + HPRE_BD_AWUSR_CFG); 706 writel(0x1, qm->io_base + HPRE_RDCHN_INI_CFG); 707 ret = readl_relaxed_poll_timeout(qm->io_base + HPRE_RDCHN_INI_ST, val, 708 val & BIT(0), 709 HPRE_REG_RD_INTVRL_US, 710 HPRE_REG_RD_TMOUT_US); 711 if (ret) { 712 dev_err(dev, "read rd channel timeout fail!\n"); 713 return -ETIMEDOUT; 714 } 715 716 ret = hpre_set_cluster(qm); 717 if (ret) 718 return -ETIMEDOUT; 719 720 /* This setting is only needed by Kunpeng 920. */ 721 if (qm->ver == QM_HW_V2) { 722 ret = hpre_cfg_by_dsm(qm); 723 if (ret) 724 return ret; 725 726 disable_flr_of_bme(qm); 727 } 728 729 /* Config data buffer pasid needed by Kunpeng 920 */ 730 hpre_config_pasid(qm); 731 732 hpre_enable_clock_gate(qm); 733 734 return ret; 735 } 736 737 static void hpre_cnt_regs_clear(struct hisi_qm *qm) 738 { 739 u8 clusters_num = hpre_cluster_num(qm); 740 unsigned long offset; 741 int i; 742 743 /* clear clusterX/cluster_ctrl */ 744 for (i = 0; i < clusters_num; i++) { 745 offset = HPRE_CLSTR_BASE + i * HPRE_CLSTR_ADDR_INTRVL; 746 writel(0x0, qm->io_base + offset + HPRE_CLUSTER_INQURY); 747 } 748 749 /* clear rdclr_en */ 750 writel(0x0, qm->io_base + HPRE_CTRL_CNT_CLR_CE); 751 752 hisi_qm_debug_regs_clear(qm); 753 } 754 755 static void hpre_master_ooo_ctrl(struct hisi_qm *qm, bool enable) 756 { 757 u32 val1, val2; 758 759 val1 = readl(qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB); 760 if (enable) { 761 val1 |= HPRE_AM_OOO_SHUTDOWN_ENABLE; 762 val2 = hisi_qm_get_hw_info(qm, hpre_basic_info, 763 HPRE_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 764 } else { 765 val1 &= ~HPRE_AM_OOO_SHUTDOWN_ENABLE; 766 val2 = 0x0; 767 } 768 769 if (qm->ver > QM_HW_V2) 770 writel(val2, qm->io_base + HPRE_OOO_SHUTDOWN_SEL); 771 772 writel(val1, qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB); 773 } 774 775 static void hpre_hw_error_disable(struct hisi_qm *qm) 776 { 777 u32 ce, nfe; 778 779 ce = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_CE_MASK_CAP, qm->cap_ver); 780 nfe = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_NFE_MASK_CAP, qm->cap_ver); 781 782 /* disable hpre hw error interrupts */ 783 writel(ce | nfe | HPRE_HAC_RAS_FE_ENABLE, qm->io_base + HPRE_INT_MASK); 784 /* disable HPRE block master OOO when nfe occurs on Kunpeng930 */ 785 hpre_master_ooo_ctrl(qm, false); 786 } 787 788 static void hpre_hw_error_enable(struct hisi_qm *qm) 789 { 790 u32 ce, nfe; 791 792 ce = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_CE_MASK_CAP, qm->cap_ver); 793 nfe = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_NFE_MASK_CAP, qm->cap_ver); 794 795 /* clear HPRE hw error source if having */ 796 writel(ce | nfe | HPRE_HAC_RAS_FE_ENABLE, qm->io_base + HPRE_HAC_SOURCE_INT); 797 798 /* configure error type */ 799 writel(ce, qm->io_base + HPRE_RAS_CE_ENB); 800 writel(nfe, qm->io_base + HPRE_RAS_NFE_ENB); 801 writel(HPRE_HAC_RAS_FE_ENABLE, qm->io_base + HPRE_RAS_FE_ENB); 802 803 /* enable HPRE block master OOO when nfe occurs on Kunpeng930 */ 804 hpre_master_ooo_ctrl(qm, true); 805 806 /* enable hpre hw error interrupts */ 807 writel(HPRE_CORE_INT_ENABLE, qm->io_base + HPRE_INT_MASK); 808 } 809 810 static inline struct hisi_qm *hpre_file_to_qm(struct hpre_debugfs_file *file) 811 { 812 struct hpre *hpre = container_of(file->debug, struct hpre, debug); 813 814 return &hpre->qm; 815 } 816 817 static u32 hpre_clear_enable_read(struct hpre_debugfs_file *file) 818 { 819 struct hisi_qm *qm = hpre_file_to_qm(file); 820 821 return readl(qm->io_base + HPRE_CTRL_CNT_CLR_CE) & 822 HPRE_CTRL_CNT_CLR_CE_BIT; 823 } 824 825 static int hpre_clear_enable_write(struct hpre_debugfs_file *file, u32 val) 826 { 827 struct hisi_qm *qm = hpre_file_to_qm(file); 828 u32 tmp; 829 830 if (val != 1 && val != 0) 831 return -EINVAL; 832 833 tmp = (readl(qm->io_base + HPRE_CTRL_CNT_CLR_CE) & 834 ~HPRE_CTRL_CNT_CLR_CE_BIT) | val; 835 writel(tmp, qm->io_base + HPRE_CTRL_CNT_CLR_CE); 836 837 return 0; 838 } 839 840 static u32 hpre_cluster_inqry_read(struct hpre_debugfs_file *file) 841 { 842 struct hisi_qm *qm = hpre_file_to_qm(file); 843 int cluster_index = file->index - HPRE_CLUSTER_CTRL; 844 unsigned long offset = HPRE_CLSTR_BASE + 845 cluster_index * HPRE_CLSTR_ADDR_INTRVL; 846 847 return readl(qm->io_base + offset + HPRE_CLSTR_ADDR_INQRY_RSLT); 848 } 849 850 static void hpre_cluster_inqry_write(struct hpre_debugfs_file *file, u32 val) 851 { 852 struct hisi_qm *qm = hpre_file_to_qm(file); 853 int cluster_index = file->index - HPRE_CLUSTER_CTRL; 854 unsigned long offset = HPRE_CLSTR_BASE + cluster_index * 855 HPRE_CLSTR_ADDR_INTRVL; 856 857 writel(val, qm->io_base + offset + HPRE_CLUSTER_INQURY); 858 } 859 860 static ssize_t hpre_ctrl_debug_read(struct file *filp, char __user *buf, 861 size_t count, loff_t *pos) 862 { 863 struct hpre_debugfs_file *file = filp->private_data; 864 struct hisi_qm *qm = hpre_file_to_qm(file); 865 char tbuf[HPRE_DBGFS_VAL_MAX_LEN]; 866 u32 val; 867 int ret; 868 869 ret = hisi_qm_get_dfx_access(qm); 870 if (ret) 871 return ret; 872 873 spin_lock_irq(&file->lock); 874 switch (file->type) { 875 case HPRE_CLEAR_ENABLE: 876 val = hpre_clear_enable_read(file); 877 break; 878 case HPRE_CLUSTER_CTRL: 879 val = hpre_cluster_inqry_read(file); 880 break; 881 default: 882 goto err_input; 883 } 884 spin_unlock_irq(&file->lock); 885 886 hisi_qm_put_dfx_access(qm); 887 ret = snprintf(tbuf, HPRE_DBGFS_VAL_MAX_LEN, "%u\n", val); 888 return simple_read_from_buffer(buf, count, pos, tbuf, ret); 889 890 err_input: 891 spin_unlock_irq(&file->lock); 892 hisi_qm_put_dfx_access(qm); 893 return -EINVAL; 894 } 895 896 static ssize_t hpre_ctrl_debug_write(struct file *filp, const char __user *buf, 897 size_t count, loff_t *pos) 898 { 899 struct hpre_debugfs_file *file = filp->private_data; 900 struct hisi_qm *qm = hpre_file_to_qm(file); 901 char tbuf[HPRE_DBGFS_VAL_MAX_LEN]; 902 unsigned long val; 903 int len, ret; 904 905 if (*pos != 0) 906 return 0; 907 908 if (count >= HPRE_DBGFS_VAL_MAX_LEN) 909 return -ENOSPC; 910 911 len = simple_write_to_buffer(tbuf, HPRE_DBGFS_VAL_MAX_LEN - 1, 912 pos, buf, count); 913 if (len < 0) 914 return len; 915 916 tbuf[len] = '\0'; 917 if (kstrtoul(tbuf, 0, &val)) 918 return -EFAULT; 919 920 ret = hisi_qm_get_dfx_access(qm); 921 if (ret) 922 return ret; 923 924 spin_lock_irq(&file->lock); 925 switch (file->type) { 926 case HPRE_CLEAR_ENABLE: 927 ret = hpre_clear_enable_write(file, val); 928 if (ret) 929 goto err_input; 930 break; 931 case HPRE_CLUSTER_CTRL: 932 hpre_cluster_inqry_write(file, val); 933 break; 934 default: 935 ret = -EINVAL; 936 goto err_input; 937 } 938 939 ret = count; 940 941 err_input: 942 spin_unlock_irq(&file->lock); 943 hisi_qm_put_dfx_access(qm); 944 return ret; 945 } 946 947 static const struct file_operations hpre_ctrl_debug_fops = { 948 .owner = THIS_MODULE, 949 .open = simple_open, 950 .read = hpre_ctrl_debug_read, 951 .write = hpre_ctrl_debug_write, 952 }; 953 954 static int hpre_debugfs_atomic64_get(void *data, u64 *val) 955 { 956 struct hpre_dfx *dfx_item = data; 957 958 *val = atomic64_read(&dfx_item->value); 959 960 return 0; 961 } 962 963 static int hpre_debugfs_atomic64_set(void *data, u64 val) 964 { 965 struct hpre_dfx *dfx_item = data; 966 struct hpre_dfx *hpre_dfx = NULL; 967 968 if (dfx_item->type == HPRE_OVERTIME_THRHLD) { 969 hpre_dfx = dfx_item - HPRE_OVERTIME_THRHLD; 970 atomic64_set(&hpre_dfx[HPRE_OVER_THRHLD_CNT].value, 0); 971 } else if (val) { 972 return -EINVAL; 973 } 974 975 atomic64_set(&dfx_item->value, val); 976 977 return 0; 978 } 979 980 DEFINE_DEBUGFS_ATTRIBUTE(hpre_atomic64_ops, hpre_debugfs_atomic64_get, 981 hpre_debugfs_atomic64_set, "%llu\n"); 982 983 static int hpre_create_debugfs_file(struct hisi_qm *qm, struct dentry *dir, 984 enum hpre_ctrl_dbgfs_file type, int indx) 985 { 986 struct hpre *hpre = container_of(qm, struct hpre, qm); 987 struct hpre_debug *dbg = &hpre->debug; 988 struct dentry *file_dir; 989 990 if (dir) 991 file_dir = dir; 992 else 993 file_dir = qm->debug.debug_root; 994 995 if (type >= HPRE_DEBUG_FILE_NUM) 996 return -EINVAL; 997 998 spin_lock_init(&dbg->files[indx].lock); 999 dbg->files[indx].debug = dbg; 1000 dbg->files[indx].type = type; 1001 dbg->files[indx].index = indx; 1002 debugfs_create_file(hpre_debug_file_name[type], 0600, file_dir, 1003 dbg->files + indx, &hpre_ctrl_debug_fops); 1004 1005 return 0; 1006 } 1007 1008 static int hpre_pf_comm_regs_debugfs_init(struct hisi_qm *qm) 1009 { 1010 struct device *dev = &qm->pdev->dev; 1011 struct debugfs_regset32 *regset; 1012 1013 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 1014 if (!regset) 1015 return -ENOMEM; 1016 1017 regset->regs = hpre_com_dfx_regs; 1018 regset->nregs = ARRAY_SIZE(hpre_com_dfx_regs); 1019 regset->base = qm->io_base; 1020 regset->dev = dev; 1021 1022 debugfs_create_file("regs", 0444, qm->debug.debug_root, 1023 regset, &hpre_com_regs_fops); 1024 1025 return 0; 1026 } 1027 1028 static int hpre_cluster_debugfs_init(struct hisi_qm *qm) 1029 { 1030 u8 clusters_num = hpre_cluster_num(qm); 1031 struct device *dev = &qm->pdev->dev; 1032 char buf[HPRE_DBGFS_VAL_MAX_LEN]; 1033 struct debugfs_regset32 *regset; 1034 struct dentry *tmp_d; 1035 int i, ret; 1036 1037 for (i = 0; i < clusters_num; i++) { 1038 ret = snprintf(buf, HPRE_DBGFS_VAL_MAX_LEN, "cluster%d", i); 1039 if (ret >= HPRE_DBGFS_VAL_MAX_LEN) 1040 return -EINVAL; 1041 tmp_d = debugfs_create_dir(buf, qm->debug.debug_root); 1042 1043 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 1044 if (!regset) 1045 return -ENOMEM; 1046 1047 regset->regs = hpre_cluster_dfx_regs; 1048 regset->nregs = ARRAY_SIZE(hpre_cluster_dfx_regs); 1049 regset->base = qm->io_base + hpre_cluster_offsets[i]; 1050 regset->dev = dev; 1051 1052 debugfs_create_file("regs", 0444, tmp_d, regset, 1053 &hpre_cluster_regs_fops); 1054 ret = hpre_create_debugfs_file(qm, tmp_d, HPRE_CLUSTER_CTRL, 1055 i + HPRE_CLUSTER_CTRL); 1056 if (ret) 1057 return ret; 1058 } 1059 1060 return 0; 1061 } 1062 1063 static int hpre_ctrl_debug_init(struct hisi_qm *qm) 1064 { 1065 int ret; 1066 1067 ret = hpre_create_debugfs_file(qm, NULL, HPRE_CLEAR_ENABLE, 1068 HPRE_CLEAR_ENABLE); 1069 if (ret) 1070 return ret; 1071 1072 ret = hpre_pf_comm_regs_debugfs_init(qm); 1073 if (ret) 1074 return ret; 1075 1076 return hpre_cluster_debugfs_init(qm); 1077 } 1078 1079 static void hpre_dfx_debug_init(struct hisi_qm *qm) 1080 { 1081 struct dfx_diff_registers *hpre_regs = qm->debug.acc_diff_regs; 1082 struct hpre *hpre = container_of(qm, struct hpre, qm); 1083 struct hpre_dfx *dfx = hpre->debug.dfx; 1084 struct dentry *parent; 1085 int i; 1086 1087 parent = debugfs_create_dir("hpre_dfx", qm->debug.debug_root); 1088 for (i = 0; i < HPRE_DFX_FILE_NUM; i++) { 1089 dfx[i].type = i; 1090 debugfs_create_file(hpre_dfx_files[i], 0644, parent, &dfx[i], 1091 &hpre_atomic64_ops); 1092 } 1093 1094 if (qm->fun_type == QM_HW_PF && hpre_regs) 1095 debugfs_create_file("diff_regs", 0444, parent, 1096 qm, &hpre_diff_regs_fops); 1097 } 1098 1099 static int hpre_debugfs_init(struct hisi_qm *qm) 1100 { 1101 struct device *dev = &qm->pdev->dev; 1102 int ret; 1103 1104 qm->debug.debug_root = debugfs_create_dir(dev_name(dev), 1105 hpre_debugfs_root); 1106 1107 qm->debug.sqe_mask_offset = HPRE_SQE_MASK_OFFSET; 1108 qm->debug.sqe_mask_len = HPRE_SQE_MASK_LEN; 1109 ret = hisi_qm_regs_debugfs_init(qm, hpre_diff_regs, ARRAY_SIZE(hpre_diff_regs)); 1110 if (ret) { 1111 dev_warn(dev, "Failed to init HPRE diff regs!\n"); 1112 goto debugfs_remove; 1113 } 1114 1115 hisi_qm_debug_init(qm); 1116 1117 if (qm->pdev->device == PCI_DEVICE_ID_HUAWEI_HPRE_PF) { 1118 ret = hpre_ctrl_debug_init(qm); 1119 if (ret) 1120 goto failed_to_create; 1121 } 1122 1123 hpre_dfx_debug_init(qm); 1124 1125 return 0; 1126 1127 failed_to_create: 1128 hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(hpre_diff_regs)); 1129 debugfs_remove: 1130 debugfs_remove_recursive(qm->debug.debug_root); 1131 return ret; 1132 } 1133 1134 static void hpre_debugfs_exit(struct hisi_qm *qm) 1135 { 1136 hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(hpre_diff_regs)); 1137 1138 debugfs_remove_recursive(qm->debug.debug_root); 1139 } 1140 1141 static int hpre_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) 1142 { 1143 int ret; 1144 1145 if (pdev->revision == QM_HW_V1) { 1146 pci_warn(pdev, "HPRE version 1 is not supported!\n"); 1147 return -EINVAL; 1148 } 1149 1150 qm->mode = uacce_mode; 1151 qm->pdev = pdev; 1152 qm->ver = pdev->revision; 1153 qm->sqe_size = HPRE_SQE_SIZE; 1154 qm->dev_name = hpre_name; 1155 1156 qm->fun_type = (pdev->device == PCI_DEVICE_ID_HUAWEI_HPRE_PF) ? 1157 QM_HW_PF : QM_HW_VF; 1158 if (qm->fun_type == QM_HW_PF) { 1159 qm->qp_base = HPRE_PF_DEF_Q_BASE; 1160 qm->qp_num = pf_q_num; 1161 qm->debug.curr_qm_qp_num = pf_q_num; 1162 qm->qm_list = &hpre_devices; 1163 if (pf_q_num_flag) 1164 set_bit(QM_MODULE_PARAM, &qm->misc_ctl); 1165 } 1166 1167 ret = hisi_qm_init(qm); 1168 if (ret) { 1169 pci_err(pdev, "Failed to init hpre qm configures!\n"); 1170 return ret; 1171 } 1172 1173 ret = hpre_set_qm_algs(qm); 1174 if (ret) { 1175 pci_err(pdev, "Failed to set hpre algs!\n"); 1176 hisi_qm_uninit(qm); 1177 } 1178 1179 return ret; 1180 } 1181 1182 static int hpre_show_last_regs_init(struct hisi_qm *qm) 1183 { 1184 int cluster_dfx_regs_num = ARRAY_SIZE(hpre_cluster_dfx_regs); 1185 int com_dfx_regs_num = ARRAY_SIZE(hpre_com_dfx_regs); 1186 u8 clusters_num = hpre_cluster_num(qm); 1187 struct qm_debug *debug = &qm->debug; 1188 void __iomem *io_base; 1189 int i, j, idx; 1190 1191 debug->last_words = kcalloc(cluster_dfx_regs_num * clusters_num + 1192 com_dfx_regs_num, sizeof(unsigned int), GFP_KERNEL); 1193 if (!debug->last_words) 1194 return -ENOMEM; 1195 1196 for (i = 0; i < com_dfx_regs_num; i++) 1197 debug->last_words[i] = readl_relaxed(qm->io_base + 1198 hpre_com_dfx_regs[i].offset); 1199 1200 for (i = 0; i < clusters_num; i++) { 1201 io_base = qm->io_base + hpre_cluster_offsets[i]; 1202 for (j = 0; j < cluster_dfx_regs_num; j++) { 1203 idx = com_dfx_regs_num + i * cluster_dfx_regs_num + j; 1204 debug->last_words[idx] = readl_relaxed( 1205 io_base + hpre_cluster_dfx_regs[j].offset); 1206 } 1207 } 1208 1209 return 0; 1210 } 1211 1212 static void hpre_show_last_regs_uninit(struct hisi_qm *qm) 1213 { 1214 struct qm_debug *debug = &qm->debug; 1215 1216 if (qm->fun_type == QM_HW_VF || !debug->last_words) 1217 return; 1218 1219 kfree(debug->last_words); 1220 debug->last_words = NULL; 1221 } 1222 1223 static void hpre_show_last_dfx_regs(struct hisi_qm *qm) 1224 { 1225 int cluster_dfx_regs_num = ARRAY_SIZE(hpre_cluster_dfx_regs); 1226 int com_dfx_regs_num = ARRAY_SIZE(hpre_com_dfx_regs); 1227 u8 clusters_num = hpre_cluster_num(qm); 1228 struct qm_debug *debug = &qm->debug; 1229 struct pci_dev *pdev = qm->pdev; 1230 void __iomem *io_base; 1231 int i, j, idx; 1232 u32 val; 1233 1234 if (qm->fun_type == QM_HW_VF || !debug->last_words) 1235 return; 1236 1237 /* dumps last word of the debugging registers during controller reset */ 1238 for (i = 0; i < com_dfx_regs_num; i++) { 1239 val = readl_relaxed(qm->io_base + hpre_com_dfx_regs[i].offset); 1240 if (debug->last_words[i] != val) 1241 pci_info(pdev, "Common_core:%s \t= 0x%08x => 0x%08x\n", 1242 hpre_com_dfx_regs[i].name, debug->last_words[i], val); 1243 } 1244 1245 for (i = 0; i < clusters_num; i++) { 1246 io_base = qm->io_base + hpre_cluster_offsets[i]; 1247 for (j = 0; j < cluster_dfx_regs_num; j++) { 1248 val = readl_relaxed(io_base + 1249 hpre_cluster_dfx_regs[j].offset); 1250 idx = com_dfx_regs_num + i * cluster_dfx_regs_num + j; 1251 if (debug->last_words[idx] != val) 1252 pci_info(pdev, "cluster-%d:%s \t= 0x%08x => 0x%08x\n", 1253 i, hpre_cluster_dfx_regs[j].name, debug->last_words[idx], val); 1254 } 1255 } 1256 } 1257 1258 static void hpre_log_hw_error(struct hisi_qm *qm, u32 err_sts) 1259 { 1260 const struct hpre_hw_error *err = hpre_hw_errors; 1261 struct device *dev = &qm->pdev->dev; 1262 1263 while (err->msg) { 1264 if (err->int_msk & err_sts) 1265 dev_warn(dev, "%s [error status=0x%x] found\n", 1266 err->msg, err->int_msk); 1267 err++; 1268 } 1269 } 1270 1271 static u32 hpre_get_hw_err_status(struct hisi_qm *qm) 1272 { 1273 return readl(qm->io_base + HPRE_INT_STATUS); 1274 } 1275 1276 static void hpre_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts) 1277 { 1278 u32 nfe; 1279 1280 writel(err_sts, qm->io_base + HPRE_HAC_SOURCE_INT); 1281 nfe = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_NFE_MASK_CAP, qm->cap_ver); 1282 writel(nfe, qm->io_base + HPRE_RAS_NFE_ENB); 1283 } 1284 1285 static void hpre_open_axi_master_ooo(struct hisi_qm *qm) 1286 { 1287 u32 value; 1288 1289 value = readl(qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB); 1290 writel(value & ~HPRE_AM_OOO_SHUTDOWN_ENABLE, 1291 qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB); 1292 writel(value | HPRE_AM_OOO_SHUTDOWN_ENABLE, 1293 qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB); 1294 } 1295 1296 static void hpre_err_info_init(struct hisi_qm *qm) 1297 { 1298 struct hisi_qm_err_info *err_info = &qm->err_info; 1299 1300 err_info->fe = HPRE_HAC_RAS_FE_ENABLE; 1301 err_info->ce = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_QM_CE_MASK_CAP, qm->cap_ver); 1302 err_info->nfe = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_QM_NFE_MASK_CAP, qm->cap_ver); 1303 err_info->ecc_2bits_mask = HPRE_CORE_ECC_2BIT_ERR | HPRE_OOO_ECC_2BIT_ERR; 1304 err_info->dev_shutdown_mask = hisi_qm_get_hw_info(qm, hpre_basic_info, 1305 HPRE_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 1306 err_info->qm_shutdown_mask = hisi_qm_get_hw_info(qm, hpre_basic_info, 1307 HPRE_QM_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 1308 err_info->qm_reset_mask = hisi_qm_get_hw_info(qm, hpre_basic_info, 1309 HPRE_QM_RESET_MASK_CAP, qm->cap_ver); 1310 err_info->dev_reset_mask = hisi_qm_get_hw_info(qm, hpre_basic_info, 1311 HPRE_RESET_MASK_CAP, qm->cap_ver); 1312 err_info->msi_wr_port = HPRE_WR_MSI_PORT; 1313 err_info->acpi_rst = "HRST"; 1314 } 1315 1316 static const struct hisi_qm_err_ini hpre_err_ini = { 1317 .hw_init = hpre_set_user_domain_and_cache, 1318 .hw_err_enable = hpre_hw_error_enable, 1319 .hw_err_disable = hpre_hw_error_disable, 1320 .get_dev_hw_err_status = hpre_get_hw_err_status, 1321 .clear_dev_hw_err_status = hpre_clear_hw_err_status, 1322 .log_dev_hw_err = hpre_log_hw_error, 1323 .open_axi_master_ooo = hpre_open_axi_master_ooo, 1324 .open_sva_prefetch = hpre_open_sva_prefetch, 1325 .close_sva_prefetch = hpre_close_sva_prefetch, 1326 .show_last_dfx_regs = hpre_show_last_dfx_regs, 1327 .err_info_init = hpre_err_info_init, 1328 }; 1329 1330 static int hpre_pf_probe_init(struct hpre *hpre) 1331 { 1332 struct hisi_qm *qm = &hpre->qm; 1333 int ret; 1334 1335 ret = hpre_set_user_domain_and_cache(qm); 1336 if (ret) 1337 return ret; 1338 1339 hpre_open_sva_prefetch(qm); 1340 1341 qm->err_ini = &hpre_err_ini; 1342 qm->err_ini->err_info_init(qm); 1343 hisi_qm_dev_err_init(qm); 1344 ret = hpre_show_last_regs_init(qm); 1345 if (ret) 1346 pci_err(qm->pdev, "Failed to init last word regs!\n"); 1347 1348 return ret; 1349 } 1350 1351 static int hpre_probe_init(struct hpre *hpre) 1352 { 1353 u32 type_rate = HPRE_SHAPER_TYPE_RATE; 1354 struct hisi_qm *qm = &hpre->qm; 1355 int ret; 1356 1357 if (qm->fun_type == QM_HW_PF) { 1358 ret = hpre_pf_probe_init(hpre); 1359 if (ret) 1360 return ret; 1361 /* Enable shaper type 0 */ 1362 if (qm->ver >= QM_HW_V3) { 1363 type_rate |= QM_SHAPER_ENABLE; 1364 qm->type_rate = type_rate; 1365 } 1366 } 1367 1368 return 0; 1369 } 1370 1371 static int hpre_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1372 { 1373 struct hisi_qm *qm; 1374 struct hpre *hpre; 1375 int ret; 1376 1377 hpre = devm_kzalloc(&pdev->dev, sizeof(*hpre), GFP_KERNEL); 1378 if (!hpre) 1379 return -ENOMEM; 1380 1381 qm = &hpre->qm; 1382 ret = hpre_qm_init(qm, pdev); 1383 if (ret) { 1384 pci_err(pdev, "Failed to init HPRE QM (%d)!\n", ret); 1385 return ret; 1386 } 1387 1388 ret = hpre_probe_init(hpre); 1389 if (ret) { 1390 pci_err(pdev, "Failed to probe (%d)!\n", ret); 1391 goto err_with_qm_init; 1392 } 1393 1394 ret = hisi_qm_start(qm); 1395 if (ret) 1396 goto err_with_err_init; 1397 1398 ret = hpre_debugfs_init(qm); 1399 if (ret) 1400 dev_warn(&pdev->dev, "init debugfs fail!\n"); 1401 1402 ret = hisi_qm_alg_register(qm, &hpre_devices); 1403 if (ret < 0) { 1404 pci_err(pdev, "fail to register algs to crypto!\n"); 1405 goto err_with_qm_start; 1406 } 1407 1408 if (qm->uacce) { 1409 ret = uacce_register(qm->uacce); 1410 if (ret) { 1411 pci_err(pdev, "failed to register uacce (%d)!\n", ret); 1412 goto err_with_alg_register; 1413 } 1414 } 1415 1416 if (qm->fun_type == QM_HW_PF && vfs_num) { 1417 ret = hisi_qm_sriov_enable(pdev, vfs_num); 1418 if (ret < 0) 1419 goto err_with_alg_register; 1420 } 1421 1422 hisi_qm_pm_init(qm); 1423 1424 return 0; 1425 1426 err_with_alg_register: 1427 hisi_qm_alg_unregister(qm, &hpre_devices); 1428 1429 err_with_qm_start: 1430 hpre_debugfs_exit(qm); 1431 hisi_qm_stop(qm, QM_NORMAL); 1432 1433 err_with_err_init: 1434 hpre_show_last_regs_uninit(qm); 1435 hisi_qm_dev_err_uninit(qm); 1436 1437 err_with_qm_init: 1438 hisi_qm_uninit(qm); 1439 1440 return ret; 1441 } 1442 1443 static void hpre_remove(struct pci_dev *pdev) 1444 { 1445 struct hisi_qm *qm = pci_get_drvdata(pdev); 1446 1447 hisi_qm_pm_uninit(qm); 1448 hisi_qm_wait_task_finish(qm, &hpre_devices); 1449 hisi_qm_alg_unregister(qm, &hpre_devices); 1450 if (qm->fun_type == QM_HW_PF && qm->vfs_num) 1451 hisi_qm_sriov_disable(pdev, true); 1452 1453 hpre_debugfs_exit(qm); 1454 hisi_qm_stop(qm, QM_NORMAL); 1455 1456 if (qm->fun_type == QM_HW_PF) { 1457 hpre_cnt_regs_clear(qm); 1458 qm->debug.curr_qm_qp_num = 0; 1459 hpre_show_last_regs_uninit(qm); 1460 hisi_qm_dev_err_uninit(qm); 1461 } 1462 1463 hisi_qm_uninit(qm); 1464 } 1465 1466 static const struct dev_pm_ops hpre_pm_ops = { 1467 SET_RUNTIME_PM_OPS(hisi_qm_suspend, hisi_qm_resume, NULL) 1468 }; 1469 1470 static const struct pci_error_handlers hpre_err_handler = { 1471 .error_detected = hisi_qm_dev_err_detected, 1472 .slot_reset = hisi_qm_dev_slot_reset, 1473 .reset_prepare = hisi_qm_reset_prepare, 1474 .reset_done = hisi_qm_reset_done, 1475 }; 1476 1477 static struct pci_driver hpre_pci_driver = { 1478 .name = hpre_name, 1479 .id_table = hpre_dev_ids, 1480 .probe = hpre_probe, 1481 .remove = hpre_remove, 1482 .sriov_configure = IS_ENABLED(CONFIG_PCI_IOV) ? 1483 hisi_qm_sriov_configure : NULL, 1484 .err_handler = &hpre_err_handler, 1485 .shutdown = hisi_qm_dev_shutdown, 1486 .driver.pm = &hpre_pm_ops, 1487 }; 1488 1489 struct pci_driver *hisi_hpre_get_pf_driver(void) 1490 { 1491 return &hpre_pci_driver; 1492 } 1493 EXPORT_SYMBOL_GPL(hisi_hpre_get_pf_driver); 1494 1495 static void hpre_register_debugfs(void) 1496 { 1497 if (!debugfs_initialized()) 1498 return; 1499 1500 hpre_debugfs_root = debugfs_create_dir(hpre_name, NULL); 1501 } 1502 1503 static void hpre_unregister_debugfs(void) 1504 { 1505 debugfs_remove_recursive(hpre_debugfs_root); 1506 } 1507 1508 static int __init hpre_init(void) 1509 { 1510 int ret; 1511 1512 hisi_qm_init_list(&hpre_devices); 1513 hpre_register_debugfs(); 1514 1515 ret = pci_register_driver(&hpre_pci_driver); 1516 if (ret) { 1517 hpre_unregister_debugfs(); 1518 pr_err("hpre: can't register hisi hpre driver.\n"); 1519 } 1520 1521 return ret; 1522 } 1523 1524 static void __exit hpre_exit(void) 1525 { 1526 pci_unregister_driver(&hpre_pci_driver); 1527 hpre_unregister_debugfs(); 1528 } 1529 1530 module_init(hpre_init); 1531 module_exit(hpre_exit); 1532 1533 MODULE_LICENSE("GPL v2"); 1534 MODULE_AUTHOR("Zaibo Xu <xuzaibo@huawei.com>"); 1535 MODULE_AUTHOR("Meng Yu <yumeng18@huawei.com>"); 1536 MODULE_DESCRIPTION("Driver for HiSilicon HPRE accelerator"); 1537