1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018-2019 HiSilicon Limited. */ 3 #include <linux/acpi.h> 4 #include <linux/aer.h> 5 #include <linux/bitops.h> 6 #include <linux/debugfs.h> 7 #include <linux/init.h> 8 #include <linux/io.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/topology.h> 13 #include <linux/uacce.h> 14 #include "hpre.h" 15 16 #define HPRE_QUEUE_NUM_V2 1024 17 #define HPRE_QM_ABNML_INT_MASK 0x100004 18 #define HPRE_CTRL_CNT_CLR_CE_BIT BIT(0) 19 #define HPRE_COMM_CNT_CLR_CE 0x0 20 #define HPRE_CTRL_CNT_CLR_CE 0x301000 21 #define HPRE_FSM_MAX_CNT 0x301008 22 #define HPRE_VFG_AXQOS 0x30100c 23 #define HPRE_VFG_AXCACHE 0x301010 24 #define HPRE_RDCHN_INI_CFG 0x301014 25 #define HPRE_AWUSR_FP_CFG 0x301018 26 #define HPRE_BD_ENDIAN 0x301020 27 #define HPRE_ECC_BYPASS 0x301024 28 #define HPRE_RAS_WIDTH_CFG 0x301028 29 #define HPRE_POISON_BYPASS 0x30102c 30 #define HPRE_BD_ARUSR_CFG 0x301030 31 #define HPRE_BD_AWUSR_CFG 0x301034 32 #define HPRE_TYPES_ENB 0x301038 33 #define HPRE_RSA_ENB BIT(0) 34 #define HPRE_ECC_ENB BIT(1) 35 #define HPRE_DATA_RUSER_CFG 0x30103c 36 #define HPRE_DATA_WUSER_CFG 0x301040 37 #define HPRE_INT_MASK 0x301400 38 #define HPRE_INT_STATUS 0x301800 39 #define HPRE_CORE_INT_ENABLE 0 40 #define HPRE_CORE_INT_DISABLE 0x003fffff 41 #define HPRE_RDCHN_INI_ST 0x301a00 42 #define HPRE_CLSTR_BASE 0x302000 43 #define HPRE_CORE_EN_OFFSET 0x04 44 #define HPRE_CORE_INI_CFG_OFFSET 0x20 45 #define HPRE_CORE_INI_STATUS_OFFSET 0x80 46 #define HPRE_CORE_HTBT_WARN_OFFSET 0x8c 47 #define HPRE_CORE_IS_SCHD_OFFSET 0x90 48 49 #define HPRE_RAS_CE_ENB 0x301410 50 #define HPRE_HAC_RAS_CE_ENABLE (BIT(0) | BIT(22) | BIT(23)) 51 #define HPRE_RAS_NFE_ENB 0x301414 52 #define HPRE_HAC_RAS_NFE_ENABLE 0x3ffffe 53 #define HPRE_RAS_FE_ENB 0x301418 54 #define HPRE_HAC_RAS_FE_ENABLE 0 55 56 #define HPRE_CORE_ENB (HPRE_CLSTR_BASE + HPRE_CORE_EN_OFFSET) 57 #define HPRE_CORE_INI_CFG (HPRE_CLSTR_BASE + HPRE_CORE_INI_CFG_OFFSET) 58 #define HPRE_CORE_INI_STATUS (HPRE_CLSTR_BASE + HPRE_CORE_INI_STATUS_OFFSET) 59 #define HPRE_HAC_ECC1_CNT 0x301a04 60 #define HPRE_HAC_ECC2_CNT 0x301a08 61 #define HPRE_HAC_INT_STATUS 0x301800 62 #define HPRE_HAC_SOURCE_INT 0x301600 63 #define HPRE_CLSTR_ADDR_INTRVL 0x1000 64 #define HPRE_CLUSTER_INQURY 0x100 65 #define HPRE_CLSTR_ADDR_INQRY_RSLT 0x104 66 #define HPRE_TIMEOUT_ABNML_BIT 6 67 #define HPRE_PASID_EN_BIT 9 68 #define HPRE_REG_RD_INTVRL_US 10 69 #define HPRE_REG_RD_TMOUT_US 1000 70 #define HPRE_DBGFS_VAL_MAX_LEN 20 71 #define HPRE_PCI_DEVICE_ID 0xa258 72 #define HPRE_PCI_VF_DEVICE_ID 0xa259 73 #define HPRE_ADDR(qm, offset) ((qm)->io_base + (offset)) 74 #define HPRE_QM_USR_CFG_MASK 0xfffffffe 75 #define HPRE_QM_AXI_CFG_MASK 0xffff 76 #define HPRE_QM_VFG_AX_MASK 0xff 77 #define HPRE_BD_USR_MASK 0x3 78 #define HPRE_CLUSTER_CORE_MASK_V2 0xf 79 #define HPRE_CLUSTER_CORE_MASK_V3 0xff 80 81 #define HPRE_AM_OOO_SHUTDOWN_ENB 0x301044 82 #define HPRE_AM_OOO_SHUTDOWN_ENABLE BIT(0) 83 #define HPRE_WR_MSI_PORT BIT(2) 84 85 #define HPRE_CORE_ECC_2BIT_ERR BIT(1) 86 #define HPRE_OOO_ECC_2BIT_ERR BIT(5) 87 88 #define HPRE_QM_BME_FLR BIT(7) 89 #define HPRE_QM_PM_FLR BIT(11) 90 #define HPRE_QM_SRIOV_FLR BIT(12) 91 92 #define HPRE_CLUSTERS_NUM(qm) \ 93 (((qm)->ver >= QM_HW_V3) ? HPRE_CLUSTERS_NUM_V3 : HPRE_CLUSTERS_NUM_V2) 94 #define HPRE_CLUSTER_CORE_MASK(qm) \ 95 (((qm)->ver >= QM_HW_V3) ? HPRE_CLUSTER_CORE_MASK_V3 :\ 96 HPRE_CLUSTER_CORE_MASK_V2) 97 #define HPRE_VIA_MSI_DSM 1 98 #define HPRE_SQE_MASK_OFFSET 8 99 #define HPRE_SQE_MASK_LEN 24 100 101 static const char hpre_name[] = "hisi_hpre"; 102 static struct dentry *hpre_debugfs_root; 103 static const struct pci_device_id hpre_dev_ids[] = { 104 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HPRE_PCI_DEVICE_ID) }, 105 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HPRE_PCI_VF_DEVICE_ID) }, 106 { 0, } 107 }; 108 109 MODULE_DEVICE_TABLE(pci, hpre_dev_ids); 110 111 struct hpre_hw_error { 112 u32 int_msk; 113 const char *msg; 114 }; 115 116 static struct hisi_qm_list hpre_devices = { 117 .register_to_crypto = hpre_algs_register, 118 .unregister_from_crypto = hpre_algs_unregister, 119 }; 120 121 static const char * const hpre_debug_file_name[] = { 122 [HPRE_CURRENT_QM] = "current_qm", 123 [HPRE_CLEAR_ENABLE] = "rdclr_en", 124 [HPRE_CLUSTER_CTRL] = "cluster_ctrl", 125 }; 126 127 static const struct hpre_hw_error hpre_hw_errors[] = { 128 { .int_msk = BIT(0), .msg = "core_ecc_1bit_err_int_set" }, 129 { .int_msk = BIT(1), .msg = "core_ecc_2bit_err_int_set" }, 130 { .int_msk = BIT(2), .msg = "dat_wb_poison_int_set" }, 131 { .int_msk = BIT(3), .msg = "dat_rd_poison_int_set" }, 132 { .int_msk = BIT(4), .msg = "bd_rd_poison_int_set" }, 133 { .int_msk = BIT(5), .msg = "ooo_ecc_2bit_err_int_set" }, 134 { .int_msk = BIT(6), .msg = "cluster1_shb_timeout_int_set" }, 135 { .int_msk = BIT(7), .msg = "cluster2_shb_timeout_int_set" }, 136 { .int_msk = BIT(8), .msg = "cluster3_shb_timeout_int_set" }, 137 { .int_msk = BIT(9), .msg = "cluster4_shb_timeout_int_set" }, 138 { .int_msk = GENMASK(15, 10), .msg = "ooo_rdrsp_err_int_set" }, 139 { .int_msk = GENMASK(21, 16), .msg = "ooo_wrrsp_err_int_set" }, 140 { .int_msk = BIT(22), .msg = "pt_rng_timeout_int_set"}, 141 { .int_msk = BIT(23), .msg = "sva_fsm_timeout_int_set"}, 142 { 143 /* sentinel */ 144 } 145 }; 146 147 static const u64 hpre_cluster_offsets[] = { 148 [HPRE_CLUSTER0] = 149 HPRE_CLSTR_BASE + HPRE_CLUSTER0 * HPRE_CLSTR_ADDR_INTRVL, 150 [HPRE_CLUSTER1] = 151 HPRE_CLSTR_BASE + HPRE_CLUSTER1 * HPRE_CLSTR_ADDR_INTRVL, 152 [HPRE_CLUSTER2] = 153 HPRE_CLSTR_BASE + HPRE_CLUSTER2 * HPRE_CLSTR_ADDR_INTRVL, 154 [HPRE_CLUSTER3] = 155 HPRE_CLSTR_BASE + HPRE_CLUSTER3 * HPRE_CLSTR_ADDR_INTRVL, 156 }; 157 158 static const struct debugfs_reg32 hpre_cluster_dfx_regs[] = { 159 {"CORES_EN_STATUS ", HPRE_CORE_EN_OFFSET}, 160 {"CORES_INI_CFG ", HPRE_CORE_INI_CFG_OFFSET}, 161 {"CORES_INI_STATUS ", HPRE_CORE_INI_STATUS_OFFSET}, 162 {"CORES_HTBT_WARN ", HPRE_CORE_HTBT_WARN_OFFSET}, 163 {"CORES_IS_SCHD ", HPRE_CORE_IS_SCHD_OFFSET}, 164 }; 165 166 static const struct debugfs_reg32 hpre_com_dfx_regs[] = { 167 {"READ_CLR_EN ", HPRE_CTRL_CNT_CLR_CE}, 168 {"AXQOS ", HPRE_VFG_AXQOS}, 169 {"AWUSR_CFG ", HPRE_AWUSR_FP_CFG}, 170 {"QM_ARUSR_MCFG1 ", QM_ARUSER_M_CFG_1}, 171 {"QM_AWUSR_MCFG1 ", QM_AWUSER_M_CFG_1}, 172 {"BD_ENDIAN ", HPRE_BD_ENDIAN}, 173 {"ECC_CHECK_CTRL ", HPRE_ECC_BYPASS}, 174 {"RAS_INT_WIDTH ", HPRE_RAS_WIDTH_CFG}, 175 {"POISON_BYPASS ", HPRE_POISON_BYPASS}, 176 {"BD_ARUSER ", HPRE_BD_ARUSR_CFG}, 177 {"BD_AWUSER ", HPRE_BD_AWUSR_CFG}, 178 {"DATA_ARUSER ", HPRE_DATA_RUSER_CFG}, 179 {"DATA_AWUSER ", HPRE_DATA_WUSER_CFG}, 180 {"INT_STATUS ", HPRE_INT_STATUS}, 181 }; 182 183 static const char *hpre_dfx_files[HPRE_DFX_FILE_NUM] = { 184 "send_cnt", 185 "recv_cnt", 186 "send_fail_cnt", 187 "send_busy_cnt", 188 "over_thrhld_cnt", 189 "overtime_thrhld", 190 "invalid_req_cnt" 191 }; 192 193 static const struct kernel_param_ops hpre_uacce_mode_ops = { 194 .set = uacce_mode_set, 195 .get = param_get_int, 196 }; 197 198 /* 199 * uacce_mode = 0 means hpre only register to crypto, 200 * uacce_mode = 1 means hpre both register to crypto and uacce. 201 */ 202 static u32 uacce_mode = UACCE_MODE_NOUACCE; 203 module_param_cb(uacce_mode, &hpre_uacce_mode_ops, &uacce_mode, 0444); 204 MODULE_PARM_DESC(uacce_mode, UACCE_MODE_DESC); 205 206 static int pf_q_num_set(const char *val, const struct kernel_param *kp) 207 { 208 return q_num_set(val, kp, HPRE_PCI_DEVICE_ID); 209 } 210 211 static const struct kernel_param_ops hpre_pf_q_num_ops = { 212 .set = pf_q_num_set, 213 .get = param_get_int, 214 }; 215 216 static u32 pf_q_num = HPRE_PF_DEF_Q_NUM; 217 module_param_cb(pf_q_num, &hpre_pf_q_num_ops, &pf_q_num, 0444); 218 MODULE_PARM_DESC(pf_q_num, "Number of queues in PF of CS(2-1024)"); 219 220 static const struct kernel_param_ops vfs_num_ops = { 221 .set = vfs_num_set, 222 .get = param_get_int, 223 }; 224 225 static u32 vfs_num; 226 module_param_cb(vfs_num, &vfs_num_ops, &vfs_num, 0444); 227 MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)"); 228 229 struct hisi_qp *hpre_create_qp(void) 230 { 231 int node = cpu_to_node(smp_processor_id()); 232 struct hisi_qp *qp = NULL; 233 int ret; 234 235 ret = hisi_qm_alloc_qps_node(&hpre_devices, 1, 0, node, &qp); 236 if (!ret) 237 return qp; 238 239 return NULL; 240 } 241 242 static void hpre_pasid_enable(struct hisi_qm *qm) 243 { 244 u32 val; 245 246 val = readl_relaxed(qm->io_base + HPRE_DATA_RUSER_CFG); 247 val |= BIT(HPRE_PASID_EN_BIT); 248 writel_relaxed(val, qm->io_base + HPRE_DATA_RUSER_CFG); 249 val = readl_relaxed(qm->io_base + HPRE_DATA_WUSER_CFG); 250 val |= BIT(HPRE_PASID_EN_BIT); 251 writel_relaxed(val, qm->io_base + HPRE_DATA_WUSER_CFG); 252 } 253 254 static void hpre_pasid_disable(struct hisi_qm *qm) 255 { 256 u32 val; 257 258 val = readl_relaxed(qm->io_base + HPRE_DATA_RUSER_CFG); 259 val &= ~BIT(HPRE_PASID_EN_BIT); 260 writel_relaxed(val, qm->io_base + HPRE_DATA_RUSER_CFG); 261 val = readl_relaxed(qm->io_base + HPRE_DATA_WUSER_CFG); 262 val &= ~BIT(HPRE_PASID_EN_BIT); 263 writel_relaxed(val, qm->io_base + HPRE_DATA_WUSER_CFG); 264 } 265 266 static int hpre_cfg_by_dsm(struct hisi_qm *qm) 267 { 268 struct device *dev = &qm->pdev->dev; 269 union acpi_object *obj; 270 guid_t guid; 271 272 if (guid_parse("b06b81ab-0134-4a45-9b0c-483447b95fa7", &guid)) { 273 dev_err(dev, "Hpre GUID failed\n"); 274 return -EINVAL; 275 } 276 277 /* Switch over to MSI handling due to non-standard PCI implementation */ 278 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &guid, 279 0, HPRE_VIA_MSI_DSM, NULL); 280 if (!obj) { 281 dev_err(dev, "ACPI handle failed!\n"); 282 return -EIO; 283 } 284 285 ACPI_FREE(obj); 286 287 return 0; 288 } 289 290 static int hpre_set_cluster(struct hisi_qm *qm) 291 { 292 u32 cluster_core_mask = HPRE_CLUSTER_CORE_MASK(qm); 293 u8 clusters_num = HPRE_CLUSTERS_NUM(qm); 294 struct device *dev = &qm->pdev->dev; 295 unsigned long offset; 296 u32 val = 0; 297 int ret, i; 298 299 for (i = 0; i < clusters_num; i++) { 300 offset = i * HPRE_CLSTR_ADDR_INTRVL; 301 302 /* clusters initiating */ 303 writel(cluster_core_mask, 304 HPRE_ADDR(qm, offset + HPRE_CORE_ENB)); 305 writel(0x1, HPRE_ADDR(qm, offset + HPRE_CORE_INI_CFG)); 306 ret = readl_relaxed_poll_timeout(HPRE_ADDR(qm, offset + 307 HPRE_CORE_INI_STATUS), val, 308 ((val & cluster_core_mask) == 309 cluster_core_mask), 310 HPRE_REG_RD_INTVRL_US, 311 HPRE_REG_RD_TMOUT_US); 312 if (ret) { 313 dev_err(dev, 314 "cluster %d int st status timeout!\n", i); 315 return -ETIMEDOUT; 316 } 317 } 318 319 return 0; 320 } 321 322 /* 323 * For Kunpeng 920, we shoul disable FLR triggered by hardware (BME/PM/SRIOV). 324 * Or it may stay in D3 state when we bind and unbind hpre quickly, 325 * as it does FLR triggered by hardware. 326 */ 327 static void disable_flr_of_bme(struct hisi_qm *qm) 328 { 329 u32 val; 330 331 val = readl(HPRE_ADDR(qm, QM_PEH_AXUSER_CFG)); 332 val &= ~(HPRE_QM_BME_FLR | HPRE_QM_SRIOV_FLR); 333 val |= HPRE_QM_PM_FLR; 334 writel(val, HPRE_ADDR(qm, QM_PEH_AXUSER_CFG)); 335 writel(PEH_AXUSER_CFG_ENABLE, HPRE_ADDR(qm, QM_PEH_AXUSER_CFG_ENABLE)); 336 } 337 338 static int hpre_set_user_domain_and_cache(struct hisi_qm *qm) 339 { 340 struct device *dev = &qm->pdev->dev; 341 u32 val; 342 int ret; 343 344 writel(HPRE_QM_USR_CFG_MASK, HPRE_ADDR(qm, QM_ARUSER_M_CFG_ENABLE)); 345 writel(HPRE_QM_USR_CFG_MASK, HPRE_ADDR(qm, QM_AWUSER_M_CFG_ENABLE)); 346 writel_relaxed(HPRE_QM_AXI_CFG_MASK, HPRE_ADDR(qm, QM_AXI_M_CFG)); 347 348 /* HPRE need more time, we close this interrupt */ 349 val = readl_relaxed(HPRE_ADDR(qm, HPRE_QM_ABNML_INT_MASK)); 350 val |= BIT(HPRE_TIMEOUT_ABNML_BIT); 351 writel_relaxed(val, HPRE_ADDR(qm, HPRE_QM_ABNML_INT_MASK)); 352 353 if (qm->ver >= QM_HW_V3) 354 writel(HPRE_RSA_ENB | HPRE_ECC_ENB, 355 HPRE_ADDR(qm, HPRE_TYPES_ENB)); 356 else 357 writel(HPRE_RSA_ENB, HPRE_ADDR(qm, HPRE_TYPES_ENB)); 358 359 writel(HPRE_QM_VFG_AX_MASK, HPRE_ADDR(qm, HPRE_VFG_AXCACHE)); 360 writel(0x0, HPRE_ADDR(qm, HPRE_BD_ENDIAN)); 361 writel(0x0, HPRE_ADDR(qm, HPRE_INT_MASK)); 362 writel(0x0, HPRE_ADDR(qm, HPRE_POISON_BYPASS)); 363 writel(0x0, HPRE_ADDR(qm, HPRE_COMM_CNT_CLR_CE)); 364 writel(0x0, HPRE_ADDR(qm, HPRE_ECC_BYPASS)); 365 366 writel(HPRE_BD_USR_MASK, HPRE_ADDR(qm, HPRE_BD_ARUSR_CFG)); 367 writel(HPRE_BD_USR_MASK, HPRE_ADDR(qm, HPRE_BD_AWUSR_CFG)); 368 writel(0x1, HPRE_ADDR(qm, HPRE_RDCHN_INI_CFG)); 369 ret = readl_relaxed_poll_timeout(HPRE_ADDR(qm, HPRE_RDCHN_INI_ST), val, 370 val & BIT(0), 371 HPRE_REG_RD_INTVRL_US, 372 HPRE_REG_RD_TMOUT_US); 373 if (ret) { 374 dev_err(dev, "read rd channel timeout fail!\n"); 375 return -ETIMEDOUT; 376 } 377 378 ret = hpre_set_cluster(qm); 379 if (ret) 380 return -ETIMEDOUT; 381 382 /* This setting is only needed by Kunpeng 920. */ 383 if (qm->ver == QM_HW_V2) { 384 ret = hpre_cfg_by_dsm(qm); 385 if (ret) 386 dev_err(dev, "acpi_evaluate_dsm err.\n"); 387 388 disable_flr_of_bme(qm); 389 390 /* Enable data buffer pasid */ 391 if (qm->use_sva) 392 hpre_pasid_enable(qm); 393 } 394 395 return ret; 396 } 397 398 static void hpre_cnt_regs_clear(struct hisi_qm *qm) 399 { 400 u8 clusters_num = HPRE_CLUSTERS_NUM(qm); 401 unsigned long offset; 402 int i; 403 404 /* clear current_qm */ 405 writel(0x0, qm->io_base + QM_DFX_MB_CNT_VF); 406 writel(0x0, qm->io_base + QM_DFX_DB_CNT_VF); 407 408 /* clear clusterX/cluster_ctrl */ 409 for (i = 0; i < clusters_num; i++) { 410 offset = HPRE_CLSTR_BASE + i * HPRE_CLSTR_ADDR_INTRVL; 411 writel(0x0, qm->io_base + offset + HPRE_CLUSTER_INQURY); 412 } 413 414 /* clear rdclr_en */ 415 writel(0x0, qm->io_base + HPRE_CTRL_CNT_CLR_CE); 416 417 hisi_qm_debug_regs_clear(qm); 418 } 419 420 static void hpre_hw_error_disable(struct hisi_qm *qm) 421 { 422 u32 val; 423 424 /* disable hpre hw error interrupts */ 425 writel(HPRE_CORE_INT_DISABLE, qm->io_base + HPRE_INT_MASK); 426 427 /* disable HPRE block master OOO when m-bit error occur */ 428 val = readl(qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB); 429 val &= ~HPRE_AM_OOO_SHUTDOWN_ENABLE; 430 writel(val, qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB); 431 } 432 433 static void hpre_hw_error_enable(struct hisi_qm *qm) 434 { 435 u32 val; 436 437 /* clear HPRE hw error source if having */ 438 writel(HPRE_CORE_INT_DISABLE, qm->io_base + HPRE_HAC_SOURCE_INT); 439 440 /* enable hpre hw error interrupts */ 441 writel(HPRE_CORE_INT_ENABLE, qm->io_base + HPRE_INT_MASK); 442 writel(HPRE_HAC_RAS_CE_ENABLE, qm->io_base + HPRE_RAS_CE_ENB); 443 writel(HPRE_HAC_RAS_NFE_ENABLE, qm->io_base + HPRE_RAS_NFE_ENB); 444 writel(HPRE_HAC_RAS_FE_ENABLE, qm->io_base + HPRE_RAS_FE_ENB); 445 446 /* enable HPRE block master OOO when m-bit error occur */ 447 val = readl(qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB); 448 val |= HPRE_AM_OOO_SHUTDOWN_ENABLE; 449 writel(val, qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB); 450 } 451 452 static inline struct hisi_qm *hpre_file_to_qm(struct hpre_debugfs_file *file) 453 { 454 struct hpre *hpre = container_of(file->debug, struct hpre, debug); 455 456 return &hpre->qm; 457 } 458 459 static u32 hpre_current_qm_read(struct hpre_debugfs_file *file) 460 { 461 struct hisi_qm *qm = hpre_file_to_qm(file); 462 463 return readl(qm->io_base + QM_DFX_MB_CNT_VF); 464 } 465 466 static int hpre_current_qm_write(struct hpre_debugfs_file *file, u32 val) 467 { 468 struct hisi_qm *qm = hpre_file_to_qm(file); 469 u32 num_vfs = qm->vfs_num; 470 u32 vfq_num, tmp; 471 472 if (val > num_vfs) 473 return -EINVAL; 474 475 /* According PF or VF Dev ID to calculation curr_qm_qp_num and store */ 476 if (val == 0) { 477 qm->debug.curr_qm_qp_num = qm->qp_num; 478 } else { 479 vfq_num = (qm->ctrl_qp_num - qm->qp_num) / num_vfs; 480 if (val == num_vfs) { 481 qm->debug.curr_qm_qp_num = 482 qm->ctrl_qp_num - qm->qp_num - (num_vfs - 1) * vfq_num; 483 } else { 484 qm->debug.curr_qm_qp_num = vfq_num; 485 } 486 } 487 488 writel(val, qm->io_base + QM_DFX_MB_CNT_VF); 489 writel(val, qm->io_base + QM_DFX_DB_CNT_VF); 490 491 tmp = val | 492 (readl(qm->io_base + QM_DFX_SQE_CNT_VF_SQN) & CURRENT_Q_MASK); 493 writel(tmp, qm->io_base + QM_DFX_SQE_CNT_VF_SQN); 494 495 tmp = val | 496 (readl(qm->io_base + QM_DFX_CQE_CNT_VF_CQN) & CURRENT_Q_MASK); 497 writel(tmp, qm->io_base + QM_DFX_CQE_CNT_VF_CQN); 498 499 return 0; 500 } 501 502 static u32 hpre_clear_enable_read(struct hpre_debugfs_file *file) 503 { 504 struct hisi_qm *qm = hpre_file_to_qm(file); 505 506 return readl(qm->io_base + HPRE_CTRL_CNT_CLR_CE) & 507 HPRE_CTRL_CNT_CLR_CE_BIT; 508 } 509 510 static int hpre_clear_enable_write(struct hpre_debugfs_file *file, u32 val) 511 { 512 struct hisi_qm *qm = hpre_file_to_qm(file); 513 u32 tmp; 514 515 if (val != 1 && val != 0) 516 return -EINVAL; 517 518 tmp = (readl(qm->io_base + HPRE_CTRL_CNT_CLR_CE) & 519 ~HPRE_CTRL_CNT_CLR_CE_BIT) | val; 520 writel(tmp, qm->io_base + HPRE_CTRL_CNT_CLR_CE); 521 522 return 0; 523 } 524 525 static u32 hpre_cluster_inqry_read(struct hpre_debugfs_file *file) 526 { 527 struct hisi_qm *qm = hpre_file_to_qm(file); 528 int cluster_index = file->index - HPRE_CLUSTER_CTRL; 529 unsigned long offset = HPRE_CLSTR_BASE + 530 cluster_index * HPRE_CLSTR_ADDR_INTRVL; 531 532 return readl(qm->io_base + offset + HPRE_CLSTR_ADDR_INQRY_RSLT); 533 } 534 535 static int hpre_cluster_inqry_write(struct hpre_debugfs_file *file, u32 val) 536 { 537 struct hisi_qm *qm = hpre_file_to_qm(file); 538 int cluster_index = file->index - HPRE_CLUSTER_CTRL; 539 unsigned long offset = HPRE_CLSTR_BASE + cluster_index * 540 HPRE_CLSTR_ADDR_INTRVL; 541 542 writel(val, qm->io_base + offset + HPRE_CLUSTER_INQURY); 543 544 return 0; 545 } 546 547 static ssize_t hpre_ctrl_debug_read(struct file *filp, char __user *buf, 548 size_t count, loff_t *pos) 549 { 550 struct hpre_debugfs_file *file = filp->private_data; 551 char tbuf[HPRE_DBGFS_VAL_MAX_LEN]; 552 u32 val; 553 int ret; 554 555 spin_lock_irq(&file->lock); 556 switch (file->type) { 557 case HPRE_CURRENT_QM: 558 val = hpre_current_qm_read(file); 559 break; 560 case HPRE_CLEAR_ENABLE: 561 val = hpre_clear_enable_read(file); 562 break; 563 case HPRE_CLUSTER_CTRL: 564 val = hpre_cluster_inqry_read(file); 565 break; 566 default: 567 spin_unlock_irq(&file->lock); 568 return -EINVAL; 569 } 570 spin_unlock_irq(&file->lock); 571 ret = snprintf(tbuf, HPRE_DBGFS_VAL_MAX_LEN, "%u\n", val); 572 return simple_read_from_buffer(buf, count, pos, tbuf, ret); 573 } 574 575 static ssize_t hpre_ctrl_debug_write(struct file *filp, const char __user *buf, 576 size_t count, loff_t *pos) 577 { 578 struct hpre_debugfs_file *file = filp->private_data; 579 char tbuf[HPRE_DBGFS_VAL_MAX_LEN]; 580 unsigned long val; 581 int len, ret; 582 583 if (*pos != 0) 584 return 0; 585 586 if (count >= HPRE_DBGFS_VAL_MAX_LEN) 587 return -ENOSPC; 588 589 len = simple_write_to_buffer(tbuf, HPRE_DBGFS_VAL_MAX_LEN - 1, 590 pos, buf, count); 591 if (len < 0) 592 return len; 593 594 tbuf[len] = '\0'; 595 if (kstrtoul(tbuf, 0, &val)) 596 return -EFAULT; 597 598 spin_lock_irq(&file->lock); 599 switch (file->type) { 600 case HPRE_CURRENT_QM: 601 ret = hpre_current_qm_write(file, val); 602 if (ret) 603 goto err_input; 604 break; 605 case HPRE_CLEAR_ENABLE: 606 ret = hpre_clear_enable_write(file, val); 607 if (ret) 608 goto err_input; 609 break; 610 case HPRE_CLUSTER_CTRL: 611 ret = hpre_cluster_inqry_write(file, val); 612 if (ret) 613 goto err_input; 614 break; 615 default: 616 ret = -EINVAL; 617 goto err_input; 618 } 619 spin_unlock_irq(&file->lock); 620 621 return count; 622 623 err_input: 624 spin_unlock_irq(&file->lock); 625 return ret; 626 } 627 628 static const struct file_operations hpre_ctrl_debug_fops = { 629 .owner = THIS_MODULE, 630 .open = simple_open, 631 .read = hpre_ctrl_debug_read, 632 .write = hpre_ctrl_debug_write, 633 }; 634 635 static int hpre_debugfs_atomic64_get(void *data, u64 *val) 636 { 637 struct hpre_dfx *dfx_item = data; 638 639 *val = atomic64_read(&dfx_item->value); 640 641 return 0; 642 } 643 644 static int hpre_debugfs_atomic64_set(void *data, u64 val) 645 { 646 struct hpre_dfx *dfx_item = data; 647 struct hpre_dfx *hpre_dfx = NULL; 648 649 if (dfx_item->type == HPRE_OVERTIME_THRHLD) { 650 hpre_dfx = dfx_item - HPRE_OVERTIME_THRHLD; 651 atomic64_set(&hpre_dfx[HPRE_OVER_THRHLD_CNT].value, 0); 652 } else if (val) { 653 return -EINVAL; 654 } 655 656 atomic64_set(&dfx_item->value, val); 657 658 return 0; 659 } 660 661 DEFINE_DEBUGFS_ATTRIBUTE(hpre_atomic64_ops, hpre_debugfs_atomic64_get, 662 hpre_debugfs_atomic64_set, "%llu\n"); 663 664 static int hpre_create_debugfs_file(struct hisi_qm *qm, struct dentry *dir, 665 enum hpre_ctrl_dbgfs_file type, int indx) 666 { 667 struct hpre *hpre = container_of(qm, struct hpre, qm); 668 struct hpre_debug *dbg = &hpre->debug; 669 struct dentry *file_dir; 670 671 if (dir) 672 file_dir = dir; 673 else 674 file_dir = qm->debug.debug_root; 675 676 if (type >= HPRE_DEBUG_FILE_NUM) 677 return -EINVAL; 678 679 spin_lock_init(&dbg->files[indx].lock); 680 dbg->files[indx].debug = dbg; 681 dbg->files[indx].type = type; 682 dbg->files[indx].index = indx; 683 debugfs_create_file(hpre_debug_file_name[type], 0600, file_dir, 684 dbg->files + indx, &hpre_ctrl_debug_fops); 685 686 return 0; 687 } 688 689 static int hpre_pf_comm_regs_debugfs_init(struct hisi_qm *qm) 690 { 691 struct device *dev = &qm->pdev->dev; 692 struct debugfs_regset32 *regset; 693 694 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 695 if (!regset) 696 return -ENOMEM; 697 698 regset->regs = hpre_com_dfx_regs; 699 regset->nregs = ARRAY_SIZE(hpre_com_dfx_regs); 700 regset->base = qm->io_base; 701 702 debugfs_create_regset32("regs", 0444, qm->debug.debug_root, regset); 703 return 0; 704 } 705 706 static int hpre_cluster_debugfs_init(struct hisi_qm *qm) 707 { 708 u8 clusters_num = HPRE_CLUSTERS_NUM(qm); 709 struct device *dev = &qm->pdev->dev; 710 char buf[HPRE_DBGFS_VAL_MAX_LEN]; 711 struct debugfs_regset32 *regset; 712 struct dentry *tmp_d; 713 int i, ret; 714 715 for (i = 0; i < clusters_num; i++) { 716 ret = snprintf(buf, HPRE_DBGFS_VAL_MAX_LEN, "cluster%d", i); 717 if (ret < 0) 718 return -EINVAL; 719 tmp_d = debugfs_create_dir(buf, qm->debug.debug_root); 720 721 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 722 if (!regset) 723 return -ENOMEM; 724 725 regset->regs = hpre_cluster_dfx_regs; 726 regset->nregs = ARRAY_SIZE(hpre_cluster_dfx_regs); 727 regset->base = qm->io_base + hpre_cluster_offsets[i]; 728 729 debugfs_create_regset32("regs", 0444, tmp_d, regset); 730 ret = hpre_create_debugfs_file(qm, tmp_d, HPRE_CLUSTER_CTRL, 731 i + HPRE_CLUSTER_CTRL); 732 if (ret) 733 return ret; 734 } 735 736 return 0; 737 } 738 739 static int hpre_ctrl_debug_init(struct hisi_qm *qm) 740 { 741 int ret; 742 743 ret = hpre_create_debugfs_file(qm, NULL, HPRE_CURRENT_QM, 744 HPRE_CURRENT_QM); 745 if (ret) 746 return ret; 747 748 ret = hpre_create_debugfs_file(qm, NULL, HPRE_CLEAR_ENABLE, 749 HPRE_CLEAR_ENABLE); 750 if (ret) 751 return ret; 752 753 ret = hpre_pf_comm_regs_debugfs_init(qm); 754 if (ret) 755 return ret; 756 757 return hpre_cluster_debugfs_init(qm); 758 } 759 760 static void hpre_dfx_debug_init(struct hisi_qm *qm) 761 { 762 struct hpre *hpre = container_of(qm, struct hpre, qm); 763 struct hpre_dfx *dfx = hpre->debug.dfx; 764 struct dentry *parent; 765 int i; 766 767 parent = debugfs_create_dir("hpre_dfx", qm->debug.debug_root); 768 for (i = 0; i < HPRE_DFX_FILE_NUM; i++) { 769 dfx[i].type = i; 770 debugfs_create_file(hpre_dfx_files[i], 0644, parent, &dfx[i], 771 &hpre_atomic64_ops); 772 } 773 } 774 775 static int hpre_debugfs_init(struct hisi_qm *qm) 776 { 777 struct device *dev = &qm->pdev->dev; 778 int ret; 779 780 qm->debug.debug_root = debugfs_create_dir(dev_name(dev), 781 hpre_debugfs_root); 782 783 qm->debug.sqe_mask_offset = HPRE_SQE_MASK_OFFSET; 784 qm->debug.sqe_mask_len = HPRE_SQE_MASK_LEN; 785 hisi_qm_debug_init(qm); 786 787 if (qm->pdev->device == HPRE_PCI_DEVICE_ID) { 788 ret = hpre_ctrl_debug_init(qm); 789 if (ret) 790 goto failed_to_create; 791 } 792 793 hpre_dfx_debug_init(qm); 794 795 return 0; 796 797 failed_to_create: 798 debugfs_remove_recursive(qm->debug.debug_root); 799 return ret; 800 } 801 802 static void hpre_debugfs_exit(struct hisi_qm *qm) 803 { 804 debugfs_remove_recursive(qm->debug.debug_root); 805 } 806 807 static int hpre_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) 808 { 809 if (pdev->revision == QM_HW_V1) { 810 pci_warn(pdev, "HPRE version 1 is not supported!\n"); 811 return -EINVAL; 812 } 813 814 if (pdev->revision >= QM_HW_V3) 815 qm->algs = "rsa\ndh\necdh\nx25519\nx448\necdsa\nsm2\n"; 816 else 817 qm->algs = "rsa\ndh\n"; 818 qm->mode = uacce_mode; 819 qm->pdev = pdev; 820 qm->ver = pdev->revision; 821 qm->sqe_size = HPRE_SQE_SIZE; 822 qm->dev_name = hpre_name; 823 824 qm->fun_type = (pdev->device == HPRE_PCI_DEVICE_ID) ? 825 QM_HW_PF : QM_HW_VF; 826 if (qm->fun_type == QM_HW_PF) { 827 qm->qp_base = HPRE_PF_DEF_Q_BASE; 828 qm->qp_num = pf_q_num; 829 qm->debug.curr_qm_qp_num = pf_q_num; 830 qm->qm_list = &hpre_devices; 831 } 832 833 return hisi_qm_init(qm); 834 } 835 836 static void hpre_log_hw_error(struct hisi_qm *qm, u32 err_sts) 837 { 838 const struct hpre_hw_error *err = hpre_hw_errors; 839 struct device *dev = &qm->pdev->dev; 840 841 while (err->msg) { 842 if (err->int_msk & err_sts) 843 dev_warn(dev, "%s [error status=0x%x] found\n", 844 err->msg, err->int_msk); 845 err++; 846 } 847 } 848 849 static u32 hpre_get_hw_err_status(struct hisi_qm *qm) 850 { 851 return readl(qm->io_base + HPRE_HAC_INT_STATUS); 852 } 853 854 static void hpre_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts) 855 { 856 writel(err_sts, qm->io_base + HPRE_HAC_SOURCE_INT); 857 } 858 859 static void hpre_open_axi_master_ooo(struct hisi_qm *qm) 860 { 861 u32 value; 862 863 value = readl(qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB); 864 writel(value & ~HPRE_AM_OOO_SHUTDOWN_ENABLE, 865 HPRE_ADDR(qm, HPRE_AM_OOO_SHUTDOWN_ENB)); 866 writel(value | HPRE_AM_OOO_SHUTDOWN_ENABLE, 867 HPRE_ADDR(qm, HPRE_AM_OOO_SHUTDOWN_ENB)); 868 } 869 870 static const struct hisi_qm_err_ini hpre_err_ini = { 871 .hw_init = hpre_set_user_domain_and_cache, 872 .hw_err_enable = hpre_hw_error_enable, 873 .hw_err_disable = hpre_hw_error_disable, 874 .get_dev_hw_err_status = hpre_get_hw_err_status, 875 .clear_dev_hw_err_status = hpre_clear_hw_err_status, 876 .log_dev_hw_err = hpre_log_hw_error, 877 .open_axi_master_ooo = hpre_open_axi_master_ooo, 878 .err_info = { 879 .ce = QM_BASE_CE, 880 .nfe = QM_BASE_NFE | QM_ACC_DO_TASK_TIMEOUT, 881 .fe = 0, 882 .ecc_2bits_mask = HPRE_CORE_ECC_2BIT_ERR | 883 HPRE_OOO_ECC_2BIT_ERR, 884 .dev_ce_mask = HPRE_HAC_RAS_CE_ENABLE, 885 .msi_wr_port = HPRE_WR_MSI_PORT, 886 .acpi_rst = "HRST", 887 } 888 }; 889 890 static int hpre_pf_probe_init(struct hpre *hpre) 891 { 892 struct hisi_qm *qm = &hpre->qm; 893 int ret; 894 895 qm->ctrl_qp_num = HPRE_QUEUE_NUM_V2; 896 897 ret = hpre_set_user_domain_and_cache(qm); 898 if (ret) 899 return ret; 900 901 qm->err_ini = &hpre_err_ini; 902 hisi_qm_dev_err_init(qm); 903 904 return 0; 905 } 906 907 static int hpre_probe_init(struct hpre *hpre) 908 { 909 struct hisi_qm *qm = &hpre->qm; 910 int ret; 911 912 if (qm->fun_type == QM_HW_PF) { 913 ret = hpre_pf_probe_init(hpre); 914 if (ret) 915 return ret; 916 } 917 918 return 0; 919 } 920 921 static int hpre_probe(struct pci_dev *pdev, const struct pci_device_id *id) 922 { 923 struct hisi_qm *qm; 924 struct hpre *hpre; 925 int ret; 926 927 hpre = devm_kzalloc(&pdev->dev, sizeof(*hpre), GFP_KERNEL); 928 if (!hpre) 929 return -ENOMEM; 930 931 qm = &hpre->qm; 932 ret = hpre_qm_init(qm, pdev); 933 if (ret) { 934 pci_err(pdev, "Failed to init HPRE QM (%d)!\n", ret); 935 return ret; 936 } 937 938 ret = hpre_probe_init(hpre); 939 if (ret) { 940 pci_err(pdev, "Failed to probe (%d)!\n", ret); 941 goto err_with_qm_init; 942 } 943 944 ret = hisi_qm_start(qm); 945 if (ret) 946 goto err_with_err_init; 947 948 ret = hpre_debugfs_init(qm); 949 if (ret) 950 dev_warn(&pdev->dev, "init debugfs fail!\n"); 951 952 ret = hisi_qm_alg_register(qm, &hpre_devices); 953 if (ret < 0) { 954 pci_err(pdev, "fail to register algs to crypto!\n"); 955 goto err_with_qm_start; 956 } 957 958 if (qm->uacce) { 959 ret = uacce_register(qm->uacce); 960 if (ret) { 961 pci_err(pdev, "failed to register uacce (%d)!\n", ret); 962 goto err_with_alg_register; 963 } 964 } 965 966 if (qm->fun_type == QM_HW_PF && vfs_num) { 967 ret = hisi_qm_sriov_enable(pdev, vfs_num); 968 if (ret < 0) 969 goto err_with_alg_register; 970 } 971 972 return 0; 973 974 err_with_alg_register: 975 hisi_qm_alg_unregister(qm, &hpre_devices); 976 977 err_with_qm_start: 978 hpre_debugfs_exit(qm); 979 hisi_qm_stop(qm, QM_NORMAL); 980 981 err_with_err_init: 982 hisi_qm_dev_err_uninit(qm); 983 984 err_with_qm_init: 985 hisi_qm_uninit(qm); 986 987 return ret; 988 } 989 990 static void hpre_remove(struct pci_dev *pdev) 991 { 992 struct hisi_qm *qm = pci_get_drvdata(pdev); 993 int ret; 994 995 hisi_qm_wait_task_finish(qm, &hpre_devices); 996 hisi_qm_alg_unregister(qm, &hpre_devices); 997 if (qm->fun_type == QM_HW_PF && qm->vfs_num) { 998 ret = hisi_qm_sriov_disable(pdev, true); 999 if (ret) { 1000 pci_err(pdev, "Disable SRIOV fail!\n"); 1001 return; 1002 } 1003 } 1004 1005 hpre_debugfs_exit(qm); 1006 hisi_qm_stop(qm, QM_NORMAL); 1007 1008 if (qm->fun_type == QM_HW_PF) { 1009 if (qm->use_sva && qm->ver == QM_HW_V2) 1010 hpre_pasid_disable(qm); 1011 hpre_cnt_regs_clear(qm); 1012 qm->debug.curr_qm_qp_num = 0; 1013 hisi_qm_dev_err_uninit(qm); 1014 } 1015 1016 hisi_qm_uninit(qm); 1017 } 1018 1019 1020 static const struct pci_error_handlers hpre_err_handler = { 1021 .error_detected = hisi_qm_dev_err_detected, 1022 .slot_reset = hisi_qm_dev_slot_reset, 1023 .reset_prepare = hisi_qm_reset_prepare, 1024 .reset_done = hisi_qm_reset_done, 1025 }; 1026 1027 static struct pci_driver hpre_pci_driver = { 1028 .name = hpre_name, 1029 .id_table = hpre_dev_ids, 1030 .probe = hpre_probe, 1031 .remove = hpre_remove, 1032 .sriov_configure = IS_ENABLED(CONFIG_PCI_IOV) ? 1033 hisi_qm_sriov_configure : NULL, 1034 .err_handler = &hpre_err_handler, 1035 .shutdown = hisi_qm_dev_shutdown, 1036 }; 1037 1038 static void hpre_register_debugfs(void) 1039 { 1040 if (!debugfs_initialized()) 1041 return; 1042 1043 hpre_debugfs_root = debugfs_create_dir(hpre_name, NULL); 1044 } 1045 1046 static void hpre_unregister_debugfs(void) 1047 { 1048 debugfs_remove_recursive(hpre_debugfs_root); 1049 } 1050 1051 static int __init hpre_init(void) 1052 { 1053 int ret; 1054 1055 hisi_qm_init_list(&hpre_devices); 1056 hpre_register_debugfs(); 1057 1058 ret = pci_register_driver(&hpre_pci_driver); 1059 if (ret) { 1060 hpre_unregister_debugfs(); 1061 pr_err("hpre: can't register hisi hpre driver.\n"); 1062 } 1063 1064 return ret; 1065 } 1066 1067 static void __exit hpre_exit(void) 1068 { 1069 pci_unregister_driver(&hpre_pci_driver); 1070 hpre_unregister_debugfs(); 1071 } 1072 1073 module_init(hpre_init); 1074 module_exit(hpre_exit); 1075 1076 MODULE_LICENSE("GPL v2"); 1077 MODULE_AUTHOR("Zaibo Xu <xuzaibo@huawei.com>"); 1078 MODULE_DESCRIPTION("Driver for HiSilicon HPRE accelerator"); 1079