1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018-2019 HiSilicon Limited. */ 3 #include <linux/acpi.h> 4 #include <linux/aer.h> 5 #include <linux/bitops.h> 6 #include <linux/debugfs.h> 7 #include <linux/init.h> 8 #include <linux/io.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/topology.h> 14 #include <linux/uacce.h> 15 #include "hpre.h" 16 17 #define HPRE_QM_ABNML_INT_MASK 0x100004 18 #define HPRE_CTRL_CNT_CLR_CE_BIT BIT(0) 19 #define HPRE_COMM_CNT_CLR_CE 0x0 20 #define HPRE_CTRL_CNT_CLR_CE 0x301000 21 #define HPRE_FSM_MAX_CNT 0x301008 22 #define HPRE_VFG_AXQOS 0x30100c 23 #define HPRE_VFG_AXCACHE 0x301010 24 #define HPRE_RDCHN_INI_CFG 0x301014 25 #define HPRE_AWUSR_FP_CFG 0x301018 26 #define HPRE_BD_ENDIAN 0x301020 27 #define HPRE_ECC_BYPASS 0x301024 28 #define HPRE_RAS_WIDTH_CFG 0x301028 29 #define HPRE_POISON_BYPASS 0x30102c 30 #define HPRE_BD_ARUSR_CFG 0x301030 31 #define HPRE_BD_AWUSR_CFG 0x301034 32 #define HPRE_TYPES_ENB 0x301038 33 #define HPRE_RSA_ENB BIT(0) 34 #define HPRE_ECC_ENB BIT(1) 35 #define HPRE_DATA_RUSER_CFG 0x30103c 36 #define HPRE_DATA_WUSER_CFG 0x301040 37 #define HPRE_INT_MASK 0x301400 38 #define HPRE_INT_STATUS 0x301800 39 #define HPRE_HAC_INT_MSK 0x301400 40 #define HPRE_HAC_RAS_CE_ENB 0x301410 41 #define HPRE_HAC_RAS_NFE_ENB 0x301414 42 #define HPRE_HAC_RAS_FE_ENB 0x301418 43 #define HPRE_HAC_INT_SET 0x301500 44 #define HPRE_RNG_TIMEOUT_NUM 0x301A34 45 #define HPRE_CORE_INT_ENABLE 0 46 #define HPRE_CORE_INT_DISABLE GENMASK(21, 0) 47 #define HPRE_RDCHN_INI_ST 0x301a00 48 #define HPRE_CLSTR_BASE 0x302000 49 #define HPRE_CORE_EN_OFFSET 0x04 50 #define HPRE_CORE_INI_CFG_OFFSET 0x20 51 #define HPRE_CORE_INI_STATUS_OFFSET 0x80 52 #define HPRE_CORE_HTBT_WARN_OFFSET 0x8c 53 #define HPRE_CORE_IS_SCHD_OFFSET 0x90 54 55 #define HPRE_RAS_CE_ENB 0x301410 56 #define HPRE_HAC_RAS_CE_ENABLE (BIT(0) | BIT(22) | BIT(23)) 57 #define HPRE_RAS_NFE_ENB 0x301414 58 #define HPRE_HAC_RAS_NFE_ENABLE 0x3ffffe 59 #define HPRE_RAS_FE_ENB 0x301418 60 #define HPRE_OOO_SHUTDOWN_SEL 0x301a3c 61 #define HPRE_HAC_RAS_FE_ENABLE 0 62 63 #define HPRE_CORE_ENB (HPRE_CLSTR_BASE + HPRE_CORE_EN_OFFSET) 64 #define HPRE_CORE_INI_CFG (HPRE_CLSTR_BASE + HPRE_CORE_INI_CFG_OFFSET) 65 #define HPRE_CORE_INI_STATUS (HPRE_CLSTR_BASE + HPRE_CORE_INI_STATUS_OFFSET) 66 #define HPRE_HAC_ECC1_CNT 0x301a04 67 #define HPRE_HAC_ECC2_CNT 0x301a08 68 #define HPRE_HAC_SOURCE_INT 0x301600 69 #define HPRE_CLSTR_ADDR_INTRVL 0x1000 70 #define HPRE_CLUSTER_INQURY 0x100 71 #define HPRE_CLSTR_ADDR_INQRY_RSLT 0x104 72 #define HPRE_TIMEOUT_ABNML_BIT 6 73 #define HPRE_PASID_EN_BIT 9 74 #define HPRE_REG_RD_INTVRL_US 10 75 #define HPRE_REG_RD_TMOUT_US 1000 76 #define HPRE_DBGFS_VAL_MAX_LEN 20 77 #define PCI_DEVICE_ID_HUAWEI_HPRE_PF 0xa258 78 #define HPRE_QM_USR_CFG_MASK GENMASK(31, 1) 79 #define HPRE_QM_AXI_CFG_MASK GENMASK(15, 0) 80 #define HPRE_QM_VFG_AX_MASK GENMASK(7, 0) 81 #define HPRE_BD_USR_MASK GENMASK(1, 0) 82 #define HPRE_CLUSTER_CORE_MASK_V2 GENMASK(3, 0) 83 #define HPRE_CLUSTER_CORE_MASK_V3 GENMASK(7, 0) 84 #define HPRE_PREFETCH_CFG 0x301130 85 #define HPRE_SVA_PREFTCH_DFX 0x30115C 86 #define HPRE_PREFETCH_ENABLE (~(BIT(0) | BIT(30))) 87 #define HPRE_PREFETCH_DISABLE BIT(30) 88 #define HPRE_SVA_DISABLE_READY (BIT(4) | BIT(8)) 89 90 /* clock gate */ 91 #define HPRE_CLKGATE_CTL 0x301a10 92 #define HPRE_PEH_CFG_AUTO_GATE 0x301a2c 93 #define HPRE_CLUSTER_DYN_CTL 0x302010 94 #define HPRE_CORE_SHB_CFG 0x302088 95 #define HPRE_CLKGATE_CTL_EN BIT(0) 96 #define HPRE_PEH_CFG_AUTO_GATE_EN BIT(0) 97 #define HPRE_CLUSTER_DYN_CTL_EN BIT(0) 98 #define HPRE_CORE_GATE_EN (BIT(30) | BIT(31)) 99 100 #define HPRE_AM_OOO_SHUTDOWN_ENB 0x301044 101 #define HPRE_AM_OOO_SHUTDOWN_ENABLE BIT(0) 102 #define HPRE_WR_MSI_PORT BIT(2) 103 104 #define HPRE_CORE_ECC_2BIT_ERR BIT(1) 105 #define HPRE_OOO_ECC_2BIT_ERR BIT(5) 106 107 #define HPRE_QM_BME_FLR BIT(7) 108 #define HPRE_QM_PM_FLR BIT(11) 109 #define HPRE_QM_SRIOV_FLR BIT(12) 110 111 #define HPRE_SHAPER_TYPE_RATE 640 112 #define HPRE_VIA_MSI_DSM 1 113 #define HPRE_SQE_MASK_OFFSET 8 114 #define HPRE_SQE_MASK_LEN 24 115 116 #define HPRE_DFX_BASE 0x301000 117 #define HPRE_DFX_COMMON1 0x301400 118 #define HPRE_DFX_COMMON2 0x301A00 119 #define HPRE_DFX_CORE 0x302000 120 #define HPRE_DFX_BASE_LEN 0x55 121 #define HPRE_DFX_COMMON1_LEN 0x41 122 #define HPRE_DFX_COMMON2_LEN 0xE 123 #define HPRE_DFX_CORE_LEN 0x43 124 125 static const char hpre_name[] = "hisi_hpre"; 126 static struct dentry *hpre_debugfs_root; 127 static const struct pci_device_id hpre_dev_ids[] = { 128 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_HPRE_PF) }, 129 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_HPRE_VF) }, 130 { 0, } 131 }; 132 133 MODULE_DEVICE_TABLE(pci, hpre_dev_ids); 134 135 struct hpre_hw_error { 136 u32 int_msk; 137 const char *msg; 138 }; 139 140 static struct hisi_qm_list hpre_devices = { 141 .register_to_crypto = hpre_algs_register, 142 .unregister_from_crypto = hpre_algs_unregister, 143 }; 144 145 static const char * const hpre_debug_file_name[] = { 146 [HPRE_CLEAR_ENABLE] = "rdclr_en", 147 [HPRE_CLUSTER_CTRL] = "cluster_ctrl", 148 }; 149 150 static const struct hpre_hw_error hpre_hw_errors[] = { 151 { 152 .int_msk = BIT(0), 153 .msg = "core_ecc_1bit_err_int_set" 154 }, { 155 .int_msk = BIT(1), 156 .msg = "core_ecc_2bit_err_int_set" 157 }, { 158 .int_msk = BIT(2), 159 .msg = "dat_wb_poison_int_set" 160 }, { 161 .int_msk = BIT(3), 162 .msg = "dat_rd_poison_int_set" 163 }, { 164 .int_msk = BIT(4), 165 .msg = "bd_rd_poison_int_set" 166 }, { 167 .int_msk = BIT(5), 168 .msg = "ooo_ecc_2bit_err_int_set" 169 }, { 170 .int_msk = BIT(6), 171 .msg = "cluster1_shb_timeout_int_set" 172 }, { 173 .int_msk = BIT(7), 174 .msg = "cluster2_shb_timeout_int_set" 175 }, { 176 .int_msk = BIT(8), 177 .msg = "cluster3_shb_timeout_int_set" 178 }, { 179 .int_msk = BIT(9), 180 .msg = "cluster4_shb_timeout_int_set" 181 }, { 182 .int_msk = GENMASK(15, 10), 183 .msg = "ooo_rdrsp_err_int_set" 184 }, { 185 .int_msk = GENMASK(21, 16), 186 .msg = "ooo_wrrsp_err_int_set" 187 }, { 188 .int_msk = BIT(22), 189 .msg = "pt_rng_timeout_int_set" 190 }, { 191 .int_msk = BIT(23), 192 .msg = "sva_fsm_timeout_int_set" 193 }, { 194 /* sentinel */ 195 } 196 }; 197 198 static const u64 hpre_cluster_offsets[] = { 199 [HPRE_CLUSTER0] = 200 HPRE_CLSTR_BASE + HPRE_CLUSTER0 * HPRE_CLSTR_ADDR_INTRVL, 201 [HPRE_CLUSTER1] = 202 HPRE_CLSTR_BASE + HPRE_CLUSTER1 * HPRE_CLSTR_ADDR_INTRVL, 203 [HPRE_CLUSTER2] = 204 HPRE_CLSTR_BASE + HPRE_CLUSTER2 * HPRE_CLSTR_ADDR_INTRVL, 205 [HPRE_CLUSTER3] = 206 HPRE_CLSTR_BASE + HPRE_CLUSTER3 * HPRE_CLSTR_ADDR_INTRVL, 207 }; 208 209 static const struct debugfs_reg32 hpre_cluster_dfx_regs[] = { 210 {"CORES_EN_STATUS ", HPRE_CORE_EN_OFFSET}, 211 {"CORES_INI_CFG ", HPRE_CORE_INI_CFG_OFFSET}, 212 {"CORES_INI_STATUS ", HPRE_CORE_INI_STATUS_OFFSET}, 213 {"CORES_HTBT_WARN ", HPRE_CORE_HTBT_WARN_OFFSET}, 214 {"CORES_IS_SCHD ", HPRE_CORE_IS_SCHD_OFFSET}, 215 }; 216 217 static const struct debugfs_reg32 hpre_com_dfx_regs[] = { 218 {"READ_CLR_EN ", HPRE_CTRL_CNT_CLR_CE}, 219 {"AXQOS ", HPRE_VFG_AXQOS}, 220 {"AWUSR_CFG ", HPRE_AWUSR_FP_CFG}, 221 {"BD_ENDIAN ", HPRE_BD_ENDIAN}, 222 {"ECC_CHECK_CTRL ", HPRE_ECC_BYPASS}, 223 {"RAS_INT_WIDTH ", HPRE_RAS_WIDTH_CFG}, 224 {"POISON_BYPASS ", HPRE_POISON_BYPASS}, 225 {"BD_ARUSER ", HPRE_BD_ARUSR_CFG}, 226 {"BD_AWUSER ", HPRE_BD_AWUSR_CFG}, 227 {"DATA_ARUSER ", HPRE_DATA_RUSER_CFG}, 228 {"DATA_AWUSER ", HPRE_DATA_WUSER_CFG}, 229 {"INT_STATUS ", HPRE_INT_STATUS}, 230 {"INT_MASK ", HPRE_HAC_INT_MSK}, 231 {"RAS_CE_ENB ", HPRE_HAC_RAS_CE_ENB}, 232 {"RAS_NFE_ENB ", HPRE_HAC_RAS_NFE_ENB}, 233 {"RAS_FE_ENB ", HPRE_HAC_RAS_FE_ENB}, 234 {"INT_SET ", HPRE_HAC_INT_SET}, 235 {"RNG_TIMEOUT_NUM ", HPRE_RNG_TIMEOUT_NUM}, 236 }; 237 238 static const char *hpre_dfx_files[HPRE_DFX_FILE_NUM] = { 239 "send_cnt", 240 "recv_cnt", 241 "send_fail_cnt", 242 "send_busy_cnt", 243 "over_thrhld_cnt", 244 "overtime_thrhld", 245 "invalid_req_cnt" 246 }; 247 248 /* define the HPRE's dfx regs region and region length */ 249 static struct dfx_diff_registers hpre_diff_regs[] = { 250 { 251 .reg_offset = HPRE_DFX_BASE, 252 .reg_len = HPRE_DFX_BASE_LEN, 253 }, { 254 .reg_offset = HPRE_DFX_COMMON1, 255 .reg_len = HPRE_DFX_COMMON1_LEN, 256 }, { 257 .reg_offset = HPRE_DFX_COMMON2, 258 .reg_len = HPRE_DFX_COMMON2_LEN, 259 }, { 260 .reg_offset = HPRE_DFX_CORE, 261 .reg_len = HPRE_DFX_CORE_LEN, 262 }, 263 }; 264 265 static int hpre_diff_regs_show(struct seq_file *s, void *unused) 266 { 267 struct hisi_qm *qm = s->private; 268 269 hisi_qm_acc_diff_regs_dump(qm, s, qm->debug.acc_diff_regs, 270 ARRAY_SIZE(hpre_diff_regs)); 271 272 return 0; 273 } 274 275 DEFINE_SHOW_ATTRIBUTE(hpre_diff_regs); 276 277 static int hpre_com_regs_show(struct seq_file *s, void *unused) 278 { 279 hisi_qm_regs_dump(s, s->private); 280 281 return 0; 282 } 283 284 DEFINE_SHOW_ATTRIBUTE(hpre_com_regs); 285 286 static int hpre_cluster_regs_show(struct seq_file *s, void *unused) 287 { 288 hisi_qm_regs_dump(s, s->private); 289 290 return 0; 291 } 292 293 DEFINE_SHOW_ATTRIBUTE(hpre_cluster_regs); 294 295 static const struct kernel_param_ops hpre_uacce_mode_ops = { 296 .set = uacce_mode_set, 297 .get = param_get_int, 298 }; 299 300 /* 301 * uacce_mode = 0 means hpre only register to crypto, 302 * uacce_mode = 1 means hpre both register to crypto and uacce. 303 */ 304 static u32 uacce_mode = UACCE_MODE_NOUACCE; 305 module_param_cb(uacce_mode, &hpre_uacce_mode_ops, &uacce_mode, 0444); 306 MODULE_PARM_DESC(uacce_mode, UACCE_MODE_DESC); 307 308 static int pf_q_num_set(const char *val, const struct kernel_param *kp) 309 { 310 return q_num_set(val, kp, PCI_DEVICE_ID_HUAWEI_HPRE_PF); 311 } 312 313 static const struct kernel_param_ops hpre_pf_q_num_ops = { 314 .set = pf_q_num_set, 315 .get = param_get_int, 316 }; 317 318 static u32 pf_q_num = HPRE_PF_DEF_Q_NUM; 319 module_param_cb(pf_q_num, &hpre_pf_q_num_ops, &pf_q_num, 0444); 320 MODULE_PARM_DESC(pf_q_num, "Number of queues in PF of CS(2-1024)"); 321 322 static const struct kernel_param_ops vfs_num_ops = { 323 .set = vfs_num_set, 324 .get = param_get_int, 325 }; 326 327 static u32 vfs_num; 328 module_param_cb(vfs_num, &vfs_num_ops, &vfs_num, 0444); 329 MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)"); 330 331 static inline int hpre_cluster_num(struct hisi_qm *qm) 332 { 333 return (qm->ver >= QM_HW_V3) ? HPRE_CLUSTERS_NUM_V3 : 334 HPRE_CLUSTERS_NUM_V2; 335 } 336 337 static inline int hpre_cluster_core_mask(struct hisi_qm *qm) 338 { 339 return (qm->ver >= QM_HW_V3) ? 340 HPRE_CLUSTER_CORE_MASK_V3 : HPRE_CLUSTER_CORE_MASK_V2; 341 } 342 343 struct hisi_qp *hpre_create_qp(u8 type) 344 { 345 int node = cpu_to_node(smp_processor_id()); 346 struct hisi_qp *qp = NULL; 347 int ret; 348 349 if (type != HPRE_V2_ALG_TYPE && type != HPRE_V3_ECC_ALG_TYPE) 350 return NULL; 351 352 /* 353 * type: 0 - RSA/DH. algorithm supported in V2, 354 * 1 - ECC algorithm in V3. 355 */ 356 ret = hisi_qm_alloc_qps_node(&hpre_devices, 1, type, node, &qp); 357 if (!ret) 358 return qp; 359 360 return NULL; 361 } 362 363 static void hpre_config_pasid(struct hisi_qm *qm) 364 { 365 u32 val1, val2; 366 367 if (qm->ver >= QM_HW_V3) 368 return; 369 370 val1 = readl_relaxed(qm->io_base + HPRE_DATA_RUSER_CFG); 371 val2 = readl_relaxed(qm->io_base + HPRE_DATA_WUSER_CFG); 372 if (qm->use_sva) { 373 val1 |= BIT(HPRE_PASID_EN_BIT); 374 val2 |= BIT(HPRE_PASID_EN_BIT); 375 } else { 376 val1 &= ~BIT(HPRE_PASID_EN_BIT); 377 val2 &= ~BIT(HPRE_PASID_EN_BIT); 378 } 379 writel_relaxed(val1, qm->io_base + HPRE_DATA_RUSER_CFG); 380 writel_relaxed(val2, qm->io_base + HPRE_DATA_WUSER_CFG); 381 } 382 383 static int hpre_cfg_by_dsm(struct hisi_qm *qm) 384 { 385 struct device *dev = &qm->pdev->dev; 386 union acpi_object *obj; 387 guid_t guid; 388 389 if (guid_parse("b06b81ab-0134-4a45-9b0c-483447b95fa7", &guid)) { 390 dev_err(dev, "Hpre GUID failed\n"); 391 return -EINVAL; 392 } 393 394 /* Switch over to MSI handling due to non-standard PCI implementation */ 395 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &guid, 396 0, HPRE_VIA_MSI_DSM, NULL); 397 if (!obj) { 398 dev_err(dev, "ACPI handle failed!\n"); 399 return -EIO; 400 } 401 402 ACPI_FREE(obj); 403 404 return 0; 405 } 406 407 static int hpre_set_cluster(struct hisi_qm *qm) 408 { 409 u32 cluster_core_mask = hpre_cluster_core_mask(qm); 410 u8 clusters_num = hpre_cluster_num(qm); 411 struct device *dev = &qm->pdev->dev; 412 unsigned long offset; 413 u32 val = 0; 414 int ret, i; 415 416 for (i = 0; i < clusters_num; i++) { 417 offset = i * HPRE_CLSTR_ADDR_INTRVL; 418 419 /* clusters initiating */ 420 writel(cluster_core_mask, 421 qm->io_base + offset + HPRE_CORE_ENB); 422 writel(0x1, qm->io_base + offset + HPRE_CORE_INI_CFG); 423 ret = readl_relaxed_poll_timeout(qm->io_base + offset + 424 HPRE_CORE_INI_STATUS, val, 425 ((val & cluster_core_mask) == 426 cluster_core_mask), 427 HPRE_REG_RD_INTVRL_US, 428 HPRE_REG_RD_TMOUT_US); 429 if (ret) { 430 dev_err(dev, 431 "cluster %d int st status timeout!\n", i); 432 return -ETIMEDOUT; 433 } 434 } 435 436 return 0; 437 } 438 439 /* 440 * For Kunpeng 920, we should disable FLR triggered by hardware (BME/PM/SRIOV). 441 * Or it may stay in D3 state when we bind and unbind hpre quickly, 442 * as it does FLR triggered by hardware. 443 */ 444 static void disable_flr_of_bme(struct hisi_qm *qm) 445 { 446 u32 val; 447 448 val = readl(qm->io_base + QM_PEH_AXUSER_CFG); 449 val &= ~(HPRE_QM_BME_FLR | HPRE_QM_SRIOV_FLR); 450 val |= HPRE_QM_PM_FLR; 451 writel(val, qm->io_base + QM_PEH_AXUSER_CFG); 452 writel(PEH_AXUSER_CFG_ENABLE, qm->io_base + QM_PEH_AXUSER_CFG_ENABLE); 453 } 454 455 static void hpre_open_sva_prefetch(struct hisi_qm *qm) 456 { 457 u32 val; 458 int ret; 459 460 if (qm->ver < QM_HW_V3) 461 return; 462 463 /* Enable prefetch */ 464 val = readl_relaxed(qm->io_base + HPRE_PREFETCH_CFG); 465 val &= HPRE_PREFETCH_ENABLE; 466 writel(val, qm->io_base + HPRE_PREFETCH_CFG); 467 468 ret = readl_relaxed_poll_timeout(qm->io_base + HPRE_PREFETCH_CFG, 469 val, !(val & HPRE_PREFETCH_DISABLE), 470 HPRE_REG_RD_INTVRL_US, 471 HPRE_REG_RD_TMOUT_US); 472 if (ret) 473 pci_err(qm->pdev, "failed to open sva prefetch\n"); 474 } 475 476 static void hpre_close_sva_prefetch(struct hisi_qm *qm) 477 { 478 u32 val; 479 int ret; 480 481 if (qm->ver < QM_HW_V3) 482 return; 483 484 val = readl_relaxed(qm->io_base + HPRE_PREFETCH_CFG); 485 val |= HPRE_PREFETCH_DISABLE; 486 writel(val, qm->io_base + HPRE_PREFETCH_CFG); 487 488 ret = readl_relaxed_poll_timeout(qm->io_base + HPRE_SVA_PREFTCH_DFX, 489 val, !(val & HPRE_SVA_DISABLE_READY), 490 HPRE_REG_RD_INTVRL_US, 491 HPRE_REG_RD_TMOUT_US); 492 if (ret) 493 pci_err(qm->pdev, "failed to close sva prefetch\n"); 494 } 495 496 static void hpre_enable_clock_gate(struct hisi_qm *qm) 497 { 498 u32 val; 499 500 if (qm->ver < QM_HW_V3) 501 return; 502 503 val = readl(qm->io_base + HPRE_CLKGATE_CTL); 504 val |= HPRE_CLKGATE_CTL_EN; 505 writel(val, qm->io_base + HPRE_CLKGATE_CTL); 506 507 val = readl(qm->io_base + HPRE_PEH_CFG_AUTO_GATE); 508 val |= HPRE_PEH_CFG_AUTO_GATE_EN; 509 writel(val, qm->io_base + HPRE_PEH_CFG_AUTO_GATE); 510 511 val = readl(qm->io_base + HPRE_CLUSTER_DYN_CTL); 512 val |= HPRE_CLUSTER_DYN_CTL_EN; 513 writel(val, qm->io_base + HPRE_CLUSTER_DYN_CTL); 514 515 val = readl_relaxed(qm->io_base + HPRE_CORE_SHB_CFG); 516 val |= HPRE_CORE_GATE_EN; 517 writel(val, qm->io_base + HPRE_CORE_SHB_CFG); 518 } 519 520 static void hpre_disable_clock_gate(struct hisi_qm *qm) 521 { 522 u32 val; 523 524 if (qm->ver < QM_HW_V3) 525 return; 526 527 val = readl(qm->io_base + HPRE_CLKGATE_CTL); 528 val &= ~HPRE_CLKGATE_CTL_EN; 529 writel(val, qm->io_base + HPRE_CLKGATE_CTL); 530 531 val = readl(qm->io_base + HPRE_PEH_CFG_AUTO_GATE); 532 val &= ~HPRE_PEH_CFG_AUTO_GATE_EN; 533 writel(val, qm->io_base + HPRE_PEH_CFG_AUTO_GATE); 534 535 val = readl(qm->io_base + HPRE_CLUSTER_DYN_CTL); 536 val &= ~HPRE_CLUSTER_DYN_CTL_EN; 537 writel(val, qm->io_base + HPRE_CLUSTER_DYN_CTL); 538 539 val = readl_relaxed(qm->io_base + HPRE_CORE_SHB_CFG); 540 val &= ~HPRE_CORE_GATE_EN; 541 writel(val, qm->io_base + HPRE_CORE_SHB_CFG); 542 } 543 544 static int hpre_set_user_domain_and_cache(struct hisi_qm *qm) 545 { 546 struct device *dev = &qm->pdev->dev; 547 u32 val; 548 int ret; 549 550 /* disabel dynamic clock gate before sram init */ 551 hpre_disable_clock_gate(qm); 552 553 writel(HPRE_QM_USR_CFG_MASK, qm->io_base + QM_ARUSER_M_CFG_ENABLE); 554 writel(HPRE_QM_USR_CFG_MASK, qm->io_base + QM_AWUSER_M_CFG_ENABLE); 555 writel_relaxed(HPRE_QM_AXI_CFG_MASK, qm->io_base + QM_AXI_M_CFG); 556 557 /* HPRE need more time, we close this interrupt */ 558 val = readl_relaxed(qm->io_base + HPRE_QM_ABNML_INT_MASK); 559 val |= BIT(HPRE_TIMEOUT_ABNML_BIT); 560 writel_relaxed(val, qm->io_base + HPRE_QM_ABNML_INT_MASK); 561 562 if (qm->ver >= QM_HW_V3) 563 writel(HPRE_RSA_ENB | HPRE_ECC_ENB, 564 qm->io_base + HPRE_TYPES_ENB); 565 else 566 writel(HPRE_RSA_ENB, qm->io_base + HPRE_TYPES_ENB); 567 568 writel(HPRE_QM_VFG_AX_MASK, qm->io_base + HPRE_VFG_AXCACHE); 569 writel(0x0, qm->io_base + HPRE_BD_ENDIAN); 570 writel(0x0, qm->io_base + HPRE_INT_MASK); 571 writel(0x0, qm->io_base + HPRE_POISON_BYPASS); 572 writel(0x0, qm->io_base + HPRE_COMM_CNT_CLR_CE); 573 writel(0x0, qm->io_base + HPRE_ECC_BYPASS); 574 575 writel(HPRE_BD_USR_MASK, qm->io_base + HPRE_BD_ARUSR_CFG); 576 writel(HPRE_BD_USR_MASK, qm->io_base + HPRE_BD_AWUSR_CFG); 577 writel(0x1, qm->io_base + HPRE_RDCHN_INI_CFG); 578 ret = readl_relaxed_poll_timeout(qm->io_base + HPRE_RDCHN_INI_ST, val, 579 val & BIT(0), 580 HPRE_REG_RD_INTVRL_US, 581 HPRE_REG_RD_TMOUT_US); 582 if (ret) { 583 dev_err(dev, "read rd channel timeout fail!\n"); 584 return -ETIMEDOUT; 585 } 586 587 ret = hpre_set_cluster(qm); 588 if (ret) 589 return -ETIMEDOUT; 590 591 /* This setting is only needed by Kunpeng 920. */ 592 if (qm->ver == QM_HW_V2) { 593 ret = hpre_cfg_by_dsm(qm); 594 if (ret) 595 return ret; 596 597 disable_flr_of_bme(qm); 598 } 599 600 /* Config data buffer pasid needed by Kunpeng 920 */ 601 hpre_config_pasid(qm); 602 603 hpre_enable_clock_gate(qm); 604 605 return ret; 606 } 607 608 static void hpre_cnt_regs_clear(struct hisi_qm *qm) 609 { 610 u8 clusters_num = hpre_cluster_num(qm); 611 unsigned long offset; 612 int i; 613 614 /* clear clusterX/cluster_ctrl */ 615 for (i = 0; i < clusters_num; i++) { 616 offset = HPRE_CLSTR_BASE + i * HPRE_CLSTR_ADDR_INTRVL; 617 writel(0x0, qm->io_base + offset + HPRE_CLUSTER_INQURY); 618 } 619 620 /* clear rdclr_en */ 621 writel(0x0, qm->io_base + HPRE_CTRL_CNT_CLR_CE); 622 623 hisi_qm_debug_regs_clear(qm); 624 } 625 626 static void hpre_master_ooo_ctrl(struct hisi_qm *qm, bool enable) 627 { 628 u32 val1, val2; 629 630 val1 = readl(qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB); 631 if (enable) { 632 val1 |= HPRE_AM_OOO_SHUTDOWN_ENABLE; 633 val2 = HPRE_HAC_RAS_NFE_ENABLE; 634 } else { 635 val1 &= ~HPRE_AM_OOO_SHUTDOWN_ENABLE; 636 val2 = 0x0; 637 } 638 639 if (qm->ver > QM_HW_V2) 640 writel(val2, qm->io_base + HPRE_OOO_SHUTDOWN_SEL); 641 642 writel(val1, qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB); 643 } 644 645 static void hpre_hw_error_disable(struct hisi_qm *qm) 646 { 647 /* disable hpre hw error interrupts */ 648 writel(HPRE_CORE_INT_DISABLE, qm->io_base + HPRE_INT_MASK); 649 650 /* disable HPRE block master OOO when nfe occurs on Kunpeng930 */ 651 hpre_master_ooo_ctrl(qm, false); 652 } 653 654 static void hpre_hw_error_enable(struct hisi_qm *qm) 655 { 656 /* clear HPRE hw error source if having */ 657 writel(HPRE_CORE_INT_DISABLE, qm->io_base + HPRE_HAC_SOURCE_INT); 658 659 /* configure error type */ 660 writel(HPRE_HAC_RAS_CE_ENABLE, qm->io_base + HPRE_RAS_CE_ENB); 661 writel(HPRE_HAC_RAS_NFE_ENABLE, qm->io_base + HPRE_RAS_NFE_ENB); 662 writel(HPRE_HAC_RAS_FE_ENABLE, qm->io_base + HPRE_RAS_FE_ENB); 663 664 /* enable HPRE block master OOO when nfe occurs on Kunpeng930 */ 665 hpre_master_ooo_ctrl(qm, true); 666 667 /* enable hpre hw error interrupts */ 668 writel(HPRE_CORE_INT_ENABLE, qm->io_base + HPRE_INT_MASK); 669 } 670 671 static inline struct hisi_qm *hpre_file_to_qm(struct hpre_debugfs_file *file) 672 { 673 struct hpre *hpre = container_of(file->debug, struct hpre, debug); 674 675 return &hpre->qm; 676 } 677 678 static u32 hpre_clear_enable_read(struct hpre_debugfs_file *file) 679 { 680 struct hisi_qm *qm = hpre_file_to_qm(file); 681 682 return readl(qm->io_base + HPRE_CTRL_CNT_CLR_CE) & 683 HPRE_CTRL_CNT_CLR_CE_BIT; 684 } 685 686 static int hpre_clear_enable_write(struct hpre_debugfs_file *file, u32 val) 687 { 688 struct hisi_qm *qm = hpre_file_to_qm(file); 689 u32 tmp; 690 691 if (val != 1 && val != 0) 692 return -EINVAL; 693 694 tmp = (readl(qm->io_base + HPRE_CTRL_CNT_CLR_CE) & 695 ~HPRE_CTRL_CNT_CLR_CE_BIT) | val; 696 writel(tmp, qm->io_base + HPRE_CTRL_CNT_CLR_CE); 697 698 return 0; 699 } 700 701 static u32 hpre_cluster_inqry_read(struct hpre_debugfs_file *file) 702 { 703 struct hisi_qm *qm = hpre_file_to_qm(file); 704 int cluster_index = file->index - HPRE_CLUSTER_CTRL; 705 unsigned long offset = HPRE_CLSTR_BASE + 706 cluster_index * HPRE_CLSTR_ADDR_INTRVL; 707 708 return readl(qm->io_base + offset + HPRE_CLSTR_ADDR_INQRY_RSLT); 709 } 710 711 static int hpre_cluster_inqry_write(struct hpre_debugfs_file *file, u32 val) 712 { 713 struct hisi_qm *qm = hpre_file_to_qm(file); 714 int cluster_index = file->index - HPRE_CLUSTER_CTRL; 715 unsigned long offset = HPRE_CLSTR_BASE + cluster_index * 716 HPRE_CLSTR_ADDR_INTRVL; 717 718 writel(val, qm->io_base + offset + HPRE_CLUSTER_INQURY); 719 720 return 0; 721 } 722 723 static ssize_t hpre_ctrl_debug_read(struct file *filp, char __user *buf, 724 size_t count, loff_t *pos) 725 { 726 struct hpre_debugfs_file *file = filp->private_data; 727 struct hisi_qm *qm = hpre_file_to_qm(file); 728 char tbuf[HPRE_DBGFS_VAL_MAX_LEN]; 729 u32 val; 730 int ret; 731 732 ret = hisi_qm_get_dfx_access(qm); 733 if (ret) 734 return ret; 735 736 spin_lock_irq(&file->lock); 737 switch (file->type) { 738 case HPRE_CLEAR_ENABLE: 739 val = hpre_clear_enable_read(file); 740 break; 741 case HPRE_CLUSTER_CTRL: 742 val = hpre_cluster_inqry_read(file); 743 break; 744 default: 745 goto err_input; 746 } 747 spin_unlock_irq(&file->lock); 748 749 hisi_qm_put_dfx_access(qm); 750 ret = snprintf(tbuf, HPRE_DBGFS_VAL_MAX_LEN, "%u\n", val); 751 return simple_read_from_buffer(buf, count, pos, tbuf, ret); 752 753 err_input: 754 spin_unlock_irq(&file->lock); 755 hisi_qm_put_dfx_access(qm); 756 return -EINVAL; 757 } 758 759 static ssize_t hpre_ctrl_debug_write(struct file *filp, const char __user *buf, 760 size_t count, loff_t *pos) 761 { 762 struct hpre_debugfs_file *file = filp->private_data; 763 struct hisi_qm *qm = hpre_file_to_qm(file); 764 char tbuf[HPRE_DBGFS_VAL_MAX_LEN]; 765 unsigned long val; 766 int len, ret; 767 768 if (*pos != 0) 769 return 0; 770 771 if (count >= HPRE_DBGFS_VAL_MAX_LEN) 772 return -ENOSPC; 773 774 len = simple_write_to_buffer(tbuf, HPRE_DBGFS_VAL_MAX_LEN - 1, 775 pos, buf, count); 776 if (len < 0) 777 return len; 778 779 tbuf[len] = '\0'; 780 if (kstrtoul(tbuf, 0, &val)) 781 return -EFAULT; 782 783 ret = hisi_qm_get_dfx_access(qm); 784 if (ret) 785 return ret; 786 787 spin_lock_irq(&file->lock); 788 switch (file->type) { 789 case HPRE_CLEAR_ENABLE: 790 ret = hpre_clear_enable_write(file, val); 791 if (ret) 792 goto err_input; 793 break; 794 case HPRE_CLUSTER_CTRL: 795 ret = hpre_cluster_inqry_write(file, val); 796 if (ret) 797 goto err_input; 798 break; 799 default: 800 ret = -EINVAL; 801 goto err_input; 802 } 803 804 ret = count; 805 806 err_input: 807 spin_unlock_irq(&file->lock); 808 hisi_qm_put_dfx_access(qm); 809 return ret; 810 } 811 812 static const struct file_operations hpre_ctrl_debug_fops = { 813 .owner = THIS_MODULE, 814 .open = simple_open, 815 .read = hpre_ctrl_debug_read, 816 .write = hpre_ctrl_debug_write, 817 }; 818 819 static int hpre_debugfs_atomic64_get(void *data, u64 *val) 820 { 821 struct hpre_dfx *dfx_item = data; 822 823 *val = atomic64_read(&dfx_item->value); 824 825 return 0; 826 } 827 828 static int hpre_debugfs_atomic64_set(void *data, u64 val) 829 { 830 struct hpre_dfx *dfx_item = data; 831 struct hpre_dfx *hpre_dfx = NULL; 832 833 if (dfx_item->type == HPRE_OVERTIME_THRHLD) { 834 hpre_dfx = dfx_item - HPRE_OVERTIME_THRHLD; 835 atomic64_set(&hpre_dfx[HPRE_OVER_THRHLD_CNT].value, 0); 836 } else if (val) { 837 return -EINVAL; 838 } 839 840 atomic64_set(&dfx_item->value, val); 841 842 return 0; 843 } 844 845 DEFINE_DEBUGFS_ATTRIBUTE(hpre_atomic64_ops, hpre_debugfs_atomic64_get, 846 hpre_debugfs_atomic64_set, "%llu\n"); 847 848 static int hpre_create_debugfs_file(struct hisi_qm *qm, struct dentry *dir, 849 enum hpre_ctrl_dbgfs_file type, int indx) 850 { 851 struct hpre *hpre = container_of(qm, struct hpre, qm); 852 struct hpre_debug *dbg = &hpre->debug; 853 struct dentry *file_dir; 854 855 if (dir) 856 file_dir = dir; 857 else 858 file_dir = qm->debug.debug_root; 859 860 if (type >= HPRE_DEBUG_FILE_NUM) 861 return -EINVAL; 862 863 spin_lock_init(&dbg->files[indx].lock); 864 dbg->files[indx].debug = dbg; 865 dbg->files[indx].type = type; 866 dbg->files[indx].index = indx; 867 debugfs_create_file(hpre_debug_file_name[type], 0600, file_dir, 868 dbg->files + indx, &hpre_ctrl_debug_fops); 869 870 return 0; 871 } 872 873 static int hpre_pf_comm_regs_debugfs_init(struct hisi_qm *qm) 874 { 875 struct device *dev = &qm->pdev->dev; 876 struct debugfs_regset32 *regset; 877 878 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 879 if (!regset) 880 return -ENOMEM; 881 882 regset->regs = hpre_com_dfx_regs; 883 regset->nregs = ARRAY_SIZE(hpre_com_dfx_regs); 884 regset->base = qm->io_base; 885 regset->dev = dev; 886 887 debugfs_create_file("regs", 0444, qm->debug.debug_root, 888 regset, &hpre_com_regs_fops); 889 890 return 0; 891 } 892 893 static int hpre_cluster_debugfs_init(struct hisi_qm *qm) 894 { 895 u8 clusters_num = hpre_cluster_num(qm); 896 struct device *dev = &qm->pdev->dev; 897 char buf[HPRE_DBGFS_VAL_MAX_LEN]; 898 struct debugfs_regset32 *regset; 899 struct dentry *tmp_d; 900 int i, ret; 901 902 for (i = 0; i < clusters_num; i++) { 903 ret = snprintf(buf, HPRE_DBGFS_VAL_MAX_LEN, "cluster%d", i); 904 if (ret < 0) 905 return -EINVAL; 906 tmp_d = debugfs_create_dir(buf, qm->debug.debug_root); 907 908 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 909 if (!regset) 910 return -ENOMEM; 911 912 regset->regs = hpre_cluster_dfx_regs; 913 regset->nregs = ARRAY_SIZE(hpre_cluster_dfx_regs); 914 regset->base = qm->io_base + hpre_cluster_offsets[i]; 915 regset->dev = dev; 916 917 debugfs_create_file("regs", 0444, tmp_d, regset, 918 &hpre_cluster_regs_fops); 919 ret = hpre_create_debugfs_file(qm, tmp_d, HPRE_CLUSTER_CTRL, 920 i + HPRE_CLUSTER_CTRL); 921 if (ret) 922 return ret; 923 } 924 925 return 0; 926 } 927 928 static int hpre_ctrl_debug_init(struct hisi_qm *qm) 929 { 930 int ret; 931 932 ret = hpre_create_debugfs_file(qm, NULL, HPRE_CLEAR_ENABLE, 933 HPRE_CLEAR_ENABLE); 934 if (ret) 935 return ret; 936 937 ret = hpre_pf_comm_regs_debugfs_init(qm); 938 if (ret) 939 return ret; 940 941 return hpre_cluster_debugfs_init(qm); 942 } 943 944 static void hpre_dfx_debug_init(struct hisi_qm *qm) 945 { 946 struct dfx_diff_registers *hpre_regs = qm->debug.acc_diff_regs; 947 struct hpre *hpre = container_of(qm, struct hpre, qm); 948 struct hpre_dfx *dfx = hpre->debug.dfx; 949 struct dentry *parent; 950 int i; 951 952 parent = debugfs_create_dir("hpre_dfx", qm->debug.debug_root); 953 for (i = 0; i < HPRE_DFX_FILE_NUM; i++) { 954 dfx[i].type = i; 955 debugfs_create_file(hpre_dfx_files[i], 0644, parent, &dfx[i], 956 &hpre_atomic64_ops); 957 } 958 959 if (qm->fun_type == QM_HW_PF && hpre_regs) 960 debugfs_create_file("diff_regs", 0444, parent, 961 qm, &hpre_diff_regs_fops); 962 } 963 964 static int hpre_debugfs_init(struct hisi_qm *qm) 965 { 966 struct device *dev = &qm->pdev->dev; 967 int ret; 968 969 qm->debug.debug_root = debugfs_create_dir(dev_name(dev), 970 hpre_debugfs_root); 971 972 qm->debug.sqe_mask_offset = HPRE_SQE_MASK_OFFSET; 973 qm->debug.sqe_mask_len = HPRE_SQE_MASK_LEN; 974 ret = hisi_qm_diff_regs_init(qm, hpre_diff_regs, 975 ARRAY_SIZE(hpre_diff_regs)); 976 if (ret) { 977 dev_warn(dev, "Failed to init HPRE diff regs!\n"); 978 goto debugfs_remove; 979 } 980 981 hisi_qm_debug_init(qm); 982 983 if (qm->pdev->device == PCI_DEVICE_ID_HUAWEI_HPRE_PF) { 984 ret = hpre_ctrl_debug_init(qm); 985 if (ret) 986 goto failed_to_create; 987 } 988 989 hpre_dfx_debug_init(qm); 990 991 return 0; 992 993 failed_to_create: 994 hisi_qm_diff_regs_uninit(qm, ARRAY_SIZE(hpre_diff_regs)); 995 debugfs_remove: 996 debugfs_remove_recursive(qm->debug.debug_root); 997 return ret; 998 } 999 1000 static void hpre_debugfs_exit(struct hisi_qm *qm) 1001 { 1002 hisi_qm_diff_regs_uninit(qm, ARRAY_SIZE(hpre_diff_regs)); 1003 1004 debugfs_remove_recursive(qm->debug.debug_root); 1005 } 1006 1007 static int hpre_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) 1008 { 1009 if (pdev->revision == QM_HW_V1) { 1010 pci_warn(pdev, "HPRE version 1 is not supported!\n"); 1011 return -EINVAL; 1012 } 1013 1014 if (pdev->revision >= QM_HW_V3) 1015 qm->algs = "rsa\ndh\necdh\nx25519\nx448\necdsa\nsm2"; 1016 else 1017 qm->algs = "rsa\ndh"; 1018 qm->mode = uacce_mode; 1019 qm->pdev = pdev; 1020 qm->ver = pdev->revision; 1021 qm->sqe_size = HPRE_SQE_SIZE; 1022 qm->dev_name = hpre_name; 1023 1024 qm->fun_type = (pdev->device == PCI_DEVICE_ID_HUAWEI_HPRE_PF) ? 1025 QM_HW_PF : QM_HW_VF; 1026 if (qm->fun_type == QM_HW_PF) { 1027 qm->qp_base = HPRE_PF_DEF_Q_BASE; 1028 qm->qp_num = pf_q_num; 1029 qm->debug.curr_qm_qp_num = pf_q_num; 1030 qm->qm_list = &hpre_devices; 1031 } 1032 1033 return hisi_qm_init(qm); 1034 } 1035 1036 static int hpre_show_last_regs_init(struct hisi_qm *qm) 1037 { 1038 int cluster_dfx_regs_num = ARRAY_SIZE(hpre_cluster_dfx_regs); 1039 int com_dfx_regs_num = ARRAY_SIZE(hpre_com_dfx_regs); 1040 u8 clusters_num = hpre_cluster_num(qm); 1041 struct qm_debug *debug = &qm->debug; 1042 void __iomem *io_base; 1043 int i, j, idx; 1044 1045 debug->last_words = kcalloc(cluster_dfx_regs_num * clusters_num + 1046 com_dfx_regs_num, sizeof(unsigned int), GFP_KERNEL); 1047 if (!debug->last_words) 1048 return -ENOMEM; 1049 1050 for (i = 0; i < com_dfx_regs_num; i++) 1051 debug->last_words[i] = readl_relaxed(qm->io_base + 1052 hpre_com_dfx_regs[i].offset); 1053 1054 for (i = 0; i < clusters_num; i++) { 1055 io_base = qm->io_base + hpre_cluster_offsets[i]; 1056 for (j = 0; j < cluster_dfx_regs_num; j++) { 1057 idx = com_dfx_regs_num + i * cluster_dfx_regs_num + j; 1058 debug->last_words[idx] = readl_relaxed( 1059 io_base + hpre_cluster_dfx_regs[j].offset); 1060 } 1061 } 1062 1063 return 0; 1064 } 1065 1066 static void hpre_show_last_regs_uninit(struct hisi_qm *qm) 1067 { 1068 struct qm_debug *debug = &qm->debug; 1069 1070 if (qm->fun_type == QM_HW_VF || !debug->last_words) 1071 return; 1072 1073 kfree(debug->last_words); 1074 debug->last_words = NULL; 1075 } 1076 1077 static void hpre_show_last_dfx_regs(struct hisi_qm *qm) 1078 { 1079 int cluster_dfx_regs_num = ARRAY_SIZE(hpre_cluster_dfx_regs); 1080 int com_dfx_regs_num = ARRAY_SIZE(hpre_com_dfx_regs); 1081 u8 clusters_num = hpre_cluster_num(qm); 1082 struct qm_debug *debug = &qm->debug; 1083 struct pci_dev *pdev = qm->pdev; 1084 void __iomem *io_base; 1085 int i, j, idx; 1086 u32 val; 1087 1088 if (qm->fun_type == QM_HW_VF || !debug->last_words) 1089 return; 1090 1091 /* dumps last word of the debugging registers during controller reset */ 1092 for (i = 0; i < com_dfx_regs_num; i++) { 1093 val = readl_relaxed(qm->io_base + hpre_com_dfx_regs[i].offset); 1094 if (debug->last_words[i] != val) 1095 pci_info(pdev, "Common_core:%s \t= 0x%08x => 0x%08x\n", 1096 hpre_com_dfx_regs[i].name, debug->last_words[i], val); 1097 } 1098 1099 for (i = 0; i < clusters_num; i++) { 1100 io_base = qm->io_base + hpre_cluster_offsets[i]; 1101 for (j = 0; j < cluster_dfx_regs_num; j++) { 1102 val = readl_relaxed(io_base + 1103 hpre_cluster_dfx_regs[j].offset); 1104 idx = com_dfx_regs_num + i * cluster_dfx_regs_num + j; 1105 if (debug->last_words[idx] != val) 1106 pci_info(pdev, "cluster-%d:%s \t= 0x%08x => 0x%08x\n", 1107 i, hpre_cluster_dfx_regs[j].name, debug->last_words[idx], val); 1108 } 1109 } 1110 } 1111 1112 static void hpre_log_hw_error(struct hisi_qm *qm, u32 err_sts) 1113 { 1114 const struct hpre_hw_error *err = hpre_hw_errors; 1115 struct device *dev = &qm->pdev->dev; 1116 1117 while (err->msg) { 1118 if (err->int_msk & err_sts) 1119 dev_warn(dev, "%s [error status=0x%x] found\n", 1120 err->msg, err->int_msk); 1121 err++; 1122 } 1123 } 1124 1125 static u32 hpre_get_hw_err_status(struct hisi_qm *qm) 1126 { 1127 return readl(qm->io_base + HPRE_INT_STATUS); 1128 } 1129 1130 static void hpre_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts) 1131 { 1132 writel(err_sts, qm->io_base + HPRE_HAC_SOURCE_INT); 1133 } 1134 1135 static void hpre_open_axi_master_ooo(struct hisi_qm *qm) 1136 { 1137 u32 value; 1138 1139 value = readl(qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB); 1140 writel(value & ~HPRE_AM_OOO_SHUTDOWN_ENABLE, 1141 qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB); 1142 writel(value | HPRE_AM_OOO_SHUTDOWN_ENABLE, 1143 qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB); 1144 } 1145 1146 static void hpre_err_info_init(struct hisi_qm *qm) 1147 { 1148 struct hisi_qm_err_info *err_info = &qm->err_info; 1149 1150 err_info->ce = QM_BASE_CE; 1151 err_info->fe = 0; 1152 err_info->ecc_2bits_mask = HPRE_CORE_ECC_2BIT_ERR | 1153 HPRE_OOO_ECC_2BIT_ERR; 1154 err_info->dev_ce_mask = HPRE_HAC_RAS_CE_ENABLE; 1155 err_info->msi_wr_port = HPRE_WR_MSI_PORT; 1156 err_info->acpi_rst = "HRST"; 1157 err_info->nfe = QM_BASE_NFE | QM_ACC_DO_TASK_TIMEOUT; 1158 } 1159 1160 static const struct hisi_qm_err_ini hpre_err_ini = { 1161 .hw_init = hpre_set_user_domain_and_cache, 1162 .hw_err_enable = hpre_hw_error_enable, 1163 .hw_err_disable = hpre_hw_error_disable, 1164 .get_dev_hw_err_status = hpre_get_hw_err_status, 1165 .clear_dev_hw_err_status = hpre_clear_hw_err_status, 1166 .log_dev_hw_err = hpre_log_hw_error, 1167 .open_axi_master_ooo = hpre_open_axi_master_ooo, 1168 .open_sva_prefetch = hpre_open_sva_prefetch, 1169 .close_sva_prefetch = hpre_close_sva_prefetch, 1170 .show_last_dfx_regs = hpre_show_last_dfx_regs, 1171 .err_info_init = hpre_err_info_init, 1172 }; 1173 1174 static int hpre_pf_probe_init(struct hpre *hpre) 1175 { 1176 struct hisi_qm *qm = &hpre->qm; 1177 int ret; 1178 1179 ret = hpre_set_user_domain_and_cache(qm); 1180 if (ret) 1181 return ret; 1182 1183 hpre_open_sva_prefetch(qm); 1184 1185 qm->err_ini = &hpre_err_ini; 1186 qm->err_ini->err_info_init(qm); 1187 hisi_qm_dev_err_init(qm); 1188 ret = hpre_show_last_regs_init(qm); 1189 if (ret) 1190 pci_err(qm->pdev, "Failed to init last word regs!\n"); 1191 1192 return ret; 1193 } 1194 1195 static int hpre_probe_init(struct hpre *hpre) 1196 { 1197 u32 type_rate = HPRE_SHAPER_TYPE_RATE; 1198 struct hisi_qm *qm = &hpre->qm; 1199 int ret; 1200 1201 if (qm->fun_type == QM_HW_PF) { 1202 ret = hpre_pf_probe_init(hpre); 1203 if (ret) 1204 return ret; 1205 /* Enable shaper type 0 */ 1206 if (qm->ver >= QM_HW_V3) { 1207 type_rate |= QM_SHAPER_ENABLE; 1208 qm->type_rate = type_rate; 1209 } 1210 } 1211 1212 return 0; 1213 } 1214 1215 static int hpre_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1216 { 1217 struct hisi_qm *qm; 1218 struct hpre *hpre; 1219 int ret; 1220 1221 hpre = devm_kzalloc(&pdev->dev, sizeof(*hpre), GFP_KERNEL); 1222 if (!hpre) 1223 return -ENOMEM; 1224 1225 qm = &hpre->qm; 1226 ret = hpre_qm_init(qm, pdev); 1227 if (ret) { 1228 pci_err(pdev, "Failed to init HPRE QM (%d)!\n", ret); 1229 return ret; 1230 } 1231 1232 ret = hpre_probe_init(hpre); 1233 if (ret) { 1234 pci_err(pdev, "Failed to probe (%d)!\n", ret); 1235 goto err_with_qm_init; 1236 } 1237 1238 ret = hisi_qm_start(qm); 1239 if (ret) 1240 goto err_with_err_init; 1241 1242 ret = hpre_debugfs_init(qm); 1243 if (ret) 1244 dev_warn(&pdev->dev, "init debugfs fail!\n"); 1245 1246 ret = hisi_qm_alg_register(qm, &hpre_devices); 1247 if (ret < 0) { 1248 pci_err(pdev, "fail to register algs to crypto!\n"); 1249 goto err_with_qm_start; 1250 } 1251 1252 if (qm->uacce) { 1253 ret = uacce_register(qm->uacce); 1254 if (ret) { 1255 pci_err(pdev, "failed to register uacce (%d)!\n", ret); 1256 goto err_with_alg_register; 1257 } 1258 } 1259 1260 if (qm->fun_type == QM_HW_PF && vfs_num) { 1261 ret = hisi_qm_sriov_enable(pdev, vfs_num); 1262 if (ret < 0) 1263 goto err_with_alg_register; 1264 } 1265 1266 hisi_qm_pm_init(qm); 1267 1268 return 0; 1269 1270 err_with_alg_register: 1271 hisi_qm_alg_unregister(qm, &hpre_devices); 1272 1273 err_with_qm_start: 1274 hpre_debugfs_exit(qm); 1275 hisi_qm_stop(qm, QM_NORMAL); 1276 1277 err_with_err_init: 1278 hpre_show_last_regs_uninit(qm); 1279 hisi_qm_dev_err_uninit(qm); 1280 1281 err_with_qm_init: 1282 hisi_qm_uninit(qm); 1283 1284 return ret; 1285 } 1286 1287 static void hpre_remove(struct pci_dev *pdev) 1288 { 1289 struct hisi_qm *qm = pci_get_drvdata(pdev); 1290 int ret; 1291 1292 hisi_qm_pm_uninit(qm); 1293 hisi_qm_wait_task_finish(qm, &hpre_devices); 1294 hisi_qm_alg_unregister(qm, &hpre_devices); 1295 if (qm->fun_type == QM_HW_PF && qm->vfs_num) { 1296 ret = hisi_qm_sriov_disable(pdev, true); 1297 if (ret) { 1298 pci_err(pdev, "Disable SRIOV fail!\n"); 1299 return; 1300 } 1301 } 1302 1303 hpre_debugfs_exit(qm); 1304 hisi_qm_stop(qm, QM_NORMAL); 1305 1306 if (qm->fun_type == QM_HW_PF) { 1307 hpre_cnt_regs_clear(qm); 1308 qm->debug.curr_qm_qp_num = 0; 1309 hpre_show_last_regs_uninit(qm); 1310 hisi_qm_dev_err_uninit(qm); 1311 } 1312 1313 hisi_qm_uninit(qm); 1314 } 1315 1316 static const struct dev_pm_ops hpre_pm_ops = { 1317 SET_RUNTIME_PM_OPS(hisi_qm_suspend, hisi_qm_resume, NULL) 1318 }; 1319 1320 static const struct pci_error_handlers hpre_err_handler = { 1321 .error_detected = hisi_qm_dev_err_detected, 1322 .slot_reset = hisi_qm_dev_slot_reset, 1323 .reset_prepare = hisi_qm_reset_prepare, 1324 .reset_done = hisi_qm_reset_done, 1325 }; 1326 1327 static struct pci_driver hpre_pci_driver = { 1328 .name = hpre_name, 1329 .id_table = hpre_dev_ids, 1330 .probe = hpre_probe, 1331 .remove = hpre_remove, 1332 .sriov_configure = IS_ENABLED(CONFIG_PCI_IOV) ? 1333 hisi_qm_sriov_configure : NULL, 1334 .err_handler = &hpre_err_handler, 1335 .shutdown = hisi_qm_dev_shutdown, 1336 .driver.pm = &hpre_pm_ops, 1337 }; 1338 1339 struct pci_driver *hisi_hpre_get_pf_driver(void) 1340 { 1341 return &hpre_pci_driver; 1342 } 1343 EXPORT_SYMBOL_GPL(hisi_hpre_get_pf_driver); 1344 1345 static void hpre_register_debugfs(void) 1346 { 1347 if (!debugfs_initialized()) 1348 return; 1349 1350 hpre_debugfs_root = debugfs_create_dir(hpre_name, NULL); 1351 } 1352 1353 static void hpre_unregister_debugfs(void) 1354 { 1355 debugfs_remove_recursive(hpre_debugfs_root); 1356 } 1357 1358 static int __init hpre_init(void) 1359 { 1360 int ret; 1361 1362 hisi_qm_init_list(&hpre_devices); 1363 hpre_register_debugfs(); 1364 1365 ret = pci_register_driver(&hpre_pci_driver); 1366 if (ret) { 1367 hpre_unregister_debugfs(); 1368 pr_err("hpre: can't register hisi hpre driver.\n"); 1369 } 1370 1371 return ret; 1372 } 1373 1374 static void __exit hpre_exit(void) 1375 { 1376 pci_unregister_driver(&hpre_pci_driver); 1377 hpre_unregister_debugfs(); 1378 } 1379 1380 module_init(hpre_init); 1381 module_exit(hpre_exit); 1382 1383 MODULE_LICENSE("GPL v2"); 1384 MODULE_AUTHOR("Zaibo Xu <xuzaibo@huawei.com>"); 1385 MODULE_AUTHOR("Meng Yu <yumeng18@huawei.com>"); 1386 MODULE_DESCRIPTION("Driver for HiSilicon HPRE accelerator"); 1387