1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018-2019 HiSilicon Limited. */ 3 #include <linux/acpi.h> 4 #include <linux/aer.h> 5 #include <linux/bitops.h> 6 #include <linux/debugfs.h> 7 #include <linux/init.h> 8 #include <linux/io.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/topology.h> 13 #include <linux/uacce.h> 14 #include "hpre.h" 15 16 #define HPRE_QUEUE_NUM_V2 1024 17 #define HPRE_QM_ABNML_INT_MASK 0x100004 18 #define HPRE_CTRL_CNT_CLR_CE_BIT BIT(0) 19 #define HPRE_COMM_CNT_CLR_CE 0x0 20 #define HPRE_CTRL_CNT_CLR_CE 0x301000 21 #define HPRE_FSM_MAX_CNT 0x301008 22 #define HPRE_VFG_AXQOS 0x30100c 23 #define HPRE_VFG_AXCACHE 0x301010 24 #define HPRE_RDCHN_INI_CFG 0x301014 25 #define HPRE_AWUSR_FP_CFG 0x301018 26 #define HPRE_BD_ENDIAN 0x301020 27 #define HPRE_ECC_BYPASS 0x301024 28 #define HPRE_RAS_WIDTH_CFG 0x301028 29 #define HPRE_POISON_BYPASS 0x30102c 30 #define HPRE_BD_ARUSR_CFG 0x301030 31 #define HPRE_BD_AWUSR_CFG 0x301034 32 #define HPRE_TYPES_ENB 0x301038 33 #define HPRE_RSA_ENB BIT(0) 34 #define HPRE_ECC_ENB BIT(1) 35 #define HPRE_DATA_RUSER_CFG 0x30103c 36 #define HPRE_DATA_WUSER_CFG 0x301040 37 #define HPRE_INT_MASK 0x301400 38 #define HPRE_INT_STATUS 0x301800 39 #define HPRE_CORE_INT_ENABLE 0 40 #define HPRE_CORE_INT_DISABLE 0x003fffff 41 #define HPRE_RDCHN_INI_ST 0x301a00 42 #define HPRE_CLSTR_BASE 0x302000 43 #define HPRE_CORE_EN_OFFSET 0x04 44 #define HPRE_CORE_INI_CFG_OFFSET 0x20 45 #define HPRE_CORE_INI_STATUS_OFFSET 0x80 46 #define HPRE_CORE_HTBT_WARN_OFFSET 0x8c 47 #define HPRE_CORE_IS_SCHD_OFFSET 0x90 48 49 #define HPRE_RAS_CE_ENB 0x301410 50 #define HPRE_HAC_RAS_CE_ENABLE (BIT(0) | BIT(22) | BIT(23)) 51 #define HPRE_RAS_NFE_ENB 0x301414 52 #define HPRE_HAC_RAS_NFE_ENABLE 0x3ffffe 53 #define HPRE_RAS_FE_ENB 0x301418 54 #define HPRE_HAC_RAS_FE_ENABLE 0 55 56 #define HPRE_CORE_ENB (HPRE_CLSTR_BASE + HPRE_CORE_EN_OFFSET) 57 #define HPRE_CORE_INI_CFG (HPRE_CLSTR_BASE + HPRE_CORE_INI_CFG_OFFSET) 58 #define HPRE_CORE_INI_STATUS (HPRE_CLSTR_BASE + HPRE_CORE_INI_STATUS_OFFSET) 59 #define HPRE_HAC_ECC1_CNT 0x301a04 60 #define HPRE_HAC_ECC2_CNT 0x301a08 61 #define HPRE_HAC_INT_STATUS 0x301800 62 #define HPRE_HAC_SOURCE_INT 0x301600 63 #define HPRE_CLSTR_ADDR_INTRVL 0x1000 64 #define HPRE_CLUSTER_INQURY 0x100 65 #define HPRE_CLSTR_ADDR_INQRY_RSLT 0x104 66 #define HPRE_TIMEOUT_ABNML_BIT 6 67 #define HPRE_PASID_EN_BIT 9 68 #define HPRE_REG_RD_INTVRL_US 10 69 #define HPRE_REG_RD_TMOUT_US 1000 70 #define HPRE_DBGFS_VAL_MAX_LEN 20 71 #define HPRE_PCI_DEVICE_ID 0xa258 72 #define HPRE_PCI_VF_DEVICE_ID 0xa259 73 #define HPRE_ADDR(qm, offset) ((qm)->io_base + (offset)) 74 #define HPRE_QM_USR_CFG_MASK 0xfffffffe 75 #define HPRE_QM_AXI_CFG_MASK 0xffff 76 #define HPRE_QM_VFG_AX_MASK 0xff 77 #define HPRE_BD_USR_MASK 0x3 78 #define HPRE_CLUSTER_CORE_MASK_V2 0xf 79 #define HPRE_CLUSTER_CORE_MASK_V3 0xff 80 81 #define HPRE_AM_OOO_SHUTDOWN_ENB 0x301044 82 #define HPRE_AM_OOO_SHUTDOWN_ENABLE BIT(0) 83 #define HPRE_WR_MSI_PORT BIT(2) 84 85 #define HPRE_CORE_ECC_2BIT_ERR BIT(1) 86 #define HPRE_OOO_ECC_2BIT_ERR BIT(5) 87 88 #define HPRE_QM_BME_FLR BIT(7) 89 #define HPRE_QM_PM_FLR BIT(11) 90 #define HPRE_QM_SRIOV_FLR BIT(12) 91 92 #define HPRE_CLUSTERS_NUM(qm) \ 93 (((qm)->ver >= QM_HW_V3) ? HPRE_CLUSTERS_NUM_V3 : HPRE_CLUSTERS_NUM_V2) 94 #define HPRE_CLUSTER_CORE_MASK(qm) \ 95 (((qm)->ver >= QM_HW_V3) ? HPRE_CLUSTER_CORE_MASK_V3 :\ 96 HPRE_CLUSTER_CORE_MASK_V2) 97 #define HPRE_VIA_MSI_DSM 1 98 #define HPRE_SQE_MASK_OFFSET 8 99 #define HPRE_SQE_MASK_LEN 24 100 101 static const char hpre_name[] = "hisi_hpre"; 102 static struct dentry *hpre_debugfs_root; 103 static const struct pci_device_id hpre_dev_ids[] = { 104 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HPRE_PCI_DEVICE_ID) }, 105 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HPRE_PCI_VF_DEVICE_ID) }, 106 { 0, } 107 }; 108 109 MODULE_DEVICE_TABLE(pci, hpre_dev_ids); 110 111 struct hpre_hw_error { 112 u32 int_msk; 113 const char *msg; 114 }; 115 116 static struct hisi_qm_list hpre_devices = { 117 .register_to_crypto = hpre_algs_register, 118 .unregister_from_crypto = hpre_algs_unregister, 119 }; 120 121 static const char * const hpre_debug_file_name[] = { 122 [HPRE_CURRENT_QM] = "current_qm", 123 [HPRE_CLEAR_ENABLE] = "rdclr_en", 124 [HPRE_CLUSTER_CTRL] = "cluster_ctrl", 125 }; 126 127 static const struct hpre_hw_error hpre_hw_errors[] = { 128 { .int_msk = BIT(0), .msg = "core_ecc_1bit_err_int_set" }, 129 { .int_msk = BIT(1), .msg = "core_ecc_2bit_err_int_set" }, 130 { .int_msk = BIT(2), .msg = "dat_wb_poison_int_set" }, 131 { .int_msk = BIT(3), .msg = "dat_rd_poison_int_set" }, 132 { .int_msk = BIT(4), .msg = "bd_rd_poison_int_set" }, 133 { .int_msk = BIT(5), .msg = "ooo_ecc_2bit_err_int_set" }, 134 { .int_msk = BIT(6), .msg = "cluster1_shb_timeout_int_set" }, 135 { .int_msk = BIT(7), .msg = "cluster2_shb_timeout_int_set" }, 136 { .int_msk = BIT(8), .msg = "cluster3_shb_timeout_int_set" }, 137 { .int_msk = BIT(9), .msg = "cluster4_shb_timeout_int_set" }, 138 { .int_msk = GENMASK(15, 10), .msg = "ooo_rdrsp_err_int_set" }, 139 { .int_msk = GENMASK(21, 16), .msg = "ooo_wrrsp_err_int_set" }, 140 { .int_msk = BIT(22), .msg = "pt_rng_timeout_int_set"}, 141 { .int_msk = BIT(23), .msg = "sva_fsm_timeout_int_set"}, 142 { 143 /* sentinel */ 144 } 145 }; 146 147 static const u64 hpre_cluster_offsets[] = { 148 [HPRE_CLUSTER0] = 149 HPRE_CLSTR_BASE + HPRE_CLUSTER0 * HPRE_CLSTR_ADDR_INTRVL, 150 [HPRE_CLUSTER1] = 151 HPRE_CLSTR_BASE + HPRE_CLUSTER1 * HPRE_CLSTR_ADDR_INTRVL, 152 [HPRE_CLUSTER2] = 153 HPRE_CLSTR_BASE + HPRE_CLUSTER2 * HPRE_CLSTR_ADDR_INTRVL, 154 [HPRE_CLUSTER3] = 155 HPRE_CLSTR_BASE + HPRE_CLUSTER3 * HPRE_CLSTR_ADDR_INTRVL, 156 }; 157 158 static const struct debugfs_reg32 hpre_cluster_dfx_regs[] = { 159 {"CORES_EN_STATUS ", HPRE_CORE_EN_OFFSET}, 160 {"CORES_INI_CFG ", HPRE_CORE_INI_CFG_OFFSET}, 161 {"CORES_INI_STATUS ", HPRE_CORE_INI_STATUS_OFFSET}, 162 {"CORES_HTBT_WARN ", HPRE_CORE_HTBT_WARN_OFFSET}, 163 {"CORES_IS_SCHD ", HPRE_CORE_IS_SCHD_OFFSET}, 164 }; 165 166 static const struct debugfs_reg32 hpre_com_dfx_regs[] = { 167 {"READ_CLR_EN ", HPRE_CTRL_CNT_CLR_CE}, 168 {"AXQOS ", HPRE_VFG_AXQOS}, 169 {"AWUSR_CFG ", HPRE_AWUSR_FP_CFG}, 170 {"QM_ARUSR_MCFG1 ", QM_ARUSER_M_CFG_1}, 171 {"QM_AWUSR_MCFG1 ", QM_AWUSER_M_CFG_1}, 172 {"BD_ENDIAN ", HPRE_BD_ENDIAN}, 173 {"ECC_CHECK_CTRL ", HPRE_ECC_BYPASS}, 174 {"RAS_INT_WIDTH ", HPRE_RAS_WIDTH_CFG}, 175 {"POISON_BYPASS ", HPRE_POISON_BYPASS}, 176 {"BD_ARUSER ", HPRE_BD_ARUSR_CFG}, 177 {"BD_AWUSER ", HPRE_BD_AWUSR_CFG}, 178 {"DATA_ARUSER ", HPRE_DATA_RUSER_CFG}, 179 {"DATA_AWUSER ", HPRE_DATA_WUSER_CFG}, 180 {"INT_STATUS ", HPRE_INT_STATUS}, 181 }; 182 183 static const char *hpre_dfx_files[HPRE_DFX_FILE_NUM] = { 184 "send_cnt", 185 "recv_cnt", 186 "send_fail_cnt", 187 "send_busy_cnt", 188 "over_thrhld_cnt", 189 "overtime_thrhld", 190 "invalid_req_cnt" 191 }; 192 193 static const struct kernel_param_ops hpre_uacce_mode_ops = { 194 .set = uacce_mode_set, 195 .get = param_get_int, 196 }; 197 198 /* 199 * uacce_mode = 0 means hpre only register to crypto, 200 * uacce_mode = 1 means hpre both register to crypto and uacce. 201 */ 202 static u32 uacce_mode = UACCE_MODE_NOUACCE; 203 module_param_cb(uacce_mode, &hpre_uacce_mode_ops, &uacce_mode, 0444); 204 MODULE_PARM_DESC(uacce_mode, UACCE_MODE_DESC); 205 206 static int pf_q_num_set(const char *val, const struct kernel_param *kp) 207 { 208 return q_num_set(val, kp, HPRE_PCI_DEVICE_ID); 209 } 210 211 static const struct kernel_param_ops hpre_pf_q_num_ops = { 212 .set = pf_q_num_set, 213 .get = param_get_int, 214 }; 215 216 static u32 pf_q_num = HPRE_PF_DEF_Q_NUM; 217 module_param_cb(pf_q_num, &hpre_pf_q_num_ops, &pf_q_num, 0444); 218 MODULE_PARM_DESC(pf_q_num, "Number of queues in PF of CS(2-1024)"); 219 220 static const struct kernel_param_ops vfs_num_ops = { 221 .set = vfs_num_set, 222 .get = param_get_int, 223 }; 224 225 static u32 vfs_num; 226 module_param_cb(vfs_num, &vfs_num_ops, &vfs_num, 0444); 227 MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)"); 228 229 struct hisi_qp *hpre_create_qp(u8 type) 230 { 231 int node = cpu_to_node(smp_processor_id()); 232 struct hisi_qp *qp = NULL; 233 int ret; 234 235 if (type != HPRE_V2_ALG_TYPE && type != HPRE_V3_ECC_ALG_TYPE) 236 return NULL; 237 238 /* 239 * type: 0 - RSA/DH. algorithm supported in V2, 240 * 1 - ECC algorithm in V3. 241 */ 242 ret = hisi_qm_alloc_qps_node(&hpre_devices, 1, type, node, &qp); 243 if (!ret) 244 return qp; 245 246 return NULL; 247 } 248 249 static void hpre_pasid_enable(struct hisi_qm *qm) 250 { 251 u32 val; 252 253 val = readl_relaxed(qm->io_base + HPRE_DATA_RUSER_CFG); 254 val |= BIT(HPRE_PASID_EN_BIT); 255 writel_relaxed(val, qm->io_base + HPRE_DATA_RUSER_CFG); 256 val = readl_relaxed(qm->io_base + HPRE_DATA_WUSER_CFG); 257 val |= BIT(HPRE_PASID_EN_BIT); 258 writel_relaxed(val, qm->io_base + HPRE_DATA_WUSER_CFG); 259 } 260 261 static void hpre_pasid_disable(struct hisi_qm *qm) 262 { 263 u32 val; 264 265 val = readl_relaxed(qm->io_base + HPRE_DATA_RUSER_CFG); 266 val &= ~BIT(HPRE_PASID_EN_BIT); 267 writel_relaxed(val, qm->io_base + HPRE_DATA_RUSER_CFG); 268 val = readl_relaxed(qm->io_base + HPRE_DATA_WUSER_CFG); 269 val &= ~BIT(HPRE_PASID_EN_BIT); 270 writel_relaxed(val, qm->io_base + HPRE_DATA_WUSER_CFG); 271 } 272 273 static int hpre_cfg_by_dsm(struct hisi_qm *qm) 274 { 275 struct device *dev = &qm->pdev->dev; 276 union acpi_object *obj; 277 guid_t guid; 278 279 if (guid_parse("b06b81ab-0134-4a45-9b0c-483447b95fa7", &guid)) { 280 dev_err(dev, "Hpre GUID failed\n"); 281 return -EINVAL; 282 } 283 284 /* Switch over to MSI handling due to non-standard PCI implementation */ 285 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &guid, 286 0, HPRE_VIA_MSI_DSM, NULL); 287 if (!obj) { 288 dev_err(dev, "ACPI handle failed!\n"); 289 return -EIO; 290 } 291 292 ACPI_FREE(obj); 293 294 return 0; 295 } 296 297 static int hpre_set_cluster(struct hisi_qm *qm) 298 { 299 u32 cluster_core_mask = HPRE_CLUSTER_CORE_MASK(qm); 300 u8 clusters_num = HPRE_CLUSTERS_NUM(qm); 301 struct device *dev = &qm->pdev->dev; 302 unsigned long offset; 303 u32 val = 0; 304 int ret, i; 305 306 for (i = 0; i < clusters_num; i++) { 307 offset = i * HPRE_CLSTR_ADDR_INTRVL; 308 309 /* clusters initiating */ 310 writel(cluster_core_mask, 311 HPRE_ADDR(qm, offset + HPRE_CORE_ENB)); 312 writel(0x1, HPRE_ADDR(qm, offset + HPRE_CORE_INI_CFG)); 313 ret = readl_relaxed_poll_timeout(HPRE_ADDR(qm, offset + 314 HPRE_CORE_INI_STATUS), val, 315 ((val & cluster_core_mask) == 316 cluster_core_mask), 317 HPRE_REG_RD_INTVRL_US, 318 HPRE_REG_RD_TMOUT_US); 319 if (ret) { 320 dev_err(dev, 321 "cluster %d int st status timeout!\n", i); 322 return -ETIMEDOUT; 323 } 324 } 325 326 return 0; 327 } 328 329 /* 330 * For Kunpeng 920, we shoul disable FLR triggered by hardware (BME/PM/SRIOV). 331 * Or it may stay in D3 state when we bind and unbind hpre quickly, 332 * as it does FLR triggered by hardware. 333 */ 334 static void disable_flr_of_bme(struct hisi_qm *qm) 335 { 336 u32 val; 337 338 val = readl(HPRE_ADDR(qm, QM_PEH_AXUSER_CFG)); 339 val &= ~(HPRE_QM_BME_FLR | HPRE_QM_SRIOV_FLR); 340 val |= HPRE_QM_PM_FLR; 341 writel(val, HPRE_ADDR(qm, QM_PEH_AXUSER_CFG)); 342 writel(PEH_AXUSER_CFG_ENABLE, HPRE_ADDR(qm, QM_PEH_AXUSER_CFG_ENABLE)); 343 } 344 345 static int hpre_set_user_domain_and_cache(struct hisi_qm *qm) 346 { 347 struct device *dev = &qm->pdev->dev; 348 u32 val; 349 int ret; 350 351 writel(HPRE_QM_USR_CFG_MASK, HPRE_ADDR(qm, QM_ARUSER_M_CFG_ENABLE)); 352 writel(HPRE_QM_USR_CFG_MASK, HPRE_ADDR(qm, QM_AWUSER_M_CFG_ENABLE)); 353 writel_relaxed(HPRE_QM_AXI_CFG_MASK, HPRE_ADDR(qm, QM_AXI_M_CFG)); 354 355 /* HPRE need more time, we close this interrupt */ 356 val = readl_relaxed(HPRE_ADDR(qm, HPRE_QM_ABNML_INT_MASK)); 357 val |= BIT(HPRE_TIMEOUT_ABNML_BIT); 358 writel_relaxed(val, HPRE_ADDR(qm, HPRE_QM_ABNML_INT_MASK)); 359 360 if (qm->ver >= QM_HW_V3) 361 writel(HPRE_RSA_ENB | HPRE_ECC_ENB, 362 HPRE_ADDR(qm, HPRE_TYPES_ENB)); 363 else 364 writel(HPRE_RSA_ENB, HPRE_ADDR(qm, HPRE_TYPES_ENB)); 365 366 writel(HPRE_QM_VFG_AX_MASK, HPRE_ADDR(qm, HPRE_VFG_AXCACHE)); 367 writel(0x0, HPRE_ADDR(qm, HPRE_BD_ENDIAN)); 368 writel(0x0, HPRE_ADDR(qm, HPRE_INT_MASK)); 369 writel(0x0, HPRE_ADDR(qm, HPRE_POISON_BYPASS)); 370 writel(0x0, HPRE_ADDR(qm, HPRE_COMM_CNT_CLR_CE)); 371 writel(0x0, HPRE_ADDR(qm, HPRE_ECC_BYPASS)); 372 373 writel(HPRE_BD_USR_MASK, HPRE_ADDR(qm, HPRE_BD_ARUSR_CFG)); 374 writel(HPRE_BD_USR_MASK, HPRE_ADDR(qm, HPRE_BD_AWUSR_CFG)); 375 writel(0x1, HPRE_ADDR(qm, HPRE_RDCHN_INI_CFG)); 376 ret = readl_relaxed_poll_timeout(HPRE_ADDR(qm, HPRE_RDCHN_INI_ST), val, 377 val & BIT(0), 378 HPRE_REG_RD_INTVRL_US, 379 HPRE_REG_RD_TMOUT_US); 380 if (ret) { 381 dev_err(dev, "read rd channel timeout fail!\n"); 382 return -ETIMEDOUT; 383 } 384 385 ret = hpre_set_cluster(qm); 386 if (ret) 387 return -ETIMEDOUT; 388 389 /* This setting is only needed by Kunpeng 920. */ 390 if (qm->ver == QM_HW_V2) { 391 ret = hpre_cfg_by_dsm(qm); 392 if (ret) 393 dev_err(dev, "acpi_evaluate_dsm err.\n"); 394 395 disable_flr_of_bme(qm); 396 397 /* Enable data buffer pasid */ 398 if (qm->use_sva) 399 hpre_pasid_enable(qm); 400 } 401 402 return ret; 403 } 404 405 static void hpre_cnt_regs_clear(struct hisi_qm *qm) 406 { 407 u8 clusters_num = HPRE_CLUSTERS_NUM(qm); 408 unsigned long offset; 409 int i; 410 411 /* clear current_qm */ 412 writel(0x0, qm->io_base + QM_DFX_MB_CNT_VF); 413 writel(0x0, qm->io_base + QM_DFX_DB_CNT_VF); 414 415 /* clear clusterX/cluster_ctrl */ 416 for (i = 0; i < clusters_num; i++) { 417 offset = HPRE_CLSTR_BASE + i * HPRE_CLSTR_ADDR_INTRVL; 418 writel(0x0, qm->io_base + offset + HPRE_CLUSTER_INQURY); 419 } 420 421 /* clear rdclr_en */ 422 writel(0x0, qm->io_base + HPRE_CTRL_CNT_CLR_CE); 423 424 hisi_qm_debug_regs_clear(qm); 425 } 426 427 static void hpre_hw_error_disable(struct hisi_qm *qm) 428 { 429 u32 val; 430 431 /* disable hpre hw error interrupts */ 432 writel(HPRE_CORE_INT_DISABLE, qm->io_base + HPRE_INT_MASK); 433 434 /* disable HPRE block master OOO when m-bit error occur */ 435 val = readl(qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB); 436 val &= ~HPRE_AM_OOO_SHUTDOWN_ENABLE; 437 writel(val, qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB); 438 } 439 440 static void hpre_hw_error_enable(struct hisi_qm *qm) 441 { 442 u32 val; 443 444 /* clear HPRE hw error source if having */ 445 writel(HPRE_CORE_INT_DISABLE, qm->io_base + HPRE_HAC_SOURCE_INT); 446 447 /* enable hpre hw error interrupts */ 448 writel(HPRE_CORE_INT_ENABLE, qm->io_base + HPRE_INT_MASK); 449 writel(HPRE_HAC_RAS_CE_ENABLE, qm->io_base + HPRE_RAS_CE_ENB); 450 writel(HPRE_HAC_RAS_NFE_ENABLE, qm->io_base + HPRE_RAS_NFE_ENB); 451 writel(HPRE_HAC_RAS_FE_ENABLE, qm->io_base + HPRE_RAS_FE_ENB); 452 453 /* enable HPRE block master OOO when m-bit error occur */ 454 val = readl(qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB); 455 val |= HPRE_AM_OOO_SHUTDOWN_ENABLE; 456 writel(val, qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB); 457 } 458 459 static inline struct hisi_qm *hpre_file_to_qm(struct hpre_debugfs_file *file) 460 { 461 struct hpre *hpre = container_of(file->debug, struct hpre, debug); 462 463 return &hpre->qm; 464 } 465 466 static u32 hpre_current_qm_read(struct hpre_debugfs_file *file) 467 { 468 struct hisi_qm *qm = hpre_file_to_qm(file); 469 470 return readl(qm->io_base + QM_DFX_MB_CNT_VF); 471 } 472 473 static int hpre_current_qm_write(struct hpre_debugfs_file *file, u32 val) 474 { 475 struct hisi_qm *qm = hpre_file_to_qm(file); 476 u32 num_vfs = qm->vfs_num; 477 u32 vfq_num, tmp; 478 479 if (val > num_vfs) 480 return -EINVAL; 481 482 /* According PF or VF Dev ID to calculation curr_qm_qp_num and store */ 483 if (val == 0) { 484 qm->debug.curr_qm_qp_num = qm->qp_num; 485 } else { 486 vfq_num = (qm->ctrl_qp_num - qm->qp_num) / num_vfs; 487 if (val == num_vfs) { 488 qm->debug.curr_qm_qp_num = 489 qm->ctrl_qp_num - qm->qp_num - (num_vfs - 1) * vfq_num; 490 } else { 491 qm->debug.curr_qm_qp_num = vfq_num; 492 } 493 } 494 495 writel(val, qm->io_base + QM_DFX_MB_CNT_VF); 496 writel(val, qm->io_base + QM_DFX_DB_CNT_VF); 497 498 tmp = val | 499 (readl(qm->io_base + QM_DFX_SQE_CNT_VF_SQN) & CURRENT_Q_MASK); 500 writel(tmp, qm->io_base + QM_DFX_SQE_CNT_VF_SQN); 501 502 tmp = val | 503 (readl(qm->io_base + QM_DFX_CQE_CNT_VF_CQN) & CURRENT_Q_MASK); 504 writel(tmp, qm->io_base + QM_DFX_CQE_CNT_VF_CQN); 505 506 return 0; 507 } 508 509 static u32 hpre_clear_enable_read(struct hpre_debugfs_file *file) 510 { 511 struct hisi_qm *qm = hpre_file_to_qm(file); 512 513 return readl(qm->io_base + HPRE_CTRL_CNT_CLR_CE) & 514 HPRE_CTRL_CNT_CLR_CE_BIT; 515 } 516 517 static int hpre_clear_enable_write(struct hpre_debugfs_file *file, u32 val) 518 { 519 struct hisi_qm *qm = hpre_file_to_qm(file); 520 u32 tmp; 521 522 if (val != 1 && val != 0) 523 return -EINVAL; 524 525 tmp = (readl(qm->io_base + HPRE_CTRL_CNT_CLR_CE) & 526 ~HPRE_CTRL_CNT_CLR_CE_BIT) | val; 527 writel(tmp, qm->io_base + HPRE_CTRL_CNT_CLR_CE); 528 529 return 0; 530 } 531 532 static u32 hpre_cluster_inqry_read(struct hpre_debugfs_file *file) 533 { 534 struct hisi_qm *qm = hpre_file_to_qm(file); 535 int cluster_index = file->index - HPRE_CLUSTER_CTRL; 536 unsigned long offset = HPRE_CLSTR_BASE + 537 cluster_index * HPRE_CLSTR_ADDR_INTRVL; 538 539 return readl(qm->io_base + offset + HPRE_CLSTR_ADDR_INQRY_RSLT); 540 } 541 542 static int hpre_cluster_inqry_write(struct hpre_debugfs_file *file, u32 val) 543 { 544 struct hisi_qm *qm = hpre_file_to_qm(file); 545 int cluster_index = file->index - HPRE_CLUSTER_CTRL; 546 unsigned long offset = HPRE_CLSTR_BASE + cluster_index * 547 HPRE_CLSTR_ADDR_INTRVL; 548 549 writel(val, qm->io_base + offset + HPRE_CLUSTER_INQURY); 550 551 return 0; 552 } 553 554 static ssize_t hpre_ctrl_debug_read(struct file *filp, char __user *buf, 555 size_t count, loff_t *pos) 556 { 557 struct hpre_debugfs_file *file = filp->private_data; 558 char tbuf[HPRE_DBGFS_VAL_MAX_LEN]; 559 u32 val; 560 int ret; 561 562 spin_lock_irq(&file->lock); 563 switch (file->type) { 564 case HPRE_CURRENT_QM: 565 val = hpre_current_qm_read(file); 566 break; 567 case HPRE_CLEAR_ENABLE: 568 val = hpre_clear_enable_read(file); 569 break; 570 case HPRE_CLUSTER_CTRL: 571 val = hpre_cluster_inqry_read(file); 572 break; 573 default: 574 spin_unlock_irq(&file->lock); 575 return -EINVAL; 576 } 577 spin_unlock_irq(&file->lock); 578 ret = snprintf(tbuf, HPRE_DBGFS_VAL_MAX_LEN, "%u\n", val); 579 return simple_read_from_buffer(buf, count, pos, tbuf, ret); 580 } 581 582 static ssize_t hpre_ctrl_debug_write(struct file *filp, const char __user *buf, 583 size_t count, loff_t *pos) 584 { 585 struct hpre_debugfs_file *file = filp->private_data; 586 char tbuf[HPRE_DBGFS_VAL_MAX_LEN]; 587 unsigned long val; 588 int len, ret; 589 590 if (*pos != 0) 591 return 0; 592 593 if (count >= HPRE_DBGFS_VAL_MAX_LEN) 594 return -ENOSPC; 595 596 len = simple_write_to_buffer(tbuf, HPRE_DBGFS_VAL_MAX_LEN - 1, 597 pos, buf, count); 598 if (len < 0) 599 return len; 600 601 tbuf[len] = '\0'; 602 if (kstrtoul(tbuf, 0, &val)) 603 return -EFAULT; 604 605 spin_lock_irq(&file->lock); 606 switch (file->type) { 607 case HPRE_CURRENT_QM: 608 ret = hpre_current_qm_write(file, val); 609 if (ret) 610 goto err_input; 611 break; 612 case HPRE_CLEAR_ENABLE: 613 ret = hpre_clear_enable_write(file, val); 614 if (ret) 615 goto err_input; 616 break; 617 case HPRE_CLUSTER_CTRL: 618 ret = hpre_cluster_inqry_write(file, val); 619 if (ret) 620 goto err_input; 621 break; 622 default: 623 ret = -EINVAL; 624 goto err_input; 625 } 626 spin_unlock_irq(&file->lock); 627 628 return count; 629 630 err_input: 631 spin_unlock_irq(&file->lock); 632 return ret; 633 } 634 635 static const struct file_operations hpre_ctrl_debug_fops = { 636 .owner = THIS_MODULE, 637 .open = simple_open, 638 .read = hpre_ctrl_debug_read, 639 .write = hpre_ctrl_debug_write, 640 }; 641 642 static int hpre_debugfs_atomic64_get(void *data, u64 *val) 643 { 644 struct hpre_dfx *dfx_item = data; 645 646 *val = atomic64_read(&dfx_item->value); 647 648 return 0; 649 } 650 651 static int hpre_debugfs_atomic64_set(void *data, u64 val) 652 { 653 struct hpre_dfx *dfx_item = data; 654 struct hpre_dfx *hpre_dfx = NULL; 655 656 if (dfx_item->type == HPRE_OVERTIME_THRHLD) { 657 hpre_dfx = dfx_item - HPRE_OVERTIME_THRHLD; 658 atomic64_set(&hpre_dfx[HPRE_OVER_THRHLD_CNT].value, 0); 659 } else if (val) { 660 return -EINVAL; 661 } 662 663 atomic64_set(&dfx_item->value, val); 664 665 return 0; 666 } 667 668 DEFINE_DEBUGFS_ATTRIBUTE(hpre_atomic64_ops, hpre_debugfs_atomic64_get, 669 hpre_debugfs_atomic64_set, "%llu\n"); 670 671 static int hpre_create_debugfs_file(struct hisi_qm *qm, struct dentry *dir, 672 enum hpre_ctrl_dbgfs_file type, int indx) 673 { 674 struct hpre *hpre = container_of(qm, struct hpre, qm); 675 struct hpre_debug *dbg = &hpre->debug; 676 struct dentry *file_dir; 677 678 if (dir) 679 file_dir = dir; 680 else 681 file_dir = qm->debug.debug_root; 682 683 if (type >= HPRE_DEBUG_FILE_NUM) 684 return -EINVAL; 685 686 spin_lock_init(&dbg->files[indx].lock); 687 dbg->files[indx].debug = dbg; 688 dbg->files[indx].type = type; 689 dbg->files[indx].index = indx; 690 debugfs_create_file(hpre_debug_file_name[type], 0600, file_dir, 691 dbg->files + indx, &hpre_ctrl_debug_fops); 692 693 return 0; 694 } 695 696 static int hpre_pf_comm_regs_debugfs_init(struct hisi_qm *qm) 697 { 698 struct device *dev = &qm->pdev->dev; 699 struct debugfs_regset32 *regset; 700 701 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 702 if (!regset) 703 return -ENOMEM; 704 705 regset->regs = hpre_com_dfx_regs; 706 regset->nregs = ARRAY_SIZE(hpre_com_dfx_regs); 707 regset->base = qm->io_base; 708 709 debugfs_create_regset32("regs", 0444, qm->debug.debug_root, regset); 710 return 0; 711 } 712 713 static int hpre_cluster_debugfs_init(struct hisi_qm *qm) 714 { 715 u8 clusters_num = HPRE_CLUSTERS_NUM(qm); 716 struct device *dev = &qm->pdev->dev; 717 char buf[HPRE_DBGFS_VAL_MAX_LEN]; 718 struct debugfs_regset32 *regset; 719 struct dentry *tmp_d; 720 int i, ret; 721 722 for (i = 0; i < clusters_num; i++) { 723 ret = snprintf(buf, HPRE_DBGFS_VAL_MAX_LEN, "cluster%d", i); 724 if (ret < 0) 725 return -EINVAL; 726 tmp_d = debugfs_create_dir(buf, qm->debug.debug_root); 727 728 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 729 if (!regset) 730 return -ENOMEM; 731 732 regset->regs = hpre_cluster_dfx_regs; 733 regset->nregs = ARRAY_SIZE(hpre_cluster_dfx_regs); 734 regset->base = qm->io_base + hpre_cluster_offsets[i]; 735 736 debugfs_create_regset32("regs", 0444, tmp_d, regset); 737 ret = hpre_create_debugfs_file(qm, tmp_d, HPRE_CLUSTER_CTRL, 738 i + HPRE_CLUSTER_CTRL); 739 if (ret) 740 return ret; 741 } 742 743 return 0; 744 } 745 746 static int hpre_ctrl_debug_init(struct hisi_qm *qm) 747 { 748 int ret; 749 750 ret = hpre_create_debugfs_file(qm, NULL, HPRE_CURRENT_QM, 751 HPRE_CURRENT_QM); 752 if (ret) 753 return ret; 754 755 ret = hpre_create_debugfs_file(qm, NULL, HPRE_CLEAR_ENABLE, 756 HPRE_CLEAR_ENABLE); 757 if (ret) 758 return ret; 759 760 ret = hpre_pf_comm_regs_debugfs_init(qm); 761 if (ret) 762 return ret; 763 764 return hpre_cluster_debugfs_init(qm); 765 } 766 767 static void hpre_dfx_debug_init(struct hisi_qm *qm) 768 { 769 struct hpre *hpre = container_of(qm, struct hpre, qm); 770 struct hpre_dfx *dfx = hpre->debug.dfx; 771 struct dentry *parent; 772 int i; 773 774 parent = debugfs_create_dir("hpre_dfx", qm->debug.debug_root); 775 for (i = 0; i < HPRE_DFX_FILE_NUM; i++) { 776 dfx[i].type = i; 777 debugfs_create_file(hpre_dfx_files[i], 0644, parent, &dfx[i], 778 &hpre_atomic64_ops); 779 } 780 } 781 782 static int hpre_debugfs_init(struct hisi_qm *qm) 783 { 784 struct device *dev = &qm->pdev->dev; 785 int ret; 786 787 qm->debug.debug_root = debugfs_create_dir(dev_name(dev), 788 hpre_debugfs_root); 789 790 qm->debug.sqe_mask_offset = HPRE_SQE_MASK_OFFSET; 791 qm->debug.sqe_mask_len = HPRE_SQE_MASK_LEN; 792 hisi_qm_debug_init(qm); 793 794 if (qm->pdev->device == HPRE_PCI_DEVICE_ID) { 795 ret = hpre_ctrl_debug_init(qm); 796 if (ret) 797 goto failed_to_create; 798 } 799 800 hpre_dfx_debug_init(qm); 801 802 return 0; 803 804 failed_to_create: 805 debugfs_remove_recursive(qm->debug.debug_root); 806 return ret; 807 } 808 809 static void hpre_debugfs_exit(struct hisi_qm *qm) 810 { 811 debugfs_remove_recursive(qm->debug.debug_root); 812 } 813 814 static int hpre_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) 815 { 816 if (pdev->revision == QM_HW_V1) { 817 pci_warn(pdev, "HPRE version 1 is not supported!\n"); 818 return -EINVAL; 819 } 820 821 if (pdev->revision >= QM_HW_V3) 822 qm->algs = "rsa\ndh\necdh\nx25519\nx448\necdsa\nsm2\n"; 823 else 824 qm->algs = "rsa\ndh\n"; 825 qm->mode = uacce_mode; 826 qm->pdev = pdev; 827 qm->ver = pdev->revision; 828 qm->sqe_size = HPRE_SQE_SIZE; 829 qm->dev_name = hpre_name; 830 831 qm->fun_type = (pdev->device == HPRE_PCI_DEVICE_ID) ? 832 QM_HW_PF : QM_HW_VF; 833 if (qm->fun_type == QM_HW_PF) { 834 qm->qp_base = HPRE_PF_DEF_Q_BASE; 835 qm->qp_num = pf_q_num; 836 qm->debug.curr_qm_qp_num = pf_q_num; 837 qm->qm_list = &hpre_devices; 838 } 839 840 return hisi_qm_init(qm); 841 } 842 843 static void hpre_log_hw_error(struct hisi_qm *qm, u32 err_sts) 844 { 845 const struct hpre_hw_error *err = hpre_hw_errors; 846 struct device *dev = &qm->pdev->dev; 847 848 while (err->msg) { 849 if (err->int_msk & err_sts) 850 dev_warn(dev, "%s [error status=0x%x] found\n", 851 err->msg, err->int_msk); 852 err++; 853 } 854 } 855 856 static u32 hpre_get_hw_err_status(struct hisi_qm *qm) 857 { 858 return readl(qm->io_base + HPRE_HAC_INT_STATUS); 859 } 860 861 static void hpre_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts) 862 { 863 writel(err_sts, qm->io_base + HPRE_HAC_SOURCE_INT); 864 } 865 866 static void hpre_open_axi_master_ooo(struct hisi_qm *qm) 867 { 868 u32 value; 869 870 value = readl(qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB); 871 writel(value & ~HPRE_AM_OOO_SHUTDOWN_ENABLE, 872 HPRE_ADDR(qm, HPRE_AM_OOO_SHUTDOWN_ENB)); 873 writel(value | HPRE_AM_OOO_SHUTDOWN_ENABLE, 874 HPRE_ADDR(qm, HPRE_AM_OOO_SHUTDOWN_ENB)); 875 } 876 877 static const struct hisi_qm_err_ini hpre_err_ini = { 878 .hw_init = hpre_set_user_domain_and_cache, 879 .hw_err_enable = hpre_hw_error_enable, 880 .hw_err_disable = hpre_hw_error_disable, 881 .get_dev_hw_err_status = hpre_get_hw_err_status, 882 .clear_dev_hw_err_status = hpre_clear_hw_err_status, 883 .log_dev_hw_err = hpre_log_hw_error, 884 .open_axi_master_ooo = hpre_open_axi_master_ooo, 885 .err_info = { 886 .ce = QM_BASE_CE, 887 .nfe = QM_BASE_NFE | QM_ACC_DO_TASK_TIMEOUT, 888 .fe = 0, 889 .ecc_2bits_mask = HPRE_CORE_ECC_2BIT_ERR | 890 HPRE_OOO_ECC_2BIT_ERR, 891 .dev_ce_mask = HPRE_HAC_RAS_CE_ENABLE, 892 .msi_wr_port = HPRE_WR_MSI_PORT, 893 .acpi_rst = "HRST", 894 } 895 }; 896 897 static int hpre_pf_probe_init(struct hpre *hpre) 898 { 899 struct hisi_qm *qm = &hpre->qm; 900 int ret; 901 902 qm->ctrl_qp_num = HPRE_QUEUE_NUM_V2; 903 904 ret = hpre_set_user_domain_and_cache(qm); 905 if (ret) 906 return ret; 907 908 qm->err_ini = &hpre_err_ini; 909 hisi_qm_dev_err_init(qm); 910 911 return 0; 912 } 913 914 static int hpre_probe_init(struct hpre *hpre) 915 { 916 struct hisi_qm *qm = &hpre->qm; 917 int ret; 918 919 if (qm->fun_type == QM_HW_PF) { 920 ret = hpre_pf_probe_init(hpre); 921 if (ret) 922 return ret; 923 } 924 925 return 0; 926 } 927 928 static int hpre_probe(struct pci_dev *pdev, const struct pci_device_id *id) 929 { 930 struct hisi_qm *qm; 931 struct hpre *hpre; 932 int ret; 933 934 hpre = devm_kzalloc(&pdev->dev, sizeof(*hpre), GFP_KERNEL); 935 if (!hpre) 936 return -ENOMEM; 937 938 qm = &hpre->qm; 939 ret = hpre_qm_init(qm, pdev); 940 if (ret) { 941 pci_err(pdev, "Failed to init HPRE QM (%d)!\n", ret); 942 return ret; 943 } 944 945 ret = hpre_probe_init(hpre); 946 if (ret) { 947 pci_err(pdev, "Failed to probe (%d)!\n", ret); 948 goto err_with_qm_init; 949 } 950 951 ret = hisi_qm_start(qm); 952 if (ret) 953 goto err_with_err_init; 954 955 ret = hpre_debugfs_init(qm); 956 if (ret) 957 dev_warn(&pdev->dev, "init debugfs fail!\n"); 958 959 ret = hisi_qm_alg_register(qm, &hpre_devices); 960 if (ret < 0) { 961 pci_err(pdev, "fail to register algs to crypto!\n"); 962 goto err_with_qm_start; 963 } 964 965 if (qm->uacce) { 966 ret = uacce_register(qm->uacce); 967 if (ret) { 968 pci_err(pdev, "failed to register uacce (%d)!\n", ret); 969 goto err_with_alg_register; 970 } 971 } 972 973 if (qm->fun_type == QM_HW_PF && vfs_num) { 974 ret = hisi_qm_sriov_enable(pdev, vfs_num); 975 if (ret < 0) 976 goto err_with_alg_register; 977 } 978 979 return 0; 980 981 err_with_alg_register: 982 hisi_qm_alg_unregister(qm, &hpre_devices); 983 984 err_with_qm_start: 985 hpre_debugfs_exit(qm); 986 hisi_qm_stop(qm, QM_NORMAL); 987 988 err_with_err_init: 989 hisi_qm_dev_err_uninit(qm); 990 991 err_with_qm_init: 992 hisi_qm_uninit(qm); 993 994 return ret; 995 } 996 997 static void hpre_remove(struct pci_dev *pdev) 998 { 999 struct hisi_qm *qm = pci_get_drvdata(pdev); 1000 int ret; 1001 1002 hisi_qm_wait_task_finish(qm, &hpre_devices); 1003 hisi_qm_alg_unregister(qm, &hpre_devices); 1004 if (qm->fun_type == QM_HW_PF && qm->vfs_num) { 1005 ret = hisi_qm_sriov_disable(pdev, true); 1006 if (ret) { 1007 pci_err(pdev, "Disable SRIOV fail!\n"); 1008 return; 1009 } 1010 } 1011 1012 hpre_debugfs_exit(qm); 1013 hisi_qm_stop(qm, QM_NORMAL); 1014 1015 if (qm->fun_type == QM_HW_PF) { 1016 if (qm->use_sva && qm->ver == QM_HW_V2) 1017 hpre_pasid_disable(qm); 1018 hpre_cnt_regs_clear(qm); 1019 qm->debug.curr_qm_qp_num = 0; 1020 hisi_qm_dev_err_uninit(qm); 1021 } 1022 1023 hisi_qm_uninit(qm); 1024 } 1025 1026 1027 static const struct pci_error_handlers hpre_err_handler = { 1028 .error_detected = hisi_qm_dev_err_detected, 1029 .slot_reset = hisi_qm_dev_slot_reset, 1030 .reset_prepare = hisi_qm_reset_prepare, 1031 .reset_done = hisi_qm_reset_done, 1032 }; 1033 1034 static struct pci_driver hpre_pci_driver = { 1035 .name = hpre_name, 1036 .id_table = hpre_dev_ids, 1037 .probe = hpre_probe, 1038 .remove = hpre_remove, 1039 .sriov_configure = IS_ENABLED(CONFIG_PCI_IOV) ? 1040 hisi_qm_sriov_configure : NULL, 1041 .err_handler = &hpre_err_handler, 1042 .shutdown = hisi_qm_dev_shutdown, 1043 }; 1044 1045 static void hpre_register_debugfs(void) 1046 { 1047 if (!debugfs_initialized()) 1048 return; 1049 1050 hpre_debugfs_root = debugfs_create_dir(hpre_name, NULL); 1051 } 1052 1053 static void hpre_unregister_debugfs(void) 1054 { 1055 debugfs_remove_recursive(hpre_debugfs_root); 1056 } 1057 1058 static int __init hpre_init(void) 1059 { 1060 int ret; 1061 1062 hisi_qm_init_list(&hpre_devices); 1063 hpre_register_debugfs(); 1064 1065 ret = pci_register_driver(&hpre_pci_driver); 1066 if (ret) { 1067 hpre_unregister_debugfs(); 1068 pr_err("hpre: can't register hisi hpre driver.\n"); 1069 } 1070 1071 return ret; 1072 } 1073 1074 static void __exit hpre_exit(void) 1075 { 1076 pci_unregister_driver(&hpre_pci_driver); 1077 hpre_unregister_debugfs(); 1078 } 1079 1080 module_init(hpre_init); 1081 module_exit(hpre_exit); 1082 1083 MODULE_LICENSE("GPL v2"); 1084 MODULE_AUTHOR("Zaibo Xu <xuzaibo@huawei.com>"); 1085 MODULE_AUTHOR("Meng Yu <yumeng18@huawei.com>"); 1086 MODULE_DESCRIPTION("Driver for HiSilicon HPRE accelerator"); 1087