1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018-2019 HiSilicon Limited. */
3 #include <linux/acpi.h>
4 #include <linux/aer.h>
5 #include <linux/bitops.h>
6 #include <linux/debugfs.h>
7 #include <linux/init.h>
8 #include <linux/io.h>
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/pci.h>
12 #include <linux/pm_runtime.h>
13 #include <linux/topology.h>
14 #include <linux/uacce.h>
15 #include "hpre.h"
16 
17 #define HPRE_QM_ABNML_INT_MASK		0x100004
18 #define HPRE_CTRL_CNT_CLR_CE_BIT	BIT(0)
19 #define HPRE_COMM_CNT_CLR_CE		0x0
20 #define HPRE_CTRL_CNT_CLR_CE		0x301000
21 #define HPRE_FSM_MAX_CNT		0x301008
22 #define HPRE_VFG_AXQOS			0x30100c
23 #define HPRE_VFG_AXCACHE		0x301010
24 #define HPRE_RDCHN_INI_CFG		0x301014
25 #define HPRE_AWUSR_FP_CFG		0x301018
26 #define HPRE_BD_ENDIAN			0x301020
27 #define HPRE_ECC_BYPASS			0x301024
28 #define HPRE_RAS_WIDTH_CFG		0x301028
29 #define HPRE_POISON_BYPASS		0x30102c
30 #define HPRE_BD_ARUSR_CFG		0x301030
31 #define HPRE_BD_AWUSR_CFG		0x301034
32 #define HPRE_TYPES_ENB			0x301038
33 #define HPRE_RSA_ENB			BIT(0)
34 #define HPRE_ECC_ENB			BIT(1)
35 #define HPRE_DATA_RUSER_CFG		0x30103c
36 #define HPRE_DATA_WUSER_CFG		0x301040
37 #define HPRE_INT_MASK			0x301400
38 #define HPRE_INT_STATUS			0x301800
39 #define HPRE_HAC_INT_MSK		0x301400
40 #define HPRE_HAC_RAS_CE_ENB		0x301410
41 #define HPRE_HAC_RAS_NFE_ENB		0x301414
42 #define HPRE_HAC_RAS_FE_ENB		0x301418
43 #define HPRE_HAC_INT_SET		0x301500
44 #define HPRE_RNG_TIMEOUT_NUM		0x301A34
45 #define HPRE_CORE_INT_ENABLE		0
46 #define HPRE_CORE_INT_DISABLE		GENMASK(21, 0)
47 #define HPRE_RDCHN_INI_ST		0x301a00
48 #define HPRE_CLSTR_BASE			0x302000
49 #define HPRE_CORE_EN_OFFSET		0x04
50 #define HPRE_CORE_INI_CFG_OFFSET	0x20
51 #define HPRE_CORE_INI_STATUS_OFFSET	0x80
52 #define HPRE_CORE_HTBT_WARN_OFFSET	0x8c
53 #define HPRE_CORE_IS_SCHD_OFFSET	0x90
54 
55 #define HPRE_RAS_CE_ENB			0x301410
56 #define HPRE_RAS_NFE_ENB		0x301414
57 #define HPRE_RAS_FE_ENB			0x301418
58 #define HPRE_OOO_SHUTDOWN_SEL		0x301a3c
59 #define HPRE_HAC_RAS_FE_ENABLE		0
60 
61 #define HPRE_CORE_ENB		(HPRE_CLSTR_BASE + HPRE_CORE_EN_OFFSET)
62 #define HPRE_CORE_INI_CFG	(HPRE_CLSTR_BASE + HPRE_CORE_INI_CFG_OFFSET)
63 #define HPRE_CORE_INI_STATUS (HPRE_CLSTR_BASE + HPRE_CORE_INI_STATUS_OFFSET)
64 #define HPRE_HAC_ECC1_CNT		0x301a04
65 #define HPRE_HAC_ECC2_CNT		0x301a08
66 #define HPRE_HAC_SOURCE_INT		0x301600
67 #define HPRE_CLSTR_ADDR_INTRVL		0x1000
68 #define HPRE_CLUSTER_INQURY		0x100
69 #define HPRE_CLSTR_ADDR_INQRY_RSLT	0x104
70 #define HPRE_TIMEOUT_ABNML_BIT		6
71 #define HPRE_PASID_EN_BIT		9
72 #define HPRE_REG_RD_INTVRL_US		10
73 #define HPRE_REG_RD_TMOUT_US		1000
74 #define HPRE_DBGFS_VAL_MAX_LEN		20
75 #define PCI_DEVICE_ID_HUAWEI_HPRE_PF	0xa258
76 #define HPRE_QM_USR_CFG_MASK		GENMASK(31, 1)
77 #define HPRE_QM_AXI_CFG_MASK		GENMASK(15, 0)
78 #define HPRE_QM_VFG_AX_MASK		GENMASK(7, 0)
79 #define HPRE_BD_USR_MASK		GENMASK(1, 0)
80 #define HPRE_PREFETCH_CFG		0x301130
81 #define HPRE_SVA_PREFTCH_DFX		0x30115C
82 #define HPRE_PREFETCH_ENABLE		(~(BIT(0) | BIT(30)))
83 #define HPRE_PREFETCH_DISABLE		BIT(30)
84 #define HPRE_SVA_DISABLE_READY		(BIT(4) | BIT(8))
85 
86 /* clock gate */
87 #define HPRE_CLKGATE_CTL		0x301a10
88 #define HPRE_PEH_CFG_AUTO_GATE		0x301a2c
89 #define HPRE_CLUSTER_DYN_CTL		0x302010
90 #define HPRE_CORE_SHB_CFG		0x302088
91 #define HPRE_CLKGATE_CTL_EN		BIT(0)
92 #define HPRE_PEH_CFG_AUTO_GATE_EN	BIT(0)
93 #define HPRE_CLUSTER_DYN_CTL_EN		BIT(0)
94 #define HPRE_CORE_GATE_EN		(BIT(30) | BIT(31))
95 
96 #define HPRE_AM_OOO_SHUTDOWN_ENB	0x301044
97 #define HPRE_AM_OOO_SHUTDOWN_ENABLE	BIT(0)
98 #define HPRE_WR_MSI_PORT		BIT(2)
99 
100 #define HPRE_CORE_ECC_2BIT_ERR		BIT(1)
101 #define HPRE_OOO_ECC_2BIT_ERR		BIT(5)
102 
103 #define HPRE_QM_BME_FLR			BIT(7)
104 #define HPRE_QM_PM_FLR			BIT(11)
105 #define HPRE_QM_SRIOV_FLR		BIT(12)
106 
107 #define HPRE_SHAPER_TYPE_RATE		640
108 #define HPRE_VIA_MSI_DSM		1
109 #define HPRE_SQE_MASK_OFFSET		8
110 #define HPRE_SQE_MASK_LEN		24
111 
112 #define HPRE_DFX_BASE		0x301000
113 #define HPRE_DFX_COMMON1		0x301400
114 #define HPRE_DFX_COMMON2		0x301A00
115 #define HPRE_DFX_CORE		0x302000
116 #define HPRE_DFX_BASE_LEN		0x55
117 #define HPRE_DFX_COMMON1_LEN		0x41
118 #define HPRE_DFX_COMMON2_LEN		0xE
119 #define HPRE_DFX_CORE_LEN		0x43
120 
121 #define HPRE_DEV_ALG_MAX_LEN	256
122 
123 static const char hpre_name[] = "hisi_hpre";
124 static struct dentry *hpre_debugfs_root;
125 static const struct pci_device_id hpre_dev_ids[] = {
126 	{ PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_HPRE_PF) },
127 	{ PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_HPRE_VF) },
128 	{ 0, }
129 };
130 
131 MODULE_DEVICE_TABLE(pci, hpre_dev_ids);
132 
133 struct hpre_hw_error {
134 	u32 int_msk;
135 	const char *msg;
136 };
137 
138 struct hpre_dev_alg {
139 	u32 alg_msk;
140 	const char *alg;
141 };
142 
143 static const struct hpre_dev_alg hpre_dev_algs[] = {
144 	{
145 		.alg_msk = BIT(0),
146 		.alg = "rsa\n"
147 	}, {
148 		.alg_msk = BIT(1),
149 		.alg = "dh\n"
150 	}, {
151 		.alg_msk = BIT(2),
152 		.alg = "ecdh\n"
153 	}, {
154 		.alg_msk = BIT(3),
155 		.alg = "ecdsa\n"
156 	}, {
157 		.alg_msk = BIT(4),
158 		.alg = "sm2\n"
159 	}, {
160 		.alg_msk = BIT(5),
161 		.alg = "x25519\n"
162 	}, {
163 		.alg_msk = BIT(6),
164 		.alg = "x448\n"
165 	}, {
166 		/* sentinel */
167 	}
168 };
169 
170 static struct hisi_qm_list hpre_devices = {
171 	.register_to_crypto	= hpre_algs_register,
172 	.unregister_from_crypto	= hpre_algs_unregister,
173 };
174 
175 static const char * const hpre_debug_file_name[] = {
176 	[HPRE_CLEAR_ENABLE] = "rdclr_en",
177 	[HPRE_CLUSTER_CTRL] = "cluster_ctrl",
178 };
179 
180 enum hpre_cap_type {
181 	HPRE_QM_NFE_MASK_CAP,
182 	HPRE_QM_RESET_MASK_CAP,
183 	HPRE_QM_OOO_SHUTDOWN_MASK_CAP,
184 	HPRE_QM_CE_MASK_CAP,
185 	HPRE_NFE_MASK_CAP,
186 	HPRE_RESET_MASK_CAP,
187 	HPRE_OOO_SHUTDOWN_MASK_CAP,
188 	HPRE_CE_MASK_CAP,
189 	HPRE_CLUSTER_NUM_CAP,
190 	HPRE_CORE_TYPE_NUM_CAP,
191 	HPRE_CORE_NUM_CAP,
192 	HPRE_CLUSTER_CORE_NUM_CAP,
193 	HPRE_CORE_ENABLE_BITMAP_CAP,
194 	HPRE_DRV_ALG_BITMAP_CAP,
195 	HPRE_DEV_ALG_BITMAP_CAP,
196 	HPRE_CORE1_ALG_BITMAP_CAP,
197 	HPRE_CORE2_ALG_BITMAP_CAP,
198 	HPRE_CORE3_ALG_BITMAP_CAP,
199 	HPRE_CORE4_ALG_BITMAP_CAP,
200 	HPRE_CORE5_ALG_BITMAP_CAP,
201 	HPRE_CORE6_ALG_BITMAP_CAP,
202 	HPRE_CORE7_ALG_BITMAP_CAP,
203 	HPRE_CORE8_ALG_BITMAP_CAP,
204 	HPRE_CORE9_ALG_BITMAP_CAP,
205 	HPRE_CORE10_ALG_BITMAP_CAP
206 };
207 
208 static const struct hisi_qm_cap_info hpre_basic_info[] = {
209 	{HPRE_QM_NFE_MASK_CAP, 0x3124, 0, GENMASK(31, 0), 0x0, 0x1C37, 0x7C37},
210 	{HPRE_QM_RESET_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0xC37, 0x6C37},
211 	{HPRE_QM_OOO_SHUTDOWN_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0x4, 0x6C37},
212 	{HPRE_QM_CE_MASK_CAP, 0x312C, 0, GENMASK(31, 0), 0x0, 0x8, 0x8},
213 	{HPRE_NFE_MASK_CAP, 0x3130, 0, GENMASK(31, 0), 0x0, 0x3FFFFE, 0xFFFFFE},
214 	{HPRE_RESET_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x3FFFFE, 0xBFFFFE},
215 	{HPRE_OOO_SHUTDOWN_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x22, 0xBFFFFE},
216 	{HPRE_CE_MASK_CAP, 0x3138, 0, GENMASK(31, 0), 0x0, 0x1, 0x1},
217 	{HPRE_CLUSTER_NUM_CAP, 0x313c, 20, GENMASK(3, 0), 0x0,  0x4, 0x1},
218 	{HPRE_CORE_TYPE_NUM_CAP, 0x313c, 16, GENMASK(3, 0), 0x0, 0x2, 0x2},
219 	{HPRE_CORE_NUM_CAP, 0x313c, 8, GENMASK(7, 0), 0x0, 0x8, 0xA},
220 	{HPRE_CLUSTER_CORE_NUM_CAP, 0x313c, 0, GENMASK(7, 0), 0x0, 0x2, 0xA},
221 	{HPRE_CORE_ENABLE_BITMAP_CAP, 0x3140, 0, GENMASK(31, 0), 0x0, 0xF, 0x3FF},
222 	{HPRE_DRV_ALG_BITMAP_CAP, 0x3144, 0, GENMASK(31, 0), 0x0, 0x03, 0x27},
223 	{HPRE_DEV_ALG_BITMAP_CAP, 0x3148, 0, GENMASK(31, 0), 0x0, 0x03, 0x7F},
224 	{HPRE_CORE1_ALG_BITMAP_CAP, 0x314c, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F},
225 	{HPRE_CORE2_ALG_BITMAP_CAP, 0x3150, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F},
226 	{HPRE_CORE3_ALG_BITMAP_CAP, 0x3154, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F},
227 	{HPRE_CORE4_ALG_BITMAP_CAP, 0x3158, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F},
228 	{HPRE_CORE5_ALG_BITMAP_CAP, 0x315c, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F},
229 	{HPRE_CORE6_ALG_BITMAP_CAP, 0x3160, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F},
230 	{HPRE_CORE7_ALG_BITMAP_CAP, 0x3164, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F},
231 	{HPRE_CORE8_ALG_BITMAP_CAP, 0x3168, 0, GENMASK(31, 0), 0x0, 0x7F, 0x7F},
232 	{HPRE_CORE9_ALG_BITMAP_CAP, 0x316c, 0, GENMASK(31, 0), 0x0, 0x10, 0x10},
233 	{HPRE_CORE10_ALG_BITMAP_CAP, 0x3170, 0, GENMASK(31, 0), 0x0, 0x10, 0x10}
234 };
235 
236 static const struct hpre_hw_error hpre_hw_errors[] = {
237 	{
238 		.int_msk = BIT(0),
239 		.msg = "core_ecc_1bit_err_int_set"
240 	}, {
241 		.int_msk = BIT(1),
242 		.msg = "core_ecc_2bit_err_int_set"
243 	}, {
244 		.int_msk = BIT(2),
245 		.msg = "dat_wb_poison_int_set"
246 	}, {
247 		.int_msk = BIT(3),
248 		.msg = "dat_rd_poison_int_set"
249 	}, {
250 		.int_msk = BIT(4),
251 		.msg = "bd_rd_poison_int_set"
252 	}, {
253 		.int_msk = BIT(5),
254 		.msg = "ooo_ecc_2bit_err_int_set"
255 	}, {
256 		.int_msk = BIT(6),
257 		.msg = "cluster1_shb_timeout_int_set"
258 	}, {
259 		.int_msk = BIT(7),
260 		.msg = "cluster2_shb_timeout_int_set"
261 	}, {
262 		.int_msk = BIT(8),
263 		.msg = "cluster3_shb_timeout_int_set"
264 	}, {
265 		.int_msk = BIT(9),
266 		.msg = "cluster4_shb_timeout_int_set"
267 	}, {
268 		.int_msk = GENMASK(15, 10),
269 		.msg = "ooo_rdrsp_err_int_set"
270 	}, {
271 		.int_msk = GENMASK(21, 16),
272 		.msg = "ooo_wrrsp_err_int_set"
273 	}, {
274 		.int_msk = BIT(22),
275 		.msg = "pt_rng_timeout_int_set"
276 	}, {
277 		.int_msk = BIT(23),
278 		.msg = "sva_fsm_timeout_int_set"
279 	}, {
280 		/* sentinel */
281 	}
282 };
283 
284 static const u64 hpre_cluster_offsets[] = {
285 	[HPRE_CLUSTER0] =
286 		HPRE_CLSTR_BASE + HPRE_CLUSTER0 * HPRE_CLSTR_ADDR_INTRVL,
287 	[HPRE_CLUSTER1] =
288 		HPRE_CLSTR_BASE + HPRE_CLUSTER1 * HPRE_CLSTR_ADDR_INTRVL,
289 	[HPRE_CLUSTER2] =
290 		HPRE_CLSTR_BASE + HPRE_CLUSTER2 * HPRE_CLSTR_ADDR_INTRVL,
291 	[HPRE_CLUSTER3] =
292 		HPRE_CLSTR_BASE + HPRE_CLUSTER3 * HPRE_CLSTR_ADDR_INTRVL,
293 };
294 
295 static const struct debugfs_reg32 hpre_cluster_dfx_regs[] = {
296 	{"CORES_EN_STATUS     ",  HPRE_CORE_EN_OFFSET},
297 	{"CORES_INI_CFG       ",  HPRE_CORE_INI_CFG_OFFSET},
298 	{"CORES_INI_STATUS    ",  HPRE_CORE_INI_STATUS_OFFSET},
299 	{"CORES_HTBT_WARN     ",  HPRE_CORE_HTBT_WARN_OFFSET},
300 	{"CORES_IS_SCHD       ",  HPRE_CORE_IS_SCHD_OFFSET},
301 };
302 
303 static const struct debugfs_reg32 hpre_com_dfx_regs[] = {
304 	{"READ_CLR_EN     ",  HPRE_CTRL_CNT_CLR_CE},
305 	{"AXQOS           ",  HPRE_VFG_AXQOS},
306 	{"AWUSR_CFG       ",  HPRE_AWUSR_FP_CFG},
307 	{"BD_ENDIAN       ",  HPRE_BD_ENDIAN},
308 	{"ECC_CHECK_CTRL  ",  HPRE_ECC_BYPASS},
309 	{"RAS_INT_WIDTH   ",  HPRE_RAS_WIDTH_CFG},
310 	{"POISON_BYPASS   ",  HPRE_POISON_BYPASS},
311 	{"BD_ARUSER       ",  HPRE_BD_ARUSR_CFG},
312 	{"BD_AWUSER       ",  HPRE_BD_AWUSR_CFG},
313 	{"DATA_ARUSER     ",  HPRE_DATA_RUSER_CFG},
314 	{"DATA_AWUSER     ",  HPRE_DATA_WUSER_CFG},
315 	{"INT_STATUS      ",  HPRE_INT_STATUS},
316 	{"INT_MASK        ",  HPRE_HAC_INT_MSK},
317 	{"RAS_CE_ENB      ",  HPRE_HAC_RAS_CE_ENB},
318 	{"RAS_NFE_ENB     ",  HPRE_HAC_RAS_NFE_ENB},
319 	{"RAS_FE_ENB      ",  HPRE_HAC_RAS_FE_ENB},
320 	{"INT_SET         ",  HPRE_HAC_INT_SET},
321 	{"RNG_TIMEOUT_NUM ",  HPRE_RNG_TIMEOUT_NUM},
322 };
323 
324 static const char *hpre_dfx_files[HPRE_DFX_FILE_NUM] = {
325 	"send_cnt",
326 	"recv_cnt",
327 	"send_fail_cnt",
328 	"send_busy_cnt",
329 	"over_thrhld_cnt",
330 	"overtime_thrhld",
331 	"invalid_req_cnt"
332 };
333 
334 /* define the HPRE's dfx regs region and region length */
335 static struct dfx_diff_registers hpre_diff_regs[] = {
336 	{
337 		.reg_offset = HPRE_DFX_BASE,
338 		.reg_len = HPRE_DFX_BASE_LEN,
339 	}, {
340 		.reg_offset = HPRE_DFX_COMMON1,
341 		.reg_len = HPRE_DFX_COMMON1_LEN,
342 	}, {
343 		.reg_offset = HPRE_DFX_COMMON2,
344 		.reg_len = HPRE_DFX_COMMON2_LEN,
345 	}, {
346 		.reg_offset = HPRE_DFX_CORE,
347 		.reg_len = HPRE_DFX_CORE_LEN,
348 	},
349 };
350 
351 bool hpre_check_alg_support(struct hisi_qm *qm, u32 alg)
352 {
353 	u32 cap_val;
354 
355 	cap_val = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_DRV_ALG_BITMAP_CAP, qm->cap_ver);
356 	if (alg & cap_val)
357 		return true;
358 
359 	return false;
360 }
361 
362 static int hpre_set_qm_algs(struct hisi_qm *qm)
363 {
364 	struct device *dev = &qm->pdev->dev;
365 	char *algs, *ptr;
366 	u32 alg_msk;
367 	int i;
368 
369 	if (!qm->use_sva)
370 		return 0;
371 
372 	algs = devm_kzalloc(dev, HPRE_DEV_ALG_MAX_LEN * sizeof(char), GFP_KERNEL);
373 	if (!algs)
374 		return -ENOMEM;
375 
376 	alg_msk = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_DEV_ALG_BITMAP_CAP, qm->cap_ver);
377 
378 	for (i = 0; i < ARRAY_SIZE(hpre_dev_algs); i++)
379 		if (alg_msk & hpre_dev_algs[i].alg_msk)
380 			strcat(algs, hpre_dev_algs[i].alg);
381 
382 	ptr = strrchr(algs, '\n');
383 	if (ptr)
384 		*ptr = '\0';
385 
386 	qm->uacce->algs = algs;
387 
388 	return 0;
389 }
390 
391 static int hpre_diff_regs_show(struct seq_file *s, void *unused)
392 {
393 	struct hisi_qm *qm = s->private;
394 
395 	hisi_qm_acc_diff_regs_dump(qm, s, qm->debug.acc_diff_regs,
396 					ARRAY_SIZE(hpre_diff_regs));
397 
398 	return 0;
399 }
400 
401 DEFINE_SHOW_ATTRIBUTE(hpre_diff_regs);
402 
403 static int hpre_com_regs_show(struct seq_file *s, void *unused)
404 {
405 	hisi_qm_regs_dump(s, s->private);
406 
407 	return 0;
408 }
409 
410 DEFINE_SHOW_ATTRIBUTE(hpre_com_regs);
411 
412 static int hpre_cluster_regs_show(struct seq_file *s, void *unused)
413 {
414 	hisi_qm_regs_dump(s, s->private);
415 
416 	return 0;
417 }
418 
419 DEFINE_SHOW_ATTRIBUTE(hpre_cluster_regs);
420 
421 static const struct kernel_param_ops hpre_uacce_mode_ops = {
422 	.set = uacce_mode_set,
423 	.get = param_get_int,
424 };
425 
426 /*
427  * uacce_mode = 0 means hpre only register to crypto,
428  * uacce_mode = 1 means hpre both register to crypto and uacce.
429  */
430 static u32 uacce_mode = UACCE_MODE_NOUACCE;
431 module_param_cb(uacce_mode, &hpre_uacce_mode_ops, &uacce_mode, 0444);
432 MODULE_PARM_DESC(uacce_mode, UACCE_MODE_DESC);
433 
434 static int pf_q_num_set(const char *val, const struct kernel_param *kp)
435 {
436 	return q_num_set(val, kp, PCI_DEVICE_ID_HUAWEI_HPRE_PF);
437 }
438 
439 static const struct kernel_param_ops hpre_pf_q_num_ops = {
440 	.set = pf_q_num_set,
441 	.get = param_get_int,
442 };
443 
444 static u32 pf_q_num = HPRE_PF_DEF_Q_NUM;
445 module_param_cb(pf_q_num, &hpre_pf_q_num_ops, &pf_q_num, 0444);
446 MODULE_PARM_DESC(pf_q_num, "Number of queues in PF of CS(2-1024)");
447 
448 static const struct kernel_param_ops vfs_num_ops = {
449 	.set = vfs_num_set,
450 	.get = param_get_int,
451 };
452 
453 static u32 vfs_num;
454 module_param_cb(vfs_num, &vfs_num_ops, &vfs_num, 0444);
455 MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)");
456 
457 static inline int hpre_cluster_num(struct hisi_qm *qm)
458 {
459 	return hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_CLUSTER_NUM_CAP, qm->cap_ver);
460 }
461 
462 static inline int hpre_cluster_core_mask(struct hisi_qm *qm)
463 {
464 	return hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_CORE_ENABLE_BITMAP_CAP, qm->cap_ver);
465 }
466 
467 struct hisi_qp *hpre_create_qp(u8 type)
468 {
469 	int node = cpu_to_node(smp_processor_id());
470 	struct hisi_qp *qp = NULL;
471 	int ret;
472 
473 	if (type != HPRE_V2_ALG_TYPE && type != HPRE_V3_ECC_ALG_TYPE)
474 		return NULL;
475 
476 	/*
477 	 * type: 0 - RSA/DH. algorithm supported in V2,
478 	 *       1 - ECC algorithm in V3.
479 	 */
480 	ret = hisi_qm_alloc_qps_node(&hpre_devices, 1, type, node, &qp);
481 	if (!ret)
482 		return qp;
483 
484 	return NULL;
485 }
486 
487 static void hpre_config_pasid(struct hisi_qm *qm)
488 {
489 	u32 val1, val2;
490 
491 	if (qm->ver >= QM_HW_V3)
492 		return;
493 
494 	val1 = readl_relaxed(qm->io_base + HPRE_DATA_RUSER_CFG);
495 	val2 = readl_relaxed(qm->io_base + HPRE_DATA_WUSER_CFG);
496 	if (qm->use_sva) {
497 		val1 |= BIT(HPRE_PASID_EN_BIT);
498 		val2 |= BIT(HPRE_PASID_EN_BIT);
499 	} else {
500 		val1 &= ~BIT(HPRE_PASID_EN_BIT);
501 		val2 &= ~BIT(HPRE_PASID_EN_BIT);
502 	}
503 	writel_relaxed(val1, qm->io_base + HPRE_DATA_RUSER_CFG);
504 	writel_relaxed(val2, qm->io_base + HPRE_DATA_WUSER_CFG);
505 }
506 
507 static int hpre_cfg_by_dsm(struct hisi_qm *qm)
508 {
509 	struct device *dev = &qm->pdev->dev;
510 	union acpi_object *obj;
511 	guid_t guid;
512 
513 	if (guid_parse("b06b81ab-0134-4a45-9b0c-483447b95fa7", &guid)) {
514 		dev_err(dev, "Hpre GUID failed\n");
515 		return -EINVAL;
516 	}
517 
518 	/* Switch over to MSI handling due to non-standard PCI implementation */
519 	obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &guid,
520 				0, HPRE_VIA_MSI_DSM, NULL);
521 	if (!obj) {
522 		dev_err(dev, "ACPI handle failed!\n");
523 		return -EIO;
524 	}
525 
526 	ACPI_FREE(obj);
527 
528 	return 0;
529 }
530 
531 static int hpre_set_cluster(struct hisi_qm *qm)
532 {
533 	u32 cluster_core_mask = hpre_cluster_core_mask(qm);
534 	u8 clusters_num = hpre_cluster_num(qm);
535 	struct device *dev = &qm->pdev->dev;
536 	unsigned long offset;
537 	u32 val = 0;
538 	int ret, i;
539 
540 	for (i = 0; i < clusters_num; i++) {
541 		offset = i * HPRE_CLSTR_ADDR_INTRVL;
542 
543 		/* clusters initiating */
544 		writel(cluster_core_mask,
545 		       qm->io_base + offset + HPRE_CORE_ENB);
546 		writel(0x1, qm->io_base + offset + HPRE_CORE_INI_CFG);
547 		ret = readl_relaxed_poll_timeout(qm->io_base + offset +
548 					HPRE_CORE_INI_STATUS, val,
549 					((val & cluster_core_mask) ==
550 					cluster_core_mask),
551 					HPRE_REG_RD_INTVRL_US,
552 					HPRE_REG_RD_TMOUT_US);
553 		if (ret) {
554 			dev_err(dev,
555 				"cluster %d int st status timeout!\n", i);
556 			return -ETIMEDOUT;
557 		}
558 	}
559 
560 	return 0;
561 }
562 
563 /*
564  * For Kunpeng 920, we should disable FLR triggered by hardware (BME/PM/SRIOV).
565  * Or it may stay in D3 state when we bind and unbind hpre quickly,
566  * as it does FLR triggered by hardware.
567  */
568 static void disable_flr_of_bme(struct hisi_qm *qm)
569 {
570 	u32 val;
571 
572 	val = readl(qm->io_base + QM_PEH_AXUSER_CFG);
573 	val &= ~(HPRE_QM_BME_FLR | HPRE_QM_SRIOV_FLR);
574 	val |= HPRE_QM_PM_FLR;
575 	writel(val, qm->io_base + QM_PEH_AXUSER_CFG);
576 	writel(PEH_AXUSER_CFG_ENABLE, qm->io_base + QM_PEH_AXUSER_CFG_ENABLE);
577 }
578 
579 static void hpre_open_sva_prefetch(struct hisi_qm *qm)
580 {
581 	u32 val;
582 	int ret;
583 
584 	if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps))
585 		return;
586 
587 	/* Enable prefetch */
588 	val = readl_relaxed(qm->io_base + HPRE_PREFETCH_CFG);
589 	val &= HPRE_PREFETCH_ENABLE;
590 	writel(val, qm->io_base + HPRE_PREFETCH_CFG);
591 
592 	ret = readl_relaxed_poll_timeout(qm->io_base + HPRE_PREFETCH_CFG,
593 					 val, !(val & HPRE_PREFETCH_DISABLE),
594 					 HPRE_REG_RD_INTVRL_US,
595 					 HPRE_REG_RD_TMOUT_US);
596 	if (ret)
597 		pci_err(qm->pdev, "failed to open sva prefetch\n");
598 }
599 
600 static void hpre_close_sva_prefetch(struct hisi_qm *qm)
601 {
602 	u32 val;
603 	int ret;
604 
605 	if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps))
606 		return;
607 
608 	val = readl_relaxed(qm->io_base + HPRE_PREFETCH_CFG);
609 	val |= HPRE_PREFETCH_DISABLE;
610 	writel(val, qm->io_base + HPRE_PREFETCH_CFG);
611 
612 	ret = readl_relaxed_poll_timeout(qm->io_base + HPRE_SVA_PREFTCH_DFX,
613 					 val, !(val & HPRE_SVA_DISABLE_READY),
614 					 HPRE_REG_RD_INTVRL_US,
615 					 HPRE_REG_RD_TMOUT_US);
616 	if (ret)
617 		pci_err(qm->pdev, "failed to close sva prefetch\n");
618 }
619 
620 static void hpre_enable_clock_gate(struct hisi_qm *qm)
621 {
622 	u32 val;
623 
624 	if (qm->ver < QM_HW_V3)
625 		return;
626 
627 	val = readl(qm->io_base + HPRE_CLKGATE_CTL);
628 	val |= HPRE_CLKGATE_CTL_EN;
629 	writel(val, qm->io_base + HPRE_CLKGATE_CTL);
630 
631 	val = readl(qm->io_base + HPRE_PEH_CFG_AUTO_GATE);
632 	val |= HPRE_PEH_CFG_AUTO_GATE_EN;
633 	writel(val, qm->io_base + HPRE_PEH_CFG_AUTO_GATE);
634 
635 	val = readl(qm->io_base + HPRE_CLUSTER_DYN_CTL);
636 	val |= HPRE_CLUSTER_DYN_CTL_EN;
637 	writel(val, qm->io_base + HPRE_CLUSTER_DYN_CTL);
638 
639 	val = readl_relaxed(qm->io_base + HPRE_CORE_SHB_CFG);
640 	val |= HPRE_CORE_GATE_EN;
641 	writel(val, qm->io_base + HPRE_CORE_SHB_CFG);
642 }
643 
644 static void hpre_disable_clock_gate(struct hisi_qm *qm)
645 {
646 	u32 val;
647 
648 	if (qm->ver < QM_HW_V3)
649 		return;
650 
651 	val = readl(qm->io_base + HPRE_CLKGATE_CTL);
652 	val &= ~HPRE_CLKGATE_CTL_EN;
653 	writel(val, qm->io_base + HPRE_CLKGATE_CTL);
654 
655 	val = readl(qm->io_base + HPRE_PEH_CFG_AUTO_GATE);
656 	val &= ~HPRE_PEH_CFG_AUTO_GATE_EN;
657 	writel(val, qm->io_base + HPRE_PEH_CFG_AUTO_GATE);
658 
659 	val = readl(qm->io_base + HPRE_CLUSTER_DYN_CTL);
660 	val &= ~HPRE_CLUSTER_DYN_CTL_EN;
661 	writel(val, qm->io_base + HPRE_CLUSTER_DYN_CTL);
662 
663 	val = readl_relaxed(qm->io_base + HPRE_CORE_SHB_CFG);
664 	val &= ~HPRE_CORE_GATE_EN;
665 	writel(val, qm->io_base + HPRE_CORE_SHB_CFG);
666 }
667 
668 static int hpre_set_user_domain_and_cache(struct hisi_qm *qm)
669 {
670 	struct device *dev = &qm->pdev->dev;
671 	u32 val;
672 	int ret;
673 
674 	/* disabel dynamic clock gate before sram init */
675 	hpre_disable_clock_gate(qm);
676 
677 	writel(HPRE_QM_USR_CFG_MASK, qm->io_base + QM_ARUSER_M_CFG_ENABLE);
678 	writel(HPRE_QM_USR_CFG_MASK, qm->io_base + QM_AWUSER_M_CFG_ENABLE);
679 	writel_relaxed(HPRE_QM_AXI_CFG_MASK, qm->io_base + QM_AXI_M_CFG);
680 
681 	/* HPRE need more time, we close this interrupt */
682 	val = readl_relaxed(qm->io_base + HPRE_QM_ABNML_INT_MASK);
683 	val |= BIT(HPRE_TIMEOUT_ABNML_BIT);
684 	writel_relaxed(val, qm->io_base + HPRE_QM_ABNML_INT_MASK);
685 
686 	if (qm->ver >= QM_HW_V3)
687 		writel(HPRE_RSA_ENB | HPRE_ECC_ENB,
688 			qm->io_base + HPRE_TYPES_ENB);
689 	else
690 		writel(HPRE_RSA_ENB, qm->io_base + HPRE_TYPES_ENB);
691 
692 	writel(HPRE_QM_VFG_AX_MASK, qm->io_base + HPRE_VFG_AXCACHE);
693 	writel(0x0, qm->io_base + HPRE_BD_ENDIAN);
694 	writel(0x0, qm->io_base + HPRE_INT_MASK);
695 	writel(0x0, qm->io_base + HPRE_POISON_BYPASS);
696 	writel(0x0, qm->io_base + HPRE_COMM_CNT_CLR_CE);
697 	writel(0x0, qm->io_base + HPRE_ECC_BYPASS);
698 
699 	writel(HPRE_BD_USR_MASK, qm->io_base + HPRE_BD_ARUSR_CFG);
700 	writel(HPRE_BD_USR_MASK, qm->io_base + HPRE_BD_AWUSR_CFG);
701 	writel(0x1, qm->io_base + HPRE_RDCHN_INI_CFG);
702 	ret = readl_relaxed_poll_timeout(qm->io_base + HPRE_RDCHN_INI_ST, val,
703 			val & BIT(0),
704 			HPRE_REG_RD_INTVRL_US,
705 			HPRE_REG_RD_TMOUT_US);
706 	if (ret) {
707 		dev_err(dev, "read rd channel timeout fail!\n");
708 		return -ETIMEDOUT;
709 	}
710 
711 	ret = hpre_set_cluster(qm);
712 	if (ret)
713 		return -ETIMEDOUT;
714 
715 	/* This setting is only needed by Kunpeng 920. */
716 	if (qm->ver == QM_HW_V2) {
717 		ret = hpre_cfg_by_dsm(qm);
718 		if (ret)
719 			return ret;
720 
721 		disable_flr_of_bme(qm);
722 	}
723 
724 	/* Config data buffer pasid needed by Kunpeng 920 */
725 	hpre_config_pasid(qm);
726 
727 	hpre_enable_clock_gate(qm);
728 
729 	return ret;
730 }
731 
732 static void hpre_cnt_regs_clear(struct hisi_qm *qm)
733 {
734 	u8 clusters_num = hpre_cluster_num(qm);
735 	unsigned long offset;
736 	int i;
737 
738 	/* clear clusterX/cluster_ctrl */
739 	for (i = 0; i < clusters_num; i++) {
740 		offset = HPRE_CLSTR_BASE + i * HPRE_CLSTR_ADDR_INTRVL;
741 		writel(0x0, qm->io_base + offset + HPRE_CLUSTER_INQURY);
742 	}
743 
744 	/* clear rdclr_en */
745 	writel(0x0, qm->io_base + HPRE_CTRL_CNT_CLR_CE);
746 
747 	hisi_qm_debug_regs_clear(qm);
748 }
749 
750 static void hpre_master_ooo_ctrl(struct hisi_qm *qm, bool enable)
751 {
752 	u32 val1, val2;
753 
754 	val1 = readl(qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB);
755 	if (enable) {
756 		val1 |= HPRE_AM_OOO_SHUTDOWN_ENABLE;
757 		val2 = hisi_qm_get_hw_info(qm, hpre_basic_info,
758 					   HPRE_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver);
759 	} else {
760 		val1 &= ~HPRE_AM_OOO_SHUTDOWN_ENABLE;
761 		val2 = 0x0;
762 	}
763 
764 	if (qm->ver > QM_HW_V2)
765 		writel(val2, qm->io_base + HPRE_OOO_SHUTDOWN_SEL);
766 
767 	writel(val1, qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB);
768 }
769 
770 static void hpre_hw_error_disable(struct hisi_qm *qm)
771 {
772 	u32 ce, nfe;
773 
774 	ce = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_CE_MASK_CAP, qm->cap_ver);
775 	nfe = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_NFE_MASK_CAP, qm->cap_ver);
776 
777 	/* disable hpre hw error interrupts */
778 	writel(ce | nfe | HPRE_HAC_RAS_FE_ENABLE, qm->io_base + HPRE_INT_MASK);
779 	/* disable HPRE block master OOO when nfe occurs on Kunpeng930 */
780 	hpre_master_ooo_ctrl(qm, false);
781 }
782 
783 static void hpre_hw_error_enable(struct hisi_qm *qm)
784 {
785 	u32 ce, nfe;
786 
787 	ce = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_CE_MASK_CAP, qm->cap_ver);
788 	nfe = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_NFE_MASK_CAP, qm->cap_ver);
789 
790 	/* clear HPRE hw error source if having */
791 	writel(ce | nfe | HPRE_HAC_RAS_FE_ENABLE, qm->io_base + HPRE_HAC_SOURCE_INT);
792 
793 	/* configure error type */
794 	writel(ce, qm->io_base + HPRE_RAS_CE_ENB);
795 	writel(nfe, qm->io_base + HPRE_RAS_NFE_ENB);
796 	writel(HPRE_HAC_RAS_FE_ENABLE, qm->io_base + HPRE_RAS_FE_ENB);
797 
798 	/* enable HPRE block master OOO when nfe occurs on Kunpeng930 */
799 	hpre_master_ooo_ctrl(qm, true);
800 
801 	/* enable hpre hw error interrupts */
802 	writel(HPRE_CORE_INT_ENABLE, qm->io_base + HPRE_INT_MASK);
803 }
804 
805 static inline struct hisi_qm *hpre_file_to_qm(struct hpre_debugfs_file *file)
806 {
807 	struct hpre *hpre = container_of(file->debug, struct hpre, debug);
808 
809 	return &hpre->qm;
810 }
811 
812 static u32 hpre_clear_enable_read(struct hpre_debugfs_file *file)
813 {
814 	struct hisi_qm *qm = hpre_file_to_qm(file);
815 
816 	return readl(qm->io_base + HPRE_CTRL_CNT_CLR_CE) &
817 	       HPRE_CTRL_CNT_CLR_CE_BIT;
818 }
819 
820 static int hpre_clear_enable_write(struct hpre_debugfs_file *file, u32 val)
821 {
822 	struct hisi_qm *qm = hpre_file_to_qm(file);
823 	u32 tmp;
824 
825 	if (val != 1 && val != 0)
826 		return -EINVAL;
827 
828 	tmp = (readl(qm->io_base + HPRE_CTRL_CNT_CLR_CE) &
829 	       ~HPRE_CTRL_CNT_CLR_CE_BIT) | val;
830 	writel(tmp, qm->io_base + HPRE_CTRL_CNT_CLR_CE);
831 
832 	return 0;
833 }
834 
835 static u32 hpre_cluster_inqry_read(struct hpre_debugfs_file *file)
836 {
837 	struct hisi_qm *qm = hpre_file_to_qm(file);
838 	int cluster_index = file->index - HPRE_CLUSTER_CTRL;
839 	unsigned long offset = HPRE_CLSTR_BASE +
840 			       cluster_index * HPRE_CLSTR_ADDR_INTRVL;
841 
842 	return readl(qm->io_base + offset + HPRE_CLSTR_ADDR_INQRY_RSLT);
843 }
844 
845 static void hpre_cluster_inqry_write(struct hpre_debugfs_file *file, u32 val)
846 {
847 	struct hisi_qm *qm = hpre_file_to_qm(file);
848 	int cluster_index = file->index - HPRE_CLUSTER_CTRL;
849 	unsigned long offset = HPRE_CLSTR_BASE + cluster_index *
850 			       HPRE_CLSTR_ADDR_INTRVL;
851 
852 	writel(val, qm->io_base + offset + HPRE_CLUSTER_INQURY);
853 }
854 
855 static ssize_t hpre_ctrl_debug_read(struct file *filp, char __user *buf,
856 				    size_t count, loff_t *pos)
857 {
858 	struct hpre_debugfs_file *file = filp->private_data;
859 	struct hisi_qm *qm = hpre_file_to_qm(file);
860 	char tbuf[HPRE_DBGFS_VAL_MAX_LEN];
861 	u32 val;
862 	int ret;
863 
864 	ret = hisi_qm_get_dfx_access(qm);
865 	if (ret)
866 		return ret;
867 
868 	spin_lock_irq(&file->lock);
869 	switch (file->type) {
870 	case HPRE_CLEAR_ENABLE:
871 		val = hpre_clear_enable_read(file);
872 		break;
873 	case HPRE_CLUSTER_CTRL:
874 		val = hpre_cluster_inqry_read(file);
875 		break;
876 	default:
877 		goto err_input;
878 	}
879 	spin_unlock_irq(&file->lock);
880 
881 	hisi_qm_put_dfx_access(qm);
882 	ret = snprintf(tbuf, HPRE_DBGFS_VAL_MAX_LEN, "%u\n", val);
883 	return simple_read_from_buffer(buf, count, pos, tbuf, ret);
884 
885 err_input:
886 	spin_unlock_irq(&file->lock);
887 	hisi_qm_put_dfx_access(qm);
888 	return -EINVAL;
889 }
890 
891 static ssize_t hpre_ctrl_debug_write(struct file *filp, const char __user *buf,
892 				     size_t count, loff_t *pos)
893 {
894 	struct hpre_debugfs_file *file = filp->private_data;
895 	struct hisi_qm *qm = hpre_file_to_qm(file);
896 	char tbuf[HPRE_DBGFS_VAL_MAX_LEN];
897 	unsigned long val;
898 	int len, ret;
899 
900 	if (*pos != 0)
901 		return 0;
902 
903 	if (count >= HPRE_DBGFS_VAL_MAX_LEN)
904 		return -ENOSPC;
905 
906 	len = simple_write_to_buffer(tbuf, HPRE_DBGFS_VAL_MAX_LEN - 1,
907 				     pos, buf, count);
908 	if (len < 0)
909 		return len;
910 
911 	tbuf[len] = '\0';
912 	if (kstrtoul(tbuf, 0, &val))
913 		return -EFAULT;
914 
915 	ret = hisi_qm_get_dfx_access(qm);
916 	if (ret)
917 		return ret;
918 
919 	spin_lock_irq(&file->lock);
920 	switch (file->type) {
921 	case HPRE_CLEAR_ENABLE:
922 		ret = hpre_clear_enable_write(file, val);
923 		if (ret)
924 			goto err_input;
925 		break;
926 	case HPRE_CLUSTER_CTRL:
927 		hpre_cluster_inqry_write(file, val);
928 		break;
929 	default:
930 		ret = -EINVAL;
931 		goto err_input;
932 	}
933 
934 	ret = count;
935 
936 err_input:
937 	spin_unlock_irq(&file->lock);
938 	hisi_qm_put_dfx_access(qm);
939 	return ret;
940 }
941 
942 static const struct file_operations hpre_ctrl_debug_fops = {
943 	.owner = THIS_MODULE,
944 	.open = simple_open,
945 	.read = hpre_ctrl_debug_read,
946 	.write = hpre_ctrl_debug_write,
947 };
948 
949 static int hpre_debugfs_atomic64_get(void *data, u64 *val)
950 {
951 	struct hpre_dfx *dfx_item = data;
952 
953 	*val = atomic64_read(&dfx_item->value);
954 
955 	return 0;
956 }
957 
958 static int hpre_debugfs_atomic64_set(void *data, u64 val)
959 {
960 	struct hpre_dfx *dfx_item = data;
961 	struct hpre_dfx *hpre_dfx = NULL;
962 
963 	if (dfx_item->type == HPRE_OVERTIME_THRHLD) {
964 		hpre_dfx = dfx_item - HPRE_OVERTIME_THRHLD;
965 		atomic64_set(&hpre_dfx[HPRE_OVER_THRHLD_CNT].value, 0);
966 	} else if (val) {
967 		return -EINVAL;
968 	}
969 
970 	atomic64_set(&dfx_item->value, val);
971 
972 	return 0;
973 }
974 
975 DEFINE_DEBUGFS_ATTRIBUTE(hpre_atomic64_ops, hpre_debugfs_atomic64_get,
976 			 hpre_debugfs_atomic64_set, "%llu\n");
977 
978 static int hpre_create_debugfs_file(struct hisi_qm *qm, struct dentry *dir,
979 				    enum hpre_ctrl_dbgfs_file type, int indx)
980 {
981 	struct hpre *hpre = container_of(qm, struct hpre, qm);
982 	struct hpre_debug *dbg = &hpre->debug;
983 	struct dentry *file_dir;
984 
985 	if (dir)
986 		file_dir = dir;
987 	else
988 		file_dir = qm->debug.debug_root;
989 
990 	if (type >= HPRE_DEBUG_FILE_NUM)
991 		return -EINVAL;
992 
993 	spin_lock_init(&dbg->files[indx].lock);
994 	dbg->files[indx].debug = dbg;
995 	dbg->files[indx].type = type;
996 	dbg->files[indx].index = indx;
997 	debugfs_create_file(hpre_debug_file_name[type], 0600, file_dir,
998 			    dbg->files + indx, &hpre_ctrl_debug_fops);
999 
1000 	return 0;
1001 }
1002 
1003 static int hpre_pf_comm_regs_debugfs_init(struct hisi_qm *qm)
1004 {
1005 	struct device *dev = &qm->pdev->dev;
1006 	struct debugfs_regset32 *regset;
1007 
1008 	regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL);
1009 	if (!regset)
1010 		return -ENOMEM;
1011 
1012 	regset->regs = hpre_com_dfx_regs;
1013 	regset->nregs = ARRAY_SIZE(hpre_com_dfx_regs);
1014 	regset->base = qm->io_base;
1015 	regset->dev = dev;
1016 
1017 	debugfs_create_file("regs", 0444, qm->debug.debug_root,
1018 			    regset, &hpre_com_regs_fops);
1019 
1020 	return 0;
1021 }
1022 
1023 static int hpre_cluster_debugfs_init(struct hisi_qm *qm)
1024 {
1025 	u8 clusters_num = hpre_cluster_num(qm);
1026 	struct device *dev = &qm->pdev->dev;
1027 	char buf[HPRE_DBGFS_VAL_MAX_LEN];
1028 	struct debugfs_regset32 *regset;
1029 	struct dentry *tmp_d;
1030 	int i, ret;
1031 
1032 	for (i = 0; i < clusters_num; i++) {
1033 		ret = snprintf(buf, HPRE_DBGFS_VAL_MAX_LEN, "cluster%d", i);
1034 		if (ret < 0)
1035 			return -EINVAL;
1036 		tmp_d = debugfs_create_dir(buf, qm->debug.debug_root);
1037 
1038 		regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL);
1039 		if (!regset)
1040 			return -ENOMEM;
1041 
1042 		regset->regs = hpre_cluster_dfx_regs;
1043 		regset->nregs = ARRAY_SIZE(hpre_cluster_dfx_regs);
1044 		regset->base = qm->io_base + hpre_cluster_offsets[i];
1045 		regset->dev = dev;
1046 
1047 		debugfs_create_file("regs", 0444, tmp_d, regset,
1048 				    &hpre_cluster_regs_fops);
1049 		ret = hpre_create_debugfs_file(qm, tmp_d, HPRE_CLUSTER_CTRL,
1050 					       i + HPRE_CLUSTER_CTRL);
1051 		if (ret)
1052 			return ret;
1053 	}
1054 
1055 	return 0;
1056 }
1057 
1058 static int hpre_ctrl_debug_init(struct hisi_qm *qm)
1059 {
1060 	int ret;
1061 
1062 	ret = hpre_create_debugfs_file(qm, NULL, HPRE_CLEAR_ENABLE,
1063 				       HPRE_CLEAR_ENABLE);
1064 	if (ret)
1065 		return ret;
1066 
1067 	ret = hpre_pf_comm_regs_debugfs_init(qm);
1068 	if (ret)
1069 		return ret;
1070 
1071 	return hpre_cluster_debugfs_init(qm);
1072 }
1073 
1074 static void hpre_dfx_debug_init(struct hisi_qm *qm)
1075 {
1076 	struct dfx_diff_registers *hpre_regs = qm->debug.acc_diff_regs;
1077 	struct hpre *hpre = container_of(qm, struct hpre, qm);
1078 	struct hpre_dfx *dfx = hpre->debug.dfx;
1079 	struct dentry *parent;
1080 	int i;
1081 
1082 	parent = debugfs_create_dir("hpre_dfx", qm->debug.debug_root);
1083 	for (i = 0; i < HPRE_DFX_FILE_NUM; i++) {
1084 		dfx[i].type = i;
1085 		debugfs_create_file(hpre_dfx_files[i], 0644, parent, &dfx[i],
1086 				    &hpre_atomic64_ops);
1087 	}
1088 
1089 	if (qm->fun_type == QM_HW_PF && hpre_regs)
1090 		debugfs_create_file("diff_regs", 0444, parent,
1091 				      qm, &hpre_diff_regs_fops);
1092 }
1093 
1094 static int hpre_debugfs_init(struct hisi_qm *qm)
1095 {
1096 	struct device *dev = &qm->pdev->dev;
1097 	int ret;
1098 
1099 	qm->debug.debug_root = debugfs_create_dir(dev_name(dev),
1100 						  hpre_debugfs_root);
1101 
1102 	qm->debug.sqe_mask_offset = HPRE_SQE_MASK_OFFSET;
1103 	qm->debug.sqe_mask_len = HPRE_SQE_MASK_LEN;
1104 	ret = hisi_qm_diff_regs_init(qm, hpre_diff_regs,
1105 				ARRAY_SIZE(hpre_diff_regs));
1106 	if (ret) {
1107 		dev_warn(dev, "Failed to init HPRE diff regs!\n");
1108 		goto debugfs_remove;
1109 	}
1110 
1111 	hisi_qm_debug_init(qm);
1112 
1113 	if (qm->pdev->device == PCI_DEVICE_ID_HUAWEI_HPRE_PF) {
1114 		ret = hpre_ctrl_debug_init(qm);
1115 		if (ret)
1116 			goto failed_to_create;
1117 	}
1118 
1119 	hpre_dfx_debug_init(qm);
1120 
1121 	return 0;
1122 
1123 failed_to_create:
1124 	hisi_qm_diff_regs_uninit(qm, ARRAY_SIZE(hpre_diff_regs));
1125 debugfs_remove:
1126 	debugfs_remove_recursive(qm->debug.debug_root);
1127 	return ret;
1128 }
1129 
1130 static void hpre_debugfs_exit(struct hisi_qm *qm)
1131 {
1132 	hisi_qm_diff_regs_uninit(qm, ARRAY_SIZE(hpre_diff_regs));
1133 
1134 	debugfs_remove_recursive(qm->debug.debug_root);
1135 }
1136 
1137 static int hpre_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)
1138 {
1139 	int ret;
1140 
1141 	if (pdev->revision == QM_HW_V1) {
1142 		pci_warn(pdev, "HPRE version 1 is not supported!\n");
1143 		return -EINVAL;
1144 	}
1145 
1146 	qm->mode = uacce_mode;
1147 	qm->pdev = pdev;
1148 	qm->ver = pdev->revision;
1149 	qm->sqe_size = HPRE_SQE_SIZE;
1150 	qm->dev_name = hpre_name;
1151 
1152 	qm->fun_type = (pdev->device == PCI_DEVICE_ID_HUAWEI_HPRE_PF) ?
1153 			QM_HW_PF : QM_HW_VF;
1154 	if (qm->fun_type == QM_HW_PF) {
1155 		qm->qp_base = HPRE_PF_DEF_Q_BASE;
1156 		qm->qp_num = pf_q_num;
1157 		qm->debug.curr_qm_qp_num = pf_q_num;
1158 		qm->qm_list = &hpre_devices;
1159 	}
1160 
1161 	ret = hisi_qm_init(qm);
1162 	if (ret) {
1163 		pci_err(pdev, "Failed to init hpre qm configures!\n");
1164 		return ret;
1165 	}
1166 
1167 	ret = hpre_set_qm_algs(qm);
1168 	if (ret) {
1169 		pci_err(pdev, "Failed to set hpre algs!\n");
1170 		hisi_qm_uninit(qm);
1171 	}
1172 
1173 	return ret;
1174 }
1175 
1176 static int hpre_show_last_regs_init(struct hisi_qm *qm)
1177 {
1178 	int cluster_dfx_regs_num =  ARRAY_SIZE(hpre_cluster_dfx_regs);
1179 	int com_dfx_regs_num = ARRAY_SIZE(hpre_com_dfx_regs);
1180 	u8 clusters_num = hpre_cluster_num(qm);
1181 	struct qm_debug *debug = &qm->debug;
1182 	void __iomem *io_base;
1183 	int i, j, idx;
1184 
1185 	debug->last_words = kcalloc(cluster_dfx_regs_num * clusters_num +
1186 			com_dfx_regs_num, sizeof(unsigned int), GFP_KERNEL);
1187 	if (!debug->last_words)
1188 		return -ENOMEM;
1189 
1190 	for (i = 0; i < com_dfx_regs_num; i++)
1191 		debug->last_words[i] = readl_relaxed(qm->io_base +
1192 						hpre_com_dfx_regs[i].offset);
1193 
1194 	for (i = 0; i < clusters_num; i++) {
1195 		io_base = qm->io_base + hpre_cluster_offsets[i];
1196 		for (j = 0; j < cluster_dfx_regs_num; j++) {
1197 			idx = com_dfx_regs_num + i * cluster_dfx_regs_num + j;
1198 			debug->last_words[idx] = readl_relaxed(
1199 				io_base + hpre_cluster_dfx_regs[j].offset);
1200 		}
1201 	}
1202 
1203 	return 0;
1204 }
1205 
1206 static void hpre_show_last_regs_uninit(struct hisi_qm *qm)
1207 {
1208 	struct qm_debug *debug = &qm->debug;
1209 
1210 	if (qm->fun_type == QM_HW_VF || !debug->last_words)
1211 		return;
1212 
1213 	kfree(debug->last_words);
1214 	debug->last_words = NULL;
1215 }
1216 
1217 static void hpre_show_last_dfx_regs(struct hisi_qm *qm)
1218 {
1219 	int cluster_dfx_regs_num =  ARRAY_SIZE(hpre_cluster_dfx_regs);
1220 	int com_dfx_regs_num = ARRAY_SIZE(hpre_com_dfx_regs);
1221 	u8 clusters_num = hpre_cluster_num(qm);
1222 	struct qm_debug *debug = &qm->debug;
1223 	struct pci_dev *pdev = qm->pdev;
1224 	void __iomem *io_base;
1225 	int i, j, idx;
1226 	u32 val;
1227 
1228 	if (qm->fun_type == QM_HW_VF || !debug->last_words)
1229 		return;
1230 
1231 	/* dumps last word of the debugging registers during controller reset */
1232 	for (i = 0; i < com_dfx_regs_num; i++) {
1233 		val = readl_relaxed(qm->io_base + hpre_com_dfx_regs[i].offset);
1234 		if (debug->last_words[i] != val)
1235 			pci_info(pdev, "Common_core:%s \t= 0x%08x => 0x%08x\n",
1236 			  hpre_com_dfx_regs[i].name, debug->last_words[i], val);
1237 	}
1238 
1239 	for (i = 0; i < clusters_num; i++) {
1240 		io_base = qm->io_base + hpre_cluster_offsets[i];
1241 		for (j = 0; j <  cluster_dfx_regs_num; j++) {
1242 			val = readl_relaxed(io_base +
1243 					     hpre_cluster_dfx_regs[j].offset);
1244 			idx = com_dfx_regs_num + i * cluster_dfx_regs_num + j;
1245 			if (debug->last_words[idx] != val)
1246 				pci_info(pdev, "cluster-%d:%s \t= 0x%08x => 0x%08x\n",
1247 				i, hpre_cluster_dfx_regs[j].name, debug->last_words[idx], val);
1248 		}
1249 	}
1250 }
1251 
1252 static void hpre_log_hw_error(struct hisi_qm *qm, u32 err_sts)
1253 {
1254 	const struct hpre_hw_error *err = hpre_hw_errors;
1255 	struct device *dev = &qm->pdev->dev;
1256 
1257 	while (err->msg) {
1258 		if (err->int_msk & err_sts)
1259 			dev_warn(dev, "%s [error status=0x%x] found\n",
1260 				 err->msg, err->int_msk);
1261 		err++;
1262 	}
1263 }
1264 
1265 static u32 hpre_get_hw_err_status(struct hisi_qm *qm)
1266 {
1267 	return readl(qm->io_base + HPRE_INT_STATUS);
1268 }
1269 
1270 static void hpre_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts)
1271 {
1272 	u32 nfe;
1273 
1274 	writel(err_sts, qm->io_base + HPRE_HAC_SOURCE_INT);
1275 	nfe = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_NFE_MASK_CAP, qm->cap_ver);
1276 	writel(nfe, qm->io_base + HPRE_RAS_NFE_ENB);
1277 }
1278 
1279 static void hpre_open_axi_master_ooo(struct hisi_qm *qm)
1280 {
1281 	u32 value;
1282 
1283 	value = readl(qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB);
1284 	writel(value & ~HPRE_AM_OOO_SHUTDOWN_ENABLE,
1285 	       qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB);
1286 	writel(value | HPRE_AM_OOO_SHUTDOWN_ENABLE,
1287 	       qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB);
1288 }
1289 
1290 static void hpre_err_info_init(struct hisi_qm *qm)
1291 {
1292 	struct hisi_qm_err_info *err_info = &qm->err_info;
1293 
1294 	err_info->fe = HPRE_HAC_RAS_FE_ENABLE;
1295 	err_info->ce = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_QM_CE_MASK_CAP, qm->cap_ver);
1296 	err_info->nfe = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_QM_NFE_MASK_CAP, qm->cap_ver);
1297 	err_info->ecc_2bits_mask = HPRE_CORE_ECC_2BIT_ERR | HPRE_OOO_ECC_2BIT_ERR;
1298 	err_info->dev_shutdown_mask = hisi_qm_get_hw_info(qm, hpre_basic_info,
1299 			HPRE_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver);
1300 	err_info->qm_shutdown_mask = hisi_qm_get_hw_info(qm, hpre_basic_info,
1301 			HPRE_QM_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver);
1302 	err_info->qm_reset_mask = hisi_qm_get_hw_info(qm, hpre_basic_info,
1303 			HPRE_QM_RESET_MASK_CAP, qm->cap_ver);
1304 	err_info->dev_reset_mask = hisi_qm_get_hw_info(qm, hpre_basic_info,
1305 			HPRE_RESET_MASK_CAP, qm->cap_ver);
1306 	err_info->msi_wr_port = HPRE_WR_MSI_PORT;
1307 	err_info->acpi_rst = "HRST";
1308 }
1309 
1310 static const struct hisi_qm_err_ini hpre_err_ini = {
1311 	.hw_init		= hpre_set_user_domain_and_cache,
1312 	.hw_err_enable		= hpre_hw_error_enable,
1313 	.hw_err_disable		= hpre_hw_error_disable,
1314 	.get_dev_hw_err_status	= hpre_get_hw_err_status,
1315 	.clear_dev_hw_err_status = hpre_clear_hw_err_status,
1316 	.log_dev_hw_err		= hpre_log_hw_error,
1317 	.open_axi_master_ooo	= hpre_open_axi_master_ooo,
1318 	.open_sva_prefetch	= hpre_open_sva_prefetch,
1319 	.close_sva_prefetch	= hpre_close_sva_prefetch,
1320 	.show_last_dfx_regs	= hpre_show_last_dfx_regs,
1321 	.err_info_init		= hpre_err_info_init,
1322 };
1323 
1324 static int hpre_pf_probe_init(struct hpre *hpre)
1325 {
1326 	struct hisi_qm *qm = &hpre->qm;
1327 	int ret;
1328 
1329 	ret = hpre_set_user_domain_and_cache(qm);
1330 	if (ret)
1331 		return ret;
1332 
1333 	hpre_open_sva_prefetch(qm);
1334 
1335 	qm->err_ini = &hpre_err_ini;
1336 	qm->err_ini->err_info_init(qm);
1337 	hisi_qm_dev_err_init(qm);
1338 	ret = hpre_show_last_regs_init(qm);
1339 	if (ret)
1340 		pci_err(qm->pdev, "Failed to init last word regs!\n");
1341 
1342 	return ret;
1343 }
1344 
1345 static int hpre_probe_init(struct hpre *hpre)
1346 {
1347 	u32 type_rate = HPRE_SHAPER_TYPE_RATE;
1348 	struct hisi_qm *qm = &hpre->qm;
1349 	int ret;
1350 
1351 	if (qm->fun_type == QM_HW_PF) {
1352 		ret = hpre_pf_probe_init(hpre);
1353 		if (ret)
1354 			return ret;
1355 		/* Enable shaper type 0 */
1356 		if (qm->ver >= QM_HW_V3) {
1357 			type_rate |= QM_SHAPER_ENABLE;
1358 			qm->type_rate = type_rate;
1359 		}
1360 	}
1361 
1362 	return 0;
1363 }
1364 
1365 static int hpre_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1366 {
1367 	struct hisi_qm *qm;
1368 	struct hpre *hpre;
1369 	int ret;
1370 
1371 	hpre = devm_kzalloc(&pdev->dev, sizeof(*hpre), GFP_KERNEL);
1372 	if (!hpre)
1373 		return -ENOMEM;
1374 
1375 	qm = &hpre->qm;
1376 	ret = hpre_qm_init(qm, pdev);
1377 	if (ret) {
1378 		pci_err(pdev, "Failed to init HPRE QM (%d)!\n", ret);
1379 		return ret;
1380 	}
1381 
1382 	ret = hpre_probe_init(hpre);
1383 	if (ret) {
1384 		pci_err(pdev, "Failed to probe (%d)!\n", ret);
1385 		goto err_with_qm_init;
1386 	}
1387 
1388 	ret = hisi_qm_start(qm);
1389 	if (ret)
1390 		goto err_with_err_init;
1391 
1392 	ret = hpre_debugfs_init(qm);
1393 	if (ret)
1394 		dev_warn(&pdev->dev, "init debugfs fail!\n");
1395 
1396 	ret = hisi_qm_alg_register(qm, &hpre_devices);
1397 	if (ret < 0) {
1398 		pci_err(pdev, "fail to register algs to crypto!\n");
1399 		goto err_with_qm_start;
1400 	}
1401 
1402 	if (qm->uacce) {
1403 		ret = uacce_register(qm->uacce);
1404 		if (ret) {
1405 			pci_err(pdev, "failed to register uacce (%d)!\n", ret);
1406 			goto err_with_alg_register;
1407 		}
1408 	}
1409 
1410 	if (qm->fun_type == QM_HW_PF && vfs_num) {
1411 		ret = hisi_qm_sriov_enable(pdev, vfs_num);
1412 		if (ret < 0)
1413 			goto err_with_alg_register;
1414 	}
1415 
1416 	hisi_qm_pm_init(qm);
1417 
1418 	return 0;
1419 
1420 err_with_alg_register:
1421 	hisi_qm_alg_unregister(qm, &hpre_devices);
1422 
1423 err_with_qm_start:
1424 	hpre_debugfs_exit(qm);
1425 	hisi_qm_stop(qm, QM_NORMAL);
1426 
1427 err_with_err_init:
1428 	hpre_show_last_regs_uninit(qm);
1429 	hisi_qm_dev_err_uninit(qm);
1430 
1431 err_with_qm_init:
1432 	hisi_qm_uninit(qm);
1433 
1434 	return ret;
1435 }
1436 
1437 static void hpre_remove(struct pci_dev *pdev)
1438 {
1439 	struct hisi_qm *qm = pci_get_drvdata(pdev);
1440 	int ret;
1441 
1442 	hisi_qm_pm_uninit(qm);
1443 	hisi_qm_wait_task_finish(qm, &hpre_devices);
1444 	hisi_qm_alg_unregister(qm, &hpre_devices);
1445 	if (qm->fun_type == QM_HW_PF && qm->vfs_num) {
1446 		ret = hisi_qm_sriov_disable(pdev, true);
1447 		if (ret) {
1448 			pci_err(pdev, "Disable SRIOV fail!\n");
1449 			return;
1450 		}
1451 	}
1452 
1453 	hpre_debugfs_exit(qm);
1454 	hisi_qm_stop(qm, QM_NORMAL);
1455 
1456 	if (qm->fun_type == QM_HW_PF) {
1457 		hpre_cnt_regs_clear(qm);
1458 		qm->debug.curr_qm_qp_num = 0;
1459 		hpre_show_last_regs_uninit(qm);
1460 		hisi_qm_dev_err_uninit(qm);
1461 	}
1462 
1463 	hisi_qm_uninit(qm);
1464 }
1465 
1466 static const struct dev_pm_ops hpre_pm_ops = {
1467 	SET_RUNTIME_PM_OPS(hisi_qm_suspend, hisi_qm_resume, NULL)
1468 };
1469 
1470 static const struct pci_error_handlers hpre_err_handler = {
1471 	.error_detected		= hisi_qm_dev_err_detected,
1472 	.slot_reset		= hisi_qm_dev_slot_reset,
1473 	.reset_prepare		= hisi_qm_reset_prepare,
1474 	.reset_done		= hisi_qm_reset_done,
1475 };
1476 
1477 static struct pci_driver hpre_pci_driver = {
1478 	.name			= hpre_name,
1479 	.id_table		= hpre_dev_ids,
1480 	.probe			= hpre_probe,
1481 	.remove			= hpre_remove,
1482 	.sriov_configure	= IS_ENABLED(CONFIG_PCI_IOV) ?
1483 				  hisi_qm_sriov_configure : NULL,
1484 	.err_handler		= &hpre_err_handler,
1485 	.shutdown		= hisi_qm_dev_shutdown,
1486 	.driver.pm		= &hpre_pm_ops,
1487 };
1488 
1489 struct pci_driver *hisi_hpre_get_pf_driver(void)
1490 {
1491 	return &hpre_pci_driver;
1492 }
1493 EXPORT_SYMBOL_GPL(hisi_hpre_get_pf_driver);
1494 
1495 static void hpre_register_debugfs(void)
1496 {
1497 	if (!debugfs_initialized())
1498 		return;
1499 
1500 	hpre_debugfs_root = debugfs_create_dir(hpre_name, NULL);
1501 }
1502 
1503 static void hpre_unregister_debugfs(void)
1504 {
1505 	debugfs_remove_recursive(hpre_debugfs_root);
1506 }
1507 
1508 static int __init hpre_init(void)
1509 {
1510 	int ret;
1511 
1512 	hisi_qm_init_list(&hpre_devices);
1513 	hpre_register_debugfs();
1514 
1515 	ret = pci_register_driver(&hpre_pci_driver);
1516 	if (ret) {
1517 		hpre_unregister_debugfs();
1518 		pr_err("hpre: can't register hisi hpre driver.\n");
1519 	}
1520 
1521 	return ret;
1522 }
1523 
1524 static void __exit hpre_exit(void)
1525 {
1526 	pci_unregister_driver(&hpre_pci_driver);
1527 	hpre_unregister_debugfs();
1528 }
1529 
1530 module_init(hpre_init);
1531 module_exit(hpre_exit);
1532 
1533 MODULE_LICENSE("GPL v2");
1534 MODULE_AUTHOR("Zaibo Xu <xuzaibo@huawei.com>");
1535 MODULE_AUTHOR("Meng Yu <yumeng18@huawei.com>");
1536 MODULE_DESCRIPTION("Driver for HiSilicon HPRE accelerator");
1537