1 /*
2  * This file is part of the Chelsio T6 Crypto driver for Linux.
3  *
4  * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
5  *
6  * This software is available to you under a choice of one of two
7  * licenses.  You may choose to be licensed under the terms of the GNU
8  * General Public License (GPL) Version 2, available from the file
9  * COPYING in the main directory of this source tree, or the
10  * OpenIB.org BSD license below:
11  *
12  *     Redistribution and use in source and binary forms, with or
13  *     without modification, are permitted provided that the following
14  *     conditions are met:
15  *
16  *      - Redistributions of source code must retain the above
17  *        copyright notice, this list of conditions and the following
18  *        disclaimer.
19  *
20  *      - Redistributions in binary form must reproduce the above
21  *        copyright notice, this list of conditions and the following
22  *        disclaimer in the documentation and/or other materials
23  *        provided with the distribution.
24  *
25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32  * SOFTWARE.
33  *
34  */
35 
36 #ifndef __CHCR_CRYPTO_H__
37 #define __CHCR_CRYPTO_H__
38 
39 #define GHASH_BLOCK_SIZE    16
40 #define GHASH_DIGEST_SIZE   16
41 
42 #define CCM_B0_SIZE             16
43 #define CCM_AAD_FIELD_SIZE      2
44 // 511 - 16(For IV)
45 #define T6_MAX_AAD_SIZE 495
46 
47 
48 /* Define following if h/w is not dropping the AAD and IV data before
49  * giving the processed data
50  */
51 
52 #define CHCR_CRA_PRIORITY 500
53 #define CHCR_AEAD_PRIORITY 6000
54 #define CHCR_AES_MAX_KEY_LEN  (2 * (AES_MAX_KEY_SIZE)) /* consider xts */
55 #define CHCR_MAX_CRYPTO_IV_LEN 16 /* AES IV len */
56 
57 #define CHCR_MAX_AUTHENC_AES_KEY_LEN 32 /* max aes key length*/
58 #define CHCR_MAX_AUTHENC_SHA_KEY_LEN 128 /* max sha key length*/
59 
60 #define CHCR_GIVENCRYPT_OP 2
61 /* CPL/SCMD parameters */
62 
63 #define CHCR_ENCRYPT_OP 0
64 #define CHCR_DECRYPT_OP 1
65 
66 #define CHCR_SCMD_SEQ_NO_CTRL_32BIT     1
67 #define CHCR_SCMD_SEQ_NO_CTRL_48BIT     2
68 #define CHCR_SCMD_SEQ_NO_CTRL_64BIT     3
69 
70 #define CHCR_SCMD_PROTO_VERSION_GENERIC 4
71 
72 #define CHCR_SCMD_AUTH_CTRL_AUTH_CIPHER 0
73 #define CHCR_SCMD_AUTH_CTRL_CIPHER_AUTH 1
74 
75 #define CHCR_SCMD_CIPHER_MODE_NOP               0
76 #define CHCR_SCMD_CIPHER_MODE_AES_CBC           1
77 #define CHCR_SCMD_CIPHER_MODE_AES_GCM           2
78 #define CHCR_SCMD_CIPHER_MODE_AES_CTR           3
79 #define CHCR_SCMD_CIPHER_MODE_GENERIC_AES       4
80 #define CHCR_SCMD_CIPHER_MODE_AES_XTS           6
81 #define CHCR_SCMD_CIPHER_MODE_AES_CCM           7
82 
83 #define CHCR_SCMD_AUTH_MODE_NOP             0
84 #define CHCR_SCMD_AUTH_MODE_SHA1            1
85 #define CHCR_SCMD_AUTH_MODE_SHA224          2
86 #define CHCR_SCMD_AUTH_MODE_SHA256          3
87 #define CHCR_SCMD_AUTH_MODE_GHASH           4
88 #define CHCR_SCMD_AUTH_MODE_SHA512_224      5
89 #define CHCR_SCMD_AUTH_MODE_SHA512_256      6
90 #define CHCR_SCMD_AUTH_MODE_SHA512_384      7
91 #define CHCR_SCMD_AUTH_MODE_SHA512_512      8
92 #define CHCR_SCMD_AUTH_MODE_CBCMAC          9
93 #define CHCR_SCMD_AUTH_MODE_CMAC            10
94 
95 #define CHCR_SCMD_HMAC_CTRL_NOP             0
96 #define CHCR_SCMD_HMAC_CTRL_NO_TRUNC        1
97 #define CHCR_SCMD_HMAC_CTRL_TRUNC_RFC4366   2
98 #define CHCR_SCMD_HMAC_CTRL_IPSEC_96BIT     3
99 #define CHCR_SCMD_HMAC_CTRL_PL1		    4
100 #define CHCR_SCMD_HMAC_CTRL_PL2		    5
101 #define CHCR_SCMD_HMAC_CTRL_PL3		    6
102 #define CHCR_SCMD_HMAC_CTRL_DIV2	    7
103 #define VERIFY_HW 0
104 #define VERIFY_SW 1
105 
106 #define CHCR_SCMD_IVGEN_CTRL_HW             0
107 #define CHCR_SCMD_IVGEN_CTRL_SW             1
108 /* This are not really mac key size. They are intermediate values
109  * of sha engine and its size
110  */
111 #define CHCR_KEYCTX_MAC_KEY_SIZE_128        0
112 #define CHCR_KEYCTX_MAC_KEY_SIZE_160        1
113 #define CHCR_KEYCTX_MAC_KEY_SIZE_192        2
114 #define CHCR_KEYCTX_MAC_KEY_SIZE_256        3
115 #define CHCR_KEYCTX_MAC_KEY_SIZE_512        4
116 #define CHCR_KEYCTX_CIPHER_KEY_SIZE_128     0
117 #define CHCR_KEYCTX_CIPHER_KEY_SIZE_192     1
118 #define CHCR_KEYCTX_CIPHER_KEY_SIZE_256     2
119 #define CHCR_KEYCTX_NO_KEY                  15
120 
121 #define CHCR_CPL_FW4_PLD_IV_OFFSET          (5 * 64) /* bytes. flt #5 and #6 */
122 #define CHCR_CPL_FW4_PLD_HASH_RESULT_OFFSET (7 * 64) /* bytes. flt #7 */
123 #define CHCR_CPL_FW4_PLD_DATA_SIZE          (4 * 64) /* bytes. flt #4 to #7 */
124 
125 #define KEY_CONTEXT_HDR_SALT_AND_PAD	    16
126 #define flits_to_bytes(x)  (x * 8)
127 
128 #define IV_NOP                  0
129 #define IV_IMMEDIATE            1
130 #define IV_DSGL			2
131 
132 #define AEAD_H_SIZE             16
133 
134 #define CRYPTO_ALG_SUB_TYPE_MASK            0x0f000000
135 #define CRYPTO_ALG_SUB_TYPE_HASH_HMAC       0x01000000
136 #define CRYPTO_ALG_SUB_TYPE_AEAD_RFC4106    0x02000000
137 #define CRYPTO_ALG_SUB_TYPE_AEAD_GCM	    0x03000000
138 #define CRYPTO_ALG_SUB_TYPE_CBC_SHA	    0x04000000
139 #define CRYPTO_ALG_SUB_TYPE_AEAD_CCM        0x05000000
140 #define CRYPTO_ALG_SUB_TYPE_AEAD_RFC4309    0x06000000
141 #define CRYPTO_ALG_SUB_TYPE_CBC_NULL	    0x07000000
142 #define CRYPTO_ALG_SUB_TYPE_CTR             0x08000000
143 #define CRYPTO_ALG_SUB_TYPE_CTR_RFC3686     0x09000000
144 #define CRYPTO_ALG_SUB_TYPE_XTS		    0x0a000000
145 #define CRYPTO_ALG_SUB_TYPE_CBC		    0x0b000000
146 #define CRYPTO_ALG_SUB_TYPE_CTR_SHA	    0x0c000000
147 #define CRYPTO_ALG_SUB_TYPE_CTR_NULL   0x0d000000
148 #define CRYPTO_ALG_TYPE_HMAC (CRYPTO_ALG_TYPE_AHASH |\
149 			      CRYPTO_ALG_SUB_TYPE_HASH_HMAC)
150 
151 #define MAX_SCRATCH_PAD_SIZE    32
152 
153 #define CHCR_HASH_MAX_BLOCK_SIZE_64  64
154 #define CHCR_HASH_MAX_BLOCK_SIZE_128 128
155 #define CHCR_SRC_SG_SIZE (0x10000 - sizeof(int))
156 #define CHCR_DST_SG_SIZE 2048
157 
158 static inline struct chcr_context *a_ctx(struct crypto_aead *tfm)
159 {
160 	return crypto_aead_ctx(tfm);
161 }
162 
163 static inline struct chcr_context *c_ctx(struct crypto_ablkcipher *tfm)
164 {
165 	return crypto_ablkcipher_ctx(tfm);
166 }
167 
168 static inline struct chcr_context *h_ctx(struct crypto_ahash *tfm)
169 {
170 	return crypto_tfm_ctx(crypto_ahash_tfm(tfm));
171 }
172 
173 struct ablk_ctx {
174 	struct crypto_sync_skcipher *sw_cipher;
175 	struct crypto_cipher *aes_generic;
176 	__be32 key_ctx_hdr;
177 	unsigned int enckey_len;
178 	unsigned char ciph_mode;
179 	u8 key[CHCR_AES_MAX_KEY_LEN];
180 	u8 nonce[4];
181 	u8 rrkey[AES_MAX_KEY_SIZE];
182 };
183 struct chcr_aead_reqctx {
184 	struct	sk_buff	*skb;
185 	dma_addr_t iv_dma;
186 	dma_addr_t b0_dma;
187 	unsigned int b0_len;
188 	unsigned int op;
189 	u16 imm;
190 	u16 verify;
191 	u8 iv[CHCR_MAX_CRYPTO_IV_LEN + MAX_SCRATCH_PAD_SIZE];
192 	u8 *scratch_pad;
193 };
194 
195 struct ulptx_walk {
196 	struct ulptx_sgl *sgl;
197 	unsigned int nents;
198 	unsigned int pair_idx;
199 	unsigned int last_sg_len;
200 	struct scatterlist *last_sg;
201 	struct ulptx_sge_pair *pair;
202 
203 };
204 
205 struct dsgl_walk {
206 	unsigned int nents;
207 	unsigned int last_sg_len;
208 	struct scatterlist *last_sg;
209 	struct cpl_rx_phys_dsgl *dsgl;
210 	struct phys_sge_pairs *to;
211 };
212 
213 struct chcr_gcm_ctx {
214 	u8 ghash_h[AEAD_H_SIZE];
215 };
216 
217 struct chcr_authenc_ctx {
218 	u8 dec_rrkey[AES_MAX_KEY_SIZE];
219 	u8 h_iopad[2 * CHCR_HASH_MAX_DIGEST_SIZE];
220 	unsigned char auth_mode;
221 };
222 
223 struct __aead_ctx {
224 	struct chcr_gcm_ctx gcm[0];
225 	struct chcr_authenc_ctx authenc[0];
226 };
227 
228 struct chcr_aead_ctx {
229 	__be32 key_ctx_hdr;
230 	unsigned int enckey_len;
231 	struct crypto_aead *sw_cipher;
232 	u8 salt[MAX_SALT];
233 	u8 key[CHCR_AES_MAX_KEY_LEN];
234 	u8 nonce[4];
235 	u16 hmac_ctrl;
236 	u16 mayverify;
237 	struct	__aead_ctx ctx[0];
238 };
239 
240 struct hmac_ctx {
241 	struct crypto_shash *base_hash;
242 	u8 ipad[CHCR_HASH_MAX_BLOCK_SIZE_128];
243 	u8 opad[CHCR_HASH_MAX_BLOCK_SIZE_128];
244 };
245 
246 struct __crypto_ctx {
247 	struct hmac_ctx hmacctx[0];
248 	struct ablk_ctx ablkctx[0];
249 	struct chcr_aead_ctx aeadctx[0];
250 };
251 
252 struct chcr_context {
253 	struct chcr_dev *dev;
254 	unsigned char tx_qidx;
255 	unsigned char rx_qidx;
256 	unsigned char tx_chan_id;
257 	unsigned char pci_chan_id;
258 	struct __crypto_ctx crypto_ctx[0];
259 };
260 
261 struct chcr_hctx_per_wr {
262 	struct scatterlist *srcsg;
263 	struct sk_buff *skb;
264 	dma_addr_t dma_addr;
265 	u32 dma_len;
266 	unsigned int src_ofst;
267 	unsigned int processed;
268 	u32 result;
269 	u8 is_sg_map;
270 	u8 imm;
271 	/*Final callback called. Driver cannot rely on nbytes to decide
272 	 * final call
273 	 */
274 	u8 isfinal;
275 };
276 
277 struct chcr_ahash_req_ctx {
278 	struct chcr_hctx_per_wr hctx_wr;
279 	u8 *reqbfr;
280 	u8 *skbfr;
281 	/* SKB which is being sent to the hardware for processing */
282 	u64 data_len;  /* Data len till time */
283 	u8 reqlen;
284 	u8 partial_hash[CHCR_HASH_MAX_DIGEST_SIZE];
285 	u8 bfr1[CHCR_HASH_MAX_BLOCK_SIZE_128];
286 	u8 bfr2[CHCR_HASH_MAX_BLOCK_SIZE_128];
287 };
288 
289 struct chcr_blkcipher_req_ctx {
290 	struct sk_buff *skb;
291 	struct scatterlist *dstsg;
292 	unsigned int processed;
293 	unsigned int last_req_len;
294 	struct scatterlist *srcsg;
295 	unsigned int src_ofst;
296 	unsigned int dst_ofst;
297 	unsigned int op;
298 	u16 imm;
299 	u8 iv[CHCR_MAX_CRYPTO_IV_LEN];
300 };
301 
302 struct chcr_alg_template {
303 	u32 type;
304 	u32 is_registered;
305 	union {
306 		struct crypto_alg crypto;
307 		struct ahash_alg hash;
308 		struct aead_alg aead;
309 	} alg;
310 };
311 
312 typedef struct sk_buff *(*create_wr_t)(struct aead_request *req,
313 				       unsigned short qid,
314 				       int size);
315 
316 void chcr_verify_tag(struct aead_request *req, u8 *input, int *err);
317 int chcr_aead_dma_map(struct device *dev, struct aead_request *req,
318 		      unsigned short op_type);
319 void chcr_aead_dma_unmap(struct device *dev, struct aead_request *req,
320 			 unsigned short op_type);
321 void chcr_add_aead_dst_ent(struct aead_request *req,
322 			   struct cpl_rx_phys_dsgl *phys_cpl,
323 			   unsigned short qid);
324 void chcr_add_aead_src_ent(struct aead_request *req, struct ulptx_sgl *ulptx);
325 void chcr_add_cipher_src_ent(struct ablkcipher_request *req,
326 			     void *ulptx,
327 			     struct  cipher_wr_param *wrparam);
328 int chcr_cipher_dma_map(struct device *dev, struct ablkcipher_request *req);
329 void chcr_cipher_dma_unmap(struct device *dev, struct ablkcipher_request *req);
330 void chcr_add_cipher_dst_ent(struct ablkcipher_request *req,
331 			     struct cpl_rx_phys_dsgl *phys_cpl,
332 			     struct  cipher_wr_param *wrparam,
333 			     unsigned short qid);
334 int sg_nents_len_skip(struct scatterlist *sg, u64 len, u64 skip);
335 void chcr_add_hash_src_ent(struct ahash_request *req, struct ulptx_sgl *ulptx,
336 			   struct hash_wr_param *param);
337 int chcr_hash_dma_map(struct device *dev, struct ahash_request *req);
338 void chcr_hash_dma_unmap(struct device *dev, struct ahash_request *req);
339 void chcr_aead_common_exit(struct aead_request *req);
340 #endif /* __CHCR_CRYPTO_H__ */
341