1 /*
2  * This file is part of the Chelsio T6 Crypto driver for Linux.
3  *
4  * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
5  *
6  * This software is available to you under a choice of one of two
7  * licenses.  You may choose to be licensed under the terms of the GNU
8  * General Public License (GPL) Version 2, available from the file
9  * COPYING in the main directory of this source tree, or the
10  * OpenIB.org BSD license below:
11  *
12  *     Redistribution and use in source and binary forms, with or
13  *     without modification, are permitted provided that the following
14  *     conditions are met:
15  *
16  *      - Redistributions of source code must retain the above
17  *        copyright notice, this list of conditions and the following
18  *        disclaimer.
19  *
20  *      - Redistributions in binary form must reproduce the above
21  *        copyright notice, this list of conditions and the following
22  *        disclaimer in the documentation and/or other materials
23  *        provided with the distribution.
24  *
25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32  * SOFTWARE.
33  *
34  */
35 
36 #ifndef __CHCR_CORE_H__
37 #define __CHCR_CORE_H__
38 
39 #include <crypto/algapi.h>
40 #include "t4_hw.h"
41 #include "cxgb4.h"
42 #include "cxgb4_uld.h"
43 
44 #define DRV_MODULE_NAME "chcr"
45 #define DRV_VERSION "1.0.0.0"
46 
47 #define MAX_PENDING_REQ_TO_HW 20
48 #define CHCR_TEST_RESPONSE_TIMEOUT 1000
49 
50 #define PAD_ERROR_BIT		1
51 #define CHK_PAD_ERR_BIT(x)	(((x) >> PAD_ERROR_BIT) & 1)
52 
53 #define MAC_ERROR_BIT		0
54 #define CHK_MAC_ERR_BIT(x)	(((x) >> MAC_ERROR_BIT) & 1)
55 #define MAX_SALT                4
56 #define WR_MIN_LEN (sizeof(struct chcr_wr) + \
57 		    sizeof(struct cpl_rx_phys_dsgl) + \
58 		    sizeof(struct ulptx_sgl))
59 
60 #define padap(dev) pci_get_drvdata(dev->u_ctx->lldi.pdev)
61 
62 struct uld_ctx;
63 
64 struct _key_ctx {
65 	__be32 ctx_hdr;
66 	u8 salt[MAX_SALT];
67 	__be64 reserverd;
68 	unsigned char key[0];
69 };
70 
71 struct chcr_wr {
72 	struct fw_crypto_lookaside_wr wreq;
73 	struct ulp_txpkt ulptx;
74 	struct ulptx_idata sc_imm;
75 	struct cpl_tx_sec_pdu sec_cpl;
76 	struct _key_ctx key_ctx;
77 };
78 
79 struct chcr_dev {
80 	spinlock_t lock_chcr_dev;
81 	struct uld_ctx *u_ctx;
82 	unsigned char tx_channel_id;
83 	unsigned char rx_channel_id;
84 };
85 
86 struct uld_ctx {
87 	struct list_head entry;
88 	struct cxgb4_lld_info lldi;
89 	struct chcr_dev *dev;
90 };
91 
92 struct uld_ctx * assign_chcr_device(void);
93 int chcr_send_wr(struct sk_buff *skb);
94 int start_crypto(void);
95 int stop_crypto(void);
96 int chcr_uld_rx_handler(void *handle, const __be64 *rsp,
97 			const struct pkt_gl *pgl);
98 int chcr_handle_resp(struct crypto_async_request *req, unsigned char *input,
99 		     int err);
100 #endif /* __CHCR_CORE_H__ */
101