1 /*
2  * This file is part of the Chelsio T6 Crypto driver for Linux.
3  *
4  * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
5  *
6  * This software is available to you under a choice of one of two
7  * licenses.  You may choose to be licensed under the terms of the GNU
8  * General Public License (GPL) Version 2, available from the file
9  * COPYING in the main directory of this source tree, or the
10  * OpenIB.org BSD license below:
11  *
12  *     Redistribution and use in source and binary forms, with or
13  *     without modification, are permitted provided that the following
14  *     conditions are met:
15  *
16  *      - Redistributions of source code must retain the above
17  *        copyright notice, this list of conditions and the following
18  *        disclaimer.
19  *
20  *      - Redistributions in binary form must reproduce the above
21  *        copyright notice, this list of conditions and the following
22  *        disclaimer in the documentation and/or other materials
23  *        provided with the distribution.
24  *
25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32  * SOFTWARE.
33  *
34  */
35 
36 #ifndef __CHCR_CORE_H__
37 #define __CHCR_CORE_H__
38 
39 #include <crypto/algapi.h>
40 #include "t4_hw.h"
41 #include "cxgb4.h"
42 #include "t4_msg.h"
43 #include "cxgb4_uld.h"
44 
45 #define DRV_MODULE_NAME "chcr"
46 #define DRV_VERSION "1.0.0.0"
47 
48 #define MAX_PENDING_REQ_TO_HW 20
49 #define CHCR_TEST_RESPONSE_TIMEOUT 1000
50 #define WQ_DETACH_TM	(msecs_to_jiffies(50))
51 #define PAD_ERROR_BIT		1
52 #define CHK_PAD_ERR_BIT(x)	(((x) >> PAD_ERROR_BIT) & 1)
53 
54 #define MAC_ERROR_BIT		0
55 #define CHK_MAC_ERR_BIT(x)	(((x) >> MAC_ERROR_BIT) & 1)
56 #define MAX_SALT                4
57 #define CIP_WR_MIN_LEN (sizeof(struct chcr_wr) + \
58 		    sizeof(struct cpl_rx_phys_dsgl) + \
59 		    sizeof(struct ulptx_sgl) + 16) //IV
60 
61 #define HASH_WR_MIN_LEN (sizeof(struct chcr_wr) + \
62 			DUMMY_BYTES + \
63 		    sizeof(struct ulptx_sgl))
64 struct uld_ctx;
65 
66 struct _key_ctx {
67 	__be32 ctx_hdr;
68 	u8 salt[MAX_SALT];
69 	__be64 iv_to_auth;
70 	unsigned char key[0];
71 };
72 
73 #define KEYCTX_TX_WR_IV_S  55
74 #define KEYCTX_TX_WR_IV_M  0x1ffULL
75 #define KEYCTX_TX_WR_IV_V(x) ((x) << KEYCTX_TX_WR_IV_S)
76 #define KEYCTX_TX_WR_IV_G(x) \
77 	(((x) >> KEYCTX_TX_WR_IV_S) & KEYCTX_TX_WR_IV_M)
78 
79 #define KEYCTX_TX_WR_AAD_S 47
80 #define KEYCTX_TX_WR_AAD_M 0xffULL
81 #define KEYCTX_TX_WR_AAD_V(x) ((x) << KEYCTX_TX_WR_AAD_S)
82 #define KEYCTX_TX_WR_AAD_G(x) (((x) >> KEYCTX_TX_WR_AAD_S) & \
83 				KEYCTX_TX_WR_AAD_M)
84 
85 #define KEYCTX_TX_WR_AADST_S 39
86 #define KEYCTX_TX_WR_AADST_M 0xffULL
87 #define KEYCTX_TX_WR_AADST_V(x) ((x) << KEYCTX_TX_WR_AADST_S)
88 #define KEYCTX_TX_WR_AADST_G(x) \
89 	(((x) >> KEYCTX_TX_WR_AADST_S) & KEYCTX_TX_WR_AADST_M)
90 
91 #define KEYCTX_TX_WR_CIPHER_S 30
92 #define KEYCTX_TX_WR_CIPHER_M 0x1ffULL
93 #define KEYCTX_TX_WR_CIPHER_V(x) ((x) << KEYCTX_TX_WR_CIPHER_S)
94 #define KEYCTX_TX_WR_CIPHER_G(x) \
95 	(((x) >> KEYCTX_TX_WR_CIPHER_S) & KEYCTX_TX_WR_CIPHER_M)
96 
97 #define KEYCTX_TX_WR_CIPHERST_S 23
98 #define KEYCTX_TX_WR_CIPHERST_M 0x7f
99 #define KEYCTX_TX_WR_CIPHERST_V(x) ((x) << KEYCTX_TX_WR_CIPHERST_S)
100 #define KEYCTX_TX_WR_CIPHERST_G(x) \
101 	(((x) >> KEYCTX_TX_WR_CIPHERST_S) & KEYCTX_TX_WR_CIPHERST_M)
102 
103 #define KEYCTX_TX_WR_AUTH_S 14
104 #define KEYCTX_TX_WR_AUTH_M 0x1ff
105 #define KEYCTX_TX_WR_AUTH_V(x) ((x) << KEYCTX_TX_WR_AUTH_S)
106 #define KEYCTX_TX_WR_AUTH_G(x) \
107 	(((x) >> KEYCTX_TX_WR_AUTH_S) & KEYCTX_TX_WR_AUTH_M)
108 
109 #define KEYCTX_TX_WR_AUTHST_S 7
110 #define KEYCTX_TX_WR_AUTHST_M 0x7f
111 #define KEYCTX_TX_WR_AUTHST_V(x) ((x) << KEYCTX_TX_WR_AUTHST_S)
112 #define KEYCTX_TX_WR_AUTHST_G(x) \
113 	(((x) >> KEYCTX_TX_WR_AUTHST_S) & KEYCTX_TX_WR_AUTHST_M)
114 
115 #define KEYCTX_TX_WR_AUTHIN_S 0
116 #define KEYCTX_TX_WR_AUTHIN_M 0x7f
117 #define KEYCTX_TX_WR_AUTHIN_V(x) ((x) << KEYCTX_TX_WR_AUTHIN_S)
118 #define KEYCTX_TX_WR_AUTHIN_G(x) \
119 	(((x) >> KEYCTX_TX_WR_AUTHIN_S) & KEYCTX_TX_WR_AUTHIN_M)
120 
121 #define WQ_RETRY	5
122 struct chcr_driver_data {
123 	struct list_head act_dev;
124 	struct list_head inact_dev;
125 	atomic_t dev_count;
126 	struct mutex drv_mutex;
127 	struct uld_ctx *last_dev;
128 };
129 
130 enum chcr_state {
131 	CHCR_INIT = 0,
132 	CHCR_ATTACH,
133 	CHCR_DETACH,
134 };
135 struct chcr_wr {
136 	struct fw_crypto_lookaside_wr wreq;
137 	struct ulp_txpkt ulptx;
138 	struct ulptx_idata sc_imm;
139 	struct cpl_tx_sec_pdu sec_cpl;
140 	struct _key_ctx key_ctx;
141 };
142 
143 struct chcr_dev {
144 	spinlock_t lock_chcr_dev;
145 	enum chcr_state state;
146 	atomic_t inflight;
147 	int wqretry;
148 	struct delayed_work detach_work;
149 	struct completion detach_comp;
150 	unsigned char tx_channel_id;
151 };
152 
153 struct uld_ctx {
154 	struct list_head entry;
155 	struct cxgb4_lld_info lldi;
156 	struct chcr_dev dev;
157 };
158 
159 struct sge_opaque_hdr {
160 	void *dev;
161 	dma_addr_t addr[MAX_SKB_FRAGS + 1];
162 };
163 
164 struct chcr_ipsec_req {
165 	struct ulp_txpkt ulptx;
166 	struct ulptx_idata sc_imm;
167 	struct cpl_tx_sec_pdu sec_cpl;
168 	struct _key_ctx key_ctx;
169 };
170 
171 struct chcr_ipsec_wr {
172 	struct fw_ulptx_wr wreq;
173 	struct chcr_ipsec_req req;
174 };
175 
176 #define ESN_IV_INSERT_OFFSET 12
177 struct chcr_ipsec_aadiv {
178 	__be32 spi;
179 	u8 seq_no[8];
180 	u8 iv[8];
181 };
182 
183 struct ipsec_sa_entry {
184 	int hmac_ctrl;
185 	u16 esn;
186 	u16 resv;
187 	unsigned int enckey_len;
188 	unsigned int kctx_len;
189 	unsigned int authsize;
190 	__be32 key_ctx_hdr;
191 	char salt[MAX_SALT];
192 	char key[2 * AES_MAX_KEY_SIZE];
193 };
194 
195 /*
196  *      sgl_len - calculates the size of an SGL of the given capacity
197  *      @n: the number of SGL entries
198  *      Calculates the number of flits needed for a scatter/gather list that
199  *      can hold the given number of entries.
200  */
201 static inline unsigned int sgl_len(unsigned int n)
202 {
203 	n--;
204 	return (3 * n) / 2 + (n & 1) + 2;
205 }
206 
207 static inline void *padap(struct chcr_dev *dev)
208 {
209 	struct uld_ctx *u_ctx = container_of(dev, struct uld_ctx, dev);
210 
211 	return pci_get_drvdata(u_ctx->lldi.pdev);
212 }
213 
214 struct uld_ctx *assign_chcr_device(void);
215 int chcr_send_wr(struct sk_buff *skb);
216 int start_crypto(void);
217 int stop_crypto(void);
218 int chcr_uld_rx_handler(void *handle, const __be64 *rsp,
219 			const struct pkt_gl *pgl);
220 int chcr_uld_tx_handler(struct sk_buff *skb, struct net_device *dev);
221 int chcr_handle_resp(struct crypto_async_request *req, unsigned char *input,
222 		     int err);
223 int chcr_ipsec_xmit(struct sk_buff *skb, struct net_device *dev);
224 void chcr_add_xfrmops(const struct cxgb4_lld_info *lld);
225 #endif /* __CHCR_CORE_H__ */
226