1 /*
2  * This file is part of the Chelsio T6 Crypto driver for Linux.
3  *
4  * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
5  *
6  * This software is available to you under a choice of one of two
7  * licenses.  You may choose to be licensed under the terms of the GNU
8  * General Public License (GPL) Version 2, available from the file
9  * COPYING in the main directory of this source tree, or the
10  * OpenIB.org BSD license below:
11  *
12  *     Redistribution and use in source and binary forms, with or
13  *     without modification, are permitted provided that the following
14  *     conditions are met:
15  *
16  *      - Redistributions of source code must retain the above
17  *        copyright notice, this list of conditions and the following
18  *        disclaimer.
19  *
20  *      - Redistributions in binary form must reproduce the above
21  *        copyright notice, this list of conditions and the following
22  *        disclaimer in the documentation and/or other materials
23  *        provided with the distribution.
24  *
25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32  * SOFTWARE.
33  *
34  */
35 
36 #ifndef __CHCR_CORE_H__
37 #define __CHCR_CORE_H__
38 
39 #include <crypto/algapi.h>
40 #include <net/tls.h>
41 #include "t4_hw.h"
42 #include "cxgb4.h"
43 #include "t4_msg.h"
44 #include "cxgb4_uld.h"
45 
46 #define DRV_MODULE_NAME "chcr"
47 #define DRV_VERSION "1.0.0.0-ko"
48 #define DRV_DESC "Chelsio T6 Crypto Co-processor Driver"
49 
50 #define MAX_PENDING_REQ_TO_HW 20
51 #define CHCR_TEST_RESPONSE_TIMEOUT 1000
52 #define WQ_DETACH_TM	(msecs_to_jiffies(50))
53 #define PAD_ERROR_BIT		1
54 #define CHK_PAD_ERR_BIT(x)	(((x) >> PAD_ERROR_BIT) & 1)
55 
56 #define MAC_ERROR_BIT		0
57 #define CHK_MAC_ERR_BIT(x)	(((x) >> MAC_ERROR_BIT) & 1)
58 #define MAX_SALT                4
59 #define CIP_WR_MIN_LEN (sizeof(struct chcr_wr) + \
60 		    sizeof(struct cpl_rx_phys_dsgl) + \
61 		    sizeof(struct ulptx_sgl) + 16) //IV
62 
63 #define HASH_WR_MIN_LEN (sizeof(struct chcr_wr) + \
64 			DUMMY_BYTES + \
65 		    sizeof(struct ulptx_sgl))
66 struct uld_ctx;
67 
68 struct _key_ctx {
69 	__be32 ctx_hdr;
70 	u8 salt[MAX_SALT];
71 	__be64 iv_to_auth;
72 	unsigned char key[];
73 };
74 
75 #define WQ_RETRY	5
76 struct chcr_driver_data {
77 	struct list_head act_dev;
78 	struct list_head inact_dev;
79 	atomic_t dev_count;
80 	struct mutex drv_mutex;
81 	struct uld_ctx *last_dev;
82 };
83 
84 enum chcr_state {
85 	CHCR_INIT = 0,
86 	CHCR_ATTACH,
87 	CHCR_DETACH,
88 };
89 struct chcr_wr {
90 	struct fw_crypto_lookaside_wr wreq;
91 	struct ulp_txpkt ulptx;
92 	struct ulptx_idata sc_imm;
93 	struct cpl_tx_sec_pdu sec_cpl;
94 	struct _key_ctx key_ctx;
95 };
96 
97 struct chcr_dev {
98 	spinlock_t lock_chcr_dev;
99 	enum chcr_state state;
100 	atomic_t inflight;
101 	int wqretry;
102 	struct delayed_work detach_work;
103 	struct completion detach_comp;
104 };
105 
106 struct uld_ctx {
107 	struct list_head entry;
108 	struct cxgb4_lld_info lldi;
109 	struct chcr_dev dev;
110 };
111 
112 /*
113  *      sgl_len - calculates the size of an SGL of the given capacity
114  *      @n: the number of SGL entries
115  *      Calculates the number of flits needed for a scatter/gather list that
116  *      can hold the given number of entries.
117  */
118 static inline unsigned int sgl_len(unsigned int n)
119 {
120 	n--;
121 	return (3 * n) / 2 + (n & 1) + 2;
122 }
123 
124 static inline void *padap(struct chcr_dev *dev)
125 {
126 	struct uld_ctx *u_ctx = container_of(dev, struct uld_ctx, dev);
127 
128 	return pci_get_drvdata(u_ctx->lldi.pdev);
129 }
130 
131 struct uld_ctx *assign_chcr_device(void);
132 int chcr_send_wr(struct sk_buff *skb);
133 int start_crypto(void);
134 int stop_crypto(void);
135 int chcr_uld_rx_handler(void *handle, const __be64 *rsp,
136 			const struct pkt_gl *pgl);
137 int chcr_uld_tx_handler(struct sk_buff *skb, struct net_device *dev);
138 int chcr_handle_resp(struct crypto_async_request *req, unsigned char *input,
139 		     int err);
140 #endif /* __CHCR_CORE_H__ */
141