1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */ 3 4 #ifndef __CC_HW_QUEUE_DEFS_H__ 5 #define __CC_HW_QUEUE_DEFS_H__ 6 7 #include <linux/types.h> 8 9 #include "cc_kernel_regs.h" 10 #include <linux/bitfield.h> 11 12 /****************************************************************************** 13 * DEFINITIONS 14 ******************************************************************************/ 15 16 #define HW_DESC_SIZE_WORDS 6 17 /* Define max. available slots in HW queue */ 18 #define HW_QUEUE_SLOTS_MAX 15 19 20 #define CC_REG_LOW(word, name) \ 21 (CC_DSCRPTR_QUEUE_WORD ## word ## _ ## name ## _BIT_SHIFT) 22 23 #define CC_REG_HIGH(word, name) \ 24 (CC_REG_LOW(word, name) + \ 25 CC_DSCRPTR_QUEUE_WORD ## word ## _ ## name ## _BIT_SIZE - 1) 26 27 #define CC_GENMASK(word, name) \ 28 GENMASK(CC_REG_HIGH(word, name), CC_REG_LOW(word, name)) 29 30 #define WORD0_VALUE CC_GENMASK(0, VALUE) 31 #define WORD0_CPP_CIPHER_MODE CC_GENMASK(0, CPP_CIPHER_MODE) 32 #define WORD1_DIN_CONST_VALUE CC_GENMASK(1, DIN_CONST_VALUE) 33 #define WORD1_DIN_DMA_MODE CC_GENMASK(1, DIN_DMA_MODE) 34 #define WORD1_DIN_SIZE CC_GENMASK(1, DIN_SIZE) 35 #define WORD1_NOT_LAST CC_GENMASK(1, NOT_LAST) 36 #define WORD1_NS_BIT CC_GENMASK(1, NS_BIT) 37 #define WORD1_LOCK_QUEUE CC_GENMASK(1, LOCK_QUEUE) 38 #define WORD2_VALUE CC_GENMASK(2, VALUE) 39 #define WORD3_DOUT_DMA_MODE CC_GENMASK(3, DOUT_DMA_MODE) 40 #define WORD3_DOUT_LAST_IND CC_GENMASK(3, DOUT_LAST_IND) 41 #define WORD3_DOUT_SIZE CC_GENMASK(3, DOUT_SIZE) 42 #define WORD3_HASH_XOR_BIT CC_GENMASK(3, HASH_XOR_BIT) 43 #define WORD3_NS_BIT CC_GENMASK(3, NS_BIT) 44 #define WORD3_QUEUE_LAST_IND CC_GENMASK(3, QUEUE_LAST_IND) 45 #define WORD4_ACK_NEEDED CC_GENMASK(4, ACK_NEEDED) 46 #define WORD4_AES_SEL_N_HASH CC_GENMASK(4, AES_SEL_N_HASH) 47 #define WORD4_AES_XOR_CRYPTO_KEY CC_GENMASK(4, AES_XOR_CRYPTO_KEY) 48 #define WORD4_BYTES_SWAP CC_GENMASK(4, BYTES_SWAP) 49 #define WORD4_CIPHER_CONF0 CC_GENMASK(4, CIPHER_CONF0) 50 #define WORD4_CIPHER_CONF1 CC_GENMASK(4, CIPHER_CONF1) 51 #define WORD4_CIPHER_CONF2 CC_GENMASK(4, CIPHER_CONF2) 52 #define WORD4_CIPHER_DO CC_GENMASK(4, CIPHER_DO) 53 #define WORD4_CIPHER_MODE CC_GENMASK(4, CIPHER_MODE) 54 #define WORD4_CMAC_SIZE0 CC_GENMASK(4, CMAC_SIZE0) 55 #define WORD4_DATA_FLOW_MODE CC_GENMASK(4, DATA_FLOW_MODE) 56 #define WORD4_KEY_SIZE CC_GENMASK(4, KEY_SIZE) 57 #define WORD4_SETUP_OPERATION CC_GENMASK(4, SETUP_OPERATION) 58 #define WORD5_DIN_ADDR_HIGH CC_GENMASK(5, DIN_ADDR_HIGH) 59 #define WORD5_DOUT_ADDR_HIGH CC_GENMASK(5, DOUT_ADDR_HIGH) 60 61 /****************************************************************************** 62 * TYPE DEFINITIONS 63 ******************************************************************************/ 64 65 struct cc_hw_desc { 66 union { 67 u32 word[HW_DESC_SIZE_WORDS]; 68 u16 hword[HW_DESC_SIZE_WORDS * 2]; 69 }; 70 }; 71 72 enum cc_axi_sec { 73 AXI_SECURE = 0, 74 AXI_NOT_SECURE = 1 75 }; 76 77 enum cc_desc_direction { 78 DESC_DIRECTION_ILLEGAL = -1, 79 DESC_DIRECTION_ENCRYPT_ENCRYPT = 0, 80 DESC_DIRECTION_DECRYPT_DECRYPT = 1, 81 DESC_DIRECTION_DECRYPT_ENCRYPT = 3, 82 DESC_DIRECTION_END = S32_MAX, 83 }; 84 85 enum cc_dma_mode { 86 DMA_MODE_NULL = -1, 87 NO_DMA = 0, 88 DMA_SRAM = 1, 89 DMA_DLLI = 2, 90 DMA_MLLI = 3, 91 DMA_MODE_END = S32_MAX, 92 }; 93 94 enum cc_flow_mode { 95 FLOW_MODE_NULL = -1, 96 /* data flows */ 97 BYPASS = 0, 98 DIN_AES_DOUT = 1, 99 AES_to_HASH = 2, 100 AES_and_HASH = 3, 101 DIN_DES_DOUT = 4, 102 DES_to_HASH = 5, 103 DES_and_HASH = 6, 104 DIN_HASH = 7, 105 DIN_HASH_and_BYPASS = 8, 106 AESMAC_and_BYPASS = 9, 107 AES_to_HASH_and_DOUT = 10, 108 DIN_RC4_DOUT = 11, 109 DES_to_HASH_and_DOUT = 12, 110 AES_to_AES_to_HASH_and_DOUT = 13, 111 AES_to_AES_to_HASH = 14, 112 AES_to_HASH_and_AES = 15, 113 DIN_SM4_DOUT = 16, 114 DIN_AES_AESMAC = 17, 115 HASH_to_DOUT = 18, 116 /* setup flows */ 117 S_DIN_to_AES = 32, 118 S_DIN_to_AES2 = 33, 119 S_DIN_to_DES = 34, 120 S_DIN_to_RC4 = 35, 121 S_DIN_to_SM4 = 36, 122 S_DIN_to_HASH = 37, 123 S_AES_to_DOUT = 38, 124 S_AES2_to_DOUT = 39, 125 S_SM4_to_DOUT = 40, 126 S_RC4_to_DOUT = 41, 127 S_DES_to_DOUT = 42, 128 S_HASH_to_DOUT = 43, 129 SET_FLOW_ID = 44, 130 FLOW_MODE_END = S32_MAX, 131 }; 132 133 enum cc_setup_op { 134 SETUP_LOAD_NOP = 0, 135 SETUP_LOAD_STATE0 = 1, 136 SETUP_LOAD_STATE1 = 2, 137 SETUP_LOAD_STATE2 = 3, 138 SETUP_LOAD_KEY0 = 4, 139 SETUP_LOAD_XEX_KEY = 5, 140 SETUP_WRITE_STATE0 = 8, 141 SETUP_WRITE_STATE1 = 9, 142 SETUP_WRITE_STATE2 = 10, 143 SETUP_WRITE_STATE3 = 11, 144 SETUP_OP_END = S32_MAX, 145 }; 146 147 enum cc_hash_conf_pad { 148 HASH_PADDING_DISABLED = 0, 149 HASH_PADDING_ENABLED = 1, 150 HASH_DIGEST_RESULT_LITTLE_ENDIAN = 2, 151 HASH_CONFIG1_PADDING_RESERVE32 = S32_MAX, 152 }; 153 154 enum cc_aes_mac_selector { 155 AES_SK = 1, 156 AES_CMAC_INIT = 2, 157 AES_CMAC_SIZE0 = 3, 158 AES_MAC_END = S32_MAX, 159 }; 160 161 #define HW_KEY_MASK_CIPHER_DO 0x3 162 #define HW_KEY_SHIFT_CIPHER_CFG2 2 163 164 /* HwCryptoKey[1:0] is mapped to cipher_do[1:0] */ 165 /* HwCryptoKey[2:3] is mapped to cipher_config2[1:0] */ 166 enum cc_hw_crypto_key { 167 USER_KEY = 0, /* 0x0000 */ 168 ROOT_KEY = 1, /* 0x0001 */ 169 PROVISIONING_KEY = 2, /* 0x0010 */ /* ==KCP */ 170 SESSION_KEY = 3, /* 0x0011 */ 171 RESERVED_KEY = 4, /* NA */ 172 PLATFORM_KEY = 5, /* 0x0101 */ 173 CUSTOMER_KEY = 6, /* 0x0110 */ 174 KFDE0_KEY = 7, /* 0x0111 */ 175 KFDE1_KEY = 9, /* 0x1001 */ 176 KFDE2_KEY = 10, /* 0x1010 */ 177 KFDE3_KEY = 11, /* 0x1011 */ 178 END_OF_KEYS = S32_MAX, 179 }; 180 181 #define CC_NUM_HW_KEY_SLOTS 4 182 #define CC_FIRST_HW_KEY_SLOT 0 183 #define CC_LAST_HW_KEY_SLOT (CC_FIRST_HW_KEY_SLOT + CC_NUM_HW_KEY_SLOTS - 1) 184 185 #define CC_NUM_CPP_KEY_SLOTS 8 186 #define CC_FIRST_CPP_KEY_SLOT 16 187 #define CC_LAST_CPP_KEY_SLOT (CC_FIRST_CPP_KEY_SLOT + \ 188 CC_NUM_CPP_KEY_SLOTS - 1) 189 190 enum cc_hw_aes_key_size { 191 AES_128_KEY = 0, 192 AES_192_KEY = 1, 193 AES_256_KEY = 2, 194 END_OF_AES_KEYS = S32_MAX, 195 }; 196 197 enum cc_hash_cipher_pad { 198 DO_NOT_PAD = 0, 199 DO_PAD = 1, 200 HASH_CIPHER_DO_PADDING_RESERVE32 = S32_MAX, 201 }; 202 203 #define CC_CPP_DIN_ADDR 0xFF00FF00UL 204 #define CC_CPP_DIN_SIZE 0xFF00FFUL 205 206 /*****************************/ 207 /* Descriptor packing macros */ 208 /*****************************/ 209 210 /* 211 * Init a HW descriptor struct 212 * @pdesc: pointer HW descriptor struct 213 */ 214 static inline void hw_desc_init(struct cc_hw_desc *pdesc) 215 { 216 memset(pdesc, 0, sizeof(struct cc_hw_desc)); 217 } 218 219 /* 220 * Indicates the end of current HW descriptors flow and release the HW engines. 221 * 222 * @pdesc: pointer HW descriptor struct 223 */ 224 static inline void set_queue_last_ind_bit(struct cc_hw_desc *pdesc) 225 { 226 pdesc->word[3] |= FIELD_PREP(WORD3_QUEUE_LAST_IND, 1); 227 } 228 229 /* 230 * Set the DIN field of a HW descriptors 231 * 232 * @pdesc: pointer HW descriptor struct 233 * @dma_mode: dmaMode The DMA mode: NO_DMA, SRAM, DLLI, MLLI, CONSTANT 234 * @addr: dinAdr DIN address 235 * @size: Data size in bytes 236 * @axi_sec: AXI secure bit 237 */ 238 static inline void set_din_type(struct cc_hw_desc *pdesc, 239 enum cc_dma_mode dma_mode, dma_addr_t addr, 240 u32 size, enum cc_axi_sec axi_sec) 241 { 242 pdesc->word[0] = (u32)addr; 243 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 244 pdesc->word[5] |= FIELD_PREP(WORD5_DIN_ADDR_HIGH, ((u16)(addr >> 32))); 245 #endif 246 pdesc->word[1] |= FIELD_PREP(WORD1_DIN_DMA_MODE, dma_mode) | 247 FIELD_PREP(WORD1_DIN_SIZE, size) | 248 FIELD_PREP(WORD1_NS_BIT, axi_sec); 249 } 250 251 /* 252 * Set the DIN field of a HW descriptors to NO DMA mode. 253 * Used for NOP descriptor, register patches and other special modes. 254 * 255 * @pdesc: pointer HW descriptor struct 256 * @addr: DIN address 257 * @size: Data size in bytes 258 */ 259 static inline void set_din_no_dma(struct cc_hw_desc *pdesc, u32 addr, u32 size) 260 { 261 pdesc->word[0] = addr; 262 pdesc->word[1] |= FIELD_PREP(WORD1_DIN_SIZE, size); 263 } 264 265 /* 266 * Setup the special CPP descriptor 267 * 268 * @pdesc: pointer HW descriptor struct 269 * @alg: cipher used (AES / SM4) 270 * @mode: mode used (CTR or CBC) 271 * @slot: slot number 272 * @ksize: key size 273 */ 274 static inline void set_cpp_crypto_key(struct cc_hw_desc *pdesc, u8 slot) 275 { 276 pdesc->word[0] |= CC_CPP_DIN_ADDR; 277 278 pdesc->word[1] |= FIELD_PREP(WORD1_DIN_SIZE, CC_CPP_DIN_SIZE); 279 pdesc->word[1] |= FIELD_PREP(WORD1_LOCK_QUEUE, 1); 280 281 pdesc->word[4] |= FIELD_PREP(WORD4_SETUP_OPERATION, slot); 282 } 283 284 /* 285 * Set the DIN field of a HW descriptors to SRAM mode. 286 * Note: No need to check SRAM alignment since host requests do not use SRAM and 287 * adaptor will enforce alignment check. 288 * 289 * @pdesc: pointer HW descriptor struct 290 * @addr: DIN address 291 * @size Data size in bytes 292 */ 293 static inline void set_din_sram(struct cc_hw_desc *pdesc, dma_addr_t addr, 294 u32 size) 295 { 296 pdesc->word[0] = (u32)addr; 297 pdesc->word[1] |= FIELD_PREP(WORD1_DIN_SIZE, size) | 298 FIELD_PREP(WORD1_DIN_DMA_MODE, DMA_SRAM); 299 } 300 301 /* 302 * Set the DIN field of a HW descriptors to CONST mode 303 * 304 * @pdesc: pointer HW descriptor struct 305 * @val: DIN const value 306 * @size: Data size in bytes 307 */ 308 static inline void set_din_const(struct cc_hw_desc *pdesc, u32 val, u32 size) 309 { 310 pdesc->word[0] = val; 311 pdesc->word[1] |= FIELD_PREP(WORD1_DIN_CONST_VALUE, 1) | 312 FIELD_PREP(WORD1_DIN_DMA_MODE, DMA_SRAM) | 313 FIELD_PREP(WORD1_DIN_SIZE, size); 314 } 315 316 /* 317 * Set the DIN not last input data indicator 318 * 319 * @pdesc: pointer HW descriptor struct 320 */ 321 static inline void set_din_not_last_indication(struct cc_hw_desc *pdesc) 322 { 323 pdesc->word[1] |= FIELD_PREP(WORD1_NOT_LAST, 1); 324 } 325 326 /* 327 * Set the DOUT field of a HW descriptors 328 * 329 * @pdesc: pointer HW descriptor struct 330 * @dma_mode: The DMA mode: NO_DMA, SRAM, DLLI, MLLI, CONSTANT 331 * @addr: DOUT address 332 * @size: Data size in bytes 333 * @axi_sec: AXI secure bit 334 */ 335 static inline void set_dout_type(struct cc_hw_desc *pdesc, 336 enum cc_dma_mode dma_mode, dma_addr_t addr, 337 u32 size, enum cc_axi_sec axi_sec) 338 { 339 pdesc->word[2] = (u32)addr; 340 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 341 pdesc->word[5] |= FIELD_PREP(WORD5_DOUT_ADDR_HIGH, ((u16)(addr >> 32))); 342 #endif 343 pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_DMA_MODE, dma_mode) | 344 FIELD_PREP(WORD3_DOUT_SIZE, size) | 345 FIELD_PREP(WORD3_NS_BIT, axi_sec); 346 } 347 348 /* 349 * Set the DOUT field of a HW descriptors to DLLI type 350 * The LAST INDICATION is provided by the user 351 * 352 * @pdesc pointer HW descriptor struct 353 * @addr: DOUT address 354 * @size: Data size in bytes 355 * @last_ind: The last indication bit 356 * @axi_sec: AXI secure bit 357 */ 358 static inline void set_dout_dlli(struct cc_hw_desc *pdesc, dma_addr_t addr, 359 u32 size, enum cc_axi_sec axi_sec, 360 u32 last_ind) 361 { 362 set_dout_type(pdesc, DMA_DLLI, addr, size, axi_sec); 363 pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_LAST_IND, last_ind); 364 } 365 366 /* 367 * Set the DOUT field of a HW descriptors to DLLI type 368 * The LAST INDICATION is provided by the user 369 * 370 * @pdesc: pointer HW descriptor struct 371 * @addr: DOUT address 372 * @size: Data size in bytes 373 * @last_ind: The last indication bit 374 * @axi_sec: AXI secure bit 375 */ 376 static inline void set_dout_mlli(struct cc_hw_desc *pdesc, dma_addr_t addr, 377 u32 size, enum cc_axi_sec axi_sec, 378 bool last_ind) 379 { 380 set_dout_type(pdesc, DMA_MLLI, addr, size, axi_sec); 381 pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_LAST_IND, last_ind); 382 } 383 384 /* 385 * Set the DOUT field of a HW descriptors to NO DMA mode. 386 * Used for NOP descriptor, register patches and other special modes. 387 * 388 * @pdesc: pointer HW descriptor struct 389 * @addr: DOUT address 390 * @size: Data size in bytes 391 * @write_enable: Enables a write operation to a register 392 */ 393 static inline void set_dout_no_dma(struct cc_hw_desc *pdesc, u32 addr, 394 u32 size, bool write_enable) 395 { 396 pdesc->word[2] = addr; 397 pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_SIZE, size) | 398 FIELD_PREP(WORD3_DOUT_LAST_IND, write_enable); 399 } 400 401 /* 402 * Set the word for the XOR operation. 403 * 404 * @pdesc: pointer HW descriptor struct 405 * @val: xor data value 406 */ 407 static inline void set_xor_val(struct cc_hw_desc *pdesc, u32 val) 408 { 409 pdesc->word[2] = val; 410 } 411 412 /* 413 * Sets the XOR indicator bit in the descriptor 414 * 415 * @pdesc: pointer HW descriptor struct 416 */ 417 static inline void set_xor_active(struct cc_hw_desc *pdesc) 418 { 419 pdesc->word[3] |= FIELD_PREP(WORD3_HASH_XOR_BIT, 1); 420 } 421 422 /* 423 * Select the AES engine instead of HASH engine when setting up combined mode 424 * with AES XCBC MAC 425 * 426 * @pdesc: pointer HW descriptor struct 427 */ 428 static inline void set_aes_not_hash_mode(struct cc_hw_desc *pdesc) 429 { 430 pdesc->word[4] |= FIELD_PREP(WORD4_AES_SEL_N_HASH, 1); 431 } 432 433 /* 434 * Set aes xor crypto key, this in some secenrios select SM3 engine 435 * 436 * @pdesc: pointer HW descriptor struct 437 */ 438 static inline void set_aes_xor_crypto_key(struct cc_hw_desc *pdesc) 439 { 440 pdesc->word[4] |= FIELD_PREP(WORD4_AES_XOR_CRYPTO_KEY, 1); 441 } 442 443 /* 444 * Set the DOUT field of a HW descriptors to SRAM mode 445 * Note: No need to check SRAM alignment since host requests do not use SRAM and 446 * adaptor will enforce alignment check. 447 * 448 * @pdesc: pointer HW descriptor struct 449 * @addr: DOUT address 450 * @size: Data size in bytes 451 */ 452 static inline void set_dout_sram(struct cc_hw_desc *pdesc, u32 addr, u32 size) 453 { 454 pdesc->word[2] = addr; 455 pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_DMA_MODE, DMA_SRAM) | 456 FIELD_PREP(WORD3_DOUT_SIZE, size); 457 } 458 459 /* 460 * Sets the data unit size for XEX mode in data_out_addr[15:0] 461 * 462 * @pdesc: pDesc pointer HW descriptor struct 463 * @size: data unit size for XEX mode 464 */ 465 static inline void set_xex_data_unit_size(struct cc_hw_desc *pdesc, u32 size) 466 { 467 pdesc->word[2] = size; 468 } 469 470 /* 471 * Set the number of rounds for Multi2 in data_out_addr[15:0] 472 * 473 * @pdesc: pointer HW descriptor struct 474 * @num: number of rounds for Multi2 475 */ 476 static inline void set_multi2_num_rounds(struct cc_hw_desc *pdesc, u32 num) 477 { 478 pdesc->word[2] = num; 479 } 480 481 /* 482 * Set the flow mode. 483 * 484 * @pdesc: pointer HW descriptor struct 485 * @mode: Any one of the modes defined in [CC7x-DESC] 486 */ 487 static inline void set_flow_mode(struct cc_hw_desc *pdesc, 488 enum cc_flow_mode mode) 489 { 490 pdesc->word[4] |= FIELD_PREP(WORD4_DATA_FLOW_MODE, mode); 491 } 492 493 /* 494 * Set the cipher mode. 495 * 496 * @pdesc: pointer HW descriptor struct 497 * @mode: Any one of the modes defined in [CC7x-DESC] 498 */ 499 static inline void set_cipher_mode(struct cc_hw_desc *pdesc, int mode) 500 { 501 pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_MODE, mode); 502 } 503 504 /* 505 * Set the cipher mode for hash algorithms. 506 * 507 * @pdesc: pointer HW descriptor struct 508 * @cipher_mode: Any one of the modes defined in [CC7x-DESC] 509 * @hash_mode: specifies which hash is being handled 510 */ 511 static inline void set_hash_cipher_mode(struct cc_hw_desc *pdesc, 512 enum drv_cipher_mode cipher_mode, 513 enum drv_hash_mode hash_mode) 514 { 515 set_cipher_mode(pdesc, cipher_mode); 516 if (hash_mode == DRV_HASH_SM3) 517 set_aes_xor_crypto_key(pdesc); 518 } 519 520 /* 521 * Set the cipher configuration fields. 522 * 523 * @pdesc: pointer HW descriptor struct 524 * @mode: Any one of the modes defined in [CC7x-DESC] 525 */ 526 static inline void set_cipher_config0(struct cc_hw_desc *pdesc, int mode) 527 { 528 pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_CONF0, mode); 529 } 530 531 /* 532 * Set the cipher configuration fields. 533 * 534 * @pdesc: pointer HW descriptor struct 535 * @config: Any one of the modes defined in [CC7x-DESC] 536 */ 537 static inline void set_cipher_config1(struct cc_hw_desc *pdesc, 538 enum cc_hash_conf_pad config) 539 { 540 pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_CONF1, config); 541 } 542 543 /* 544 * Set HW key configuration fields. 545 * 546 * @pdesc: pointer HW descriptor struct 547 * @hw_key: The HW key slot asdefined in enum cc_hw_crypto_key 548 */ 549 static inline void set_hw_crypto_key(struct cc_hw_desc *pdesc, 550 enum cc_hw_crypto_key hw_key) 551 { 552 pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_DO, 553 (hw_key & HW_KEY_MASK_CIPHER_DO)) | 554 FIELD_PREP(WORD4_CIPHER_CONF2, 555 (hw_key >> HW_KEY_SHIFT_CIPHER_CFG2)); 556 } 557 558 /* 559 * Set byte order of all setup-finalize descriptors. 560 * 561 * @pdesc: pointer HW descriptor struct 562 * @config: Any one of the modes defined in [CC7x-DESC] 563 */ 564 static inline void set_bytes_swap(struct cc_hw_desc *pdesc, bool config) 565 { 566 pdesc->word[4] |= FIELD_PREP(WORD4_BYTES_SWAP, config); 567 } 568 569 /* 570 * Set CMAC_SIZE0 mode. 571 * 572 * @pdesc: pointer HW descriptor struct 573 */ 574 static inline void set_cmac_size0_mode(struct cc_hw_desc *pdesc) 575 { 576 pdesc->word[4] |= FIELD_PREP(WORD4_CMAC_SIZE0, 1); 577 } 578 579 /* 580 * Set key size descriptor field. 581 * 582 * @pdesc: pointer HW descriptor struct 583 * @size: key size in bytes (NOT size code) 584 */ 585 static inline void set_key_size(struct cc_hw_desc *pdesc, u32 size) 586 { 587 pdesc->word[4] |= FIELD_PREP(WORD4_KEY_SIZE, size); 588 } 589 590 /* 591 * Set AES key size. 592 * 593 * @pdesc: pointer HW descriptor struct 594 * @size: key size in bytes (NOT size code) 595 */ 596 static inline void set_key_size_aes(struct cc_hw_desc *pdesc, u32 size) 597 { 598 set_key_size(pdesc, ((size >> 3) - 2)); 599 } 600 601 /* 602 * Set DES key size. 603 * 604 * @pdesc: pointer HW descriptor struct 605 * @size: key size in bytes (NOT size code) 606 */ 607 static inline void set_key_size_des(struct cc_hw_desc *pdesc, u32 size) 608 { 609 set_key_size(pdesc, ((size >> 3) - 1)); 610 } 611 612 /* 613 * Set the descriptor setup mode 614 * 615 * @pdesc: pointer HW descriptor struct 616 * @mode: Any one of the setup modes defined in [CC7x-DESC] 617 */ 618 static inline void set_setup_mode(struct cc_hw_desc *pdesc, 619 enum cc_setup_op mode) 620 { 621 pdesc->word[4] |= FIELD_PREP(WORD4_SETUP_OPERATION, mode); 622 } 623 624 /* 625 * Set the descriptor cipher DO 626 * 627 * @pdesc: pointer HW descriptor struct 628 * @config: Any one of the cipher do defined in [CC7x-DESC] 629 */ 630 static inline void set_cipher_do(struct cc_hw_desc *pdesc, 631 enum cc_hash_cipher_pad config) 632 { 633 pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_DO, 634 (config & HW_KEY_MASK_CIPHER_DO)); 635 } 636 637 #endif /*__CC_HW_QUEUE_DEFS_H__*/ 638