1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (C) 2012-2018 ARM Limited or its affiliates. */ 3 4 #ifndef __CC_HW_QUEUE_DEFS_H__ 5 #define __CC_HW_QUEUE_DEFS_H__ 6 7 #include <linux/types.h> 8 9 #include "cc_kernel_regs.h" 10 #include <linux/bitfield.h> 11 12 /****************************************************************************** 13 * DEFINITIONS 14 ******************************************************************************/ 15 16 #define HW_DESC_SIZE_WORDS 6 17 /* Define max. available slots in HW queue */ 18 #define HW_QUEUE_SLOTS_MAX 15 19 20 #define CC_REG_LOW(word, name) \ 21 (CC_DSCRPTR_QUEUE_WORD ## word ## _ ## name ## _BIT_SHIFT) 22 23 #define CC_REG_HIGH(word, name) \ 24 (CC_REG_LOW(word, name) + \ 25 CC_DSCRPTR_QUEUE_WORD ## word ## _ ## name ## _BIT_SIZE - 1) 26 27 #define CC_GENMASK(word, name) \ 28 GENMASK(CC_REG_HIGH(word, name), CC_REG_LOW(word, name)) 29 30 #define WORD0_VALUE CC_GENMASK(0, VALUE) 31 #define WORD1_DIN_CONST_VALUE CC_GENMASK(1, DIN_CONST_VALUE) 32 #define WORD1_DIN_DMA_MODE CC_GENMASK(1, DIN_DMA_MODE) 33 #define WORD1_DIN_SIZE CC_GENMASK(1, DIN_SIZE) 34 #define WORD1_NOT_LAST CC_GENMASK(1, NOT_LAST) 35 #define WORD1_NS_BIT CC_GENMASK(1, NS_BIT) 36 #define WORD2_VALUE CC_GENMASK(2, VALUE) 37 #define WORD3_DOUT_DMA_MODE CC_GENMASK(3, DOUT_DMA_MODE) 38 #define WORD3_DOUT_LAST_IND CC_GENMASK(3, DOUT_LAST_IND) 39 #define WORD3_DOUT_SIZE CC_GENMASK(3, DOUT_SIZE) 40 #define WORD3_HASH_XOR_BIT CC_GENMASK(3, HASH_XOR_BIT) 41 #define WORD3_NS_BIT CC_GENMASK(3, NS_BIT) 42 #define WORD3_QUEUE_LAST_IND CC_GENMASK(3, QUEUE_LAST_IND) 43 #define WORD4_ACK_NEEDED CC_GENMASK(4, ACK_NEEDED) 44 #define WORD4_AES_SEL_N_HASH CC_GENMASK(4, AES_SEL_N_HASH) 45 #define WORD4_AES_XOR_CRYPTO_KEY CC_GENMASK(4, AES_XOR_CRYPTO_KEY) 46 #define WORD4_BYTES_SWAP CC_GENMASK(4, BYTES_SWAP) 47 #define WORD4_CIPHER_CONF0 CC_GENMASK(4, CIPHER_CONF0) 48 #define WORD4_CIPHER_CONF1 CC_GENMASK(4, CIPHER_CONF1) 49 #define WORD4_CIPHER_CONF2 CC_GENMASK(4, CIPHER_CONF2) 50 #define WORD4_CIPHER_DO CC_GENMASK(4, CIPHER_DO) 51 #define WORD4_CIPHER_MODE CC_GENMASK(4, CIPHER_MODE) 52 #define WORD4_CMAC_SIZE0 CC_GENMASK(4, CMAC_SIZE0) 53 #define WORD4_DATA_FLOW_MODE CC_GENMASK(4, DATA_FLOW_MODE) 54 #define WORD4_KEY_SIZE CC_GENMASK(4, KEY_SIZE) 55 #define WORD4_SETUP_OPERATION CC_GENMASK(4, SETUP_OPERATION) 56 #define WORD5_DIN_ADDR_HIGH CC_GENMASK(5, DIN_ADDR_HIGH) 57 #define WORD5_DOUT_ADDR_HIGH CC_GENMASK(5, DOUT_ADDR_HIGH) 58 59 /****************************************************************************** 60 * TYPE DEFINITIONS 61 ******************************************************************************/ 62 63 struct cc_hw_desc { 64 union { 65 u32 word[HW_DESC_SIZE_WORDS]; 66 u16 hword[HW_DESC_SIZE_WORDS * 2]; 67 }; 68 }; 69 70 enum cc_axi_sec { 71 AXI_SECURE = 0, 72 AXI_NOT_SECURE = 1 73 }; 74 75 enum cc_desc_direction { 76 DESC_DIRECTION_ILLEGAL = -1, 77 DESC_DIRECTION_ENCRYPT_ENCRYPT = 0, 78 DESC_DIRECTION_DECRYPT_DECRYPT = 1, 79 DESC_DIRECTION_DECRYPT_ENCRYPT = 3, 80 DESC_DIRECTION_END = S32_MAX, 81 }; 82 83 enum cc_dma_mode { 84 DMA_MODE_NULL = -1, 85 NO_DMA = 0, 86 DMA_SRAM = 1, 87 DMA_DLLI = 2, 88 DMA_MLLI = 3, 89 DMA_MODE_END = S32_MAX, 90 }; 91 92 enum cc_flow_mode { 93 FLOW_MODE_NULL = -1, 94 /* data flows */ 95 BYPASS = 0, 96 DIN_AES_DOUT = 1, 97 AES_to_HASH = 2, 98 AES_and_HASH = 3, 99 DIN_DES_DOUT = 4, 100 DES_to_HASH = 5, 101 DES_and_HASH = 6, 102 DIN_HASH = 7, 103 DIN_HASH_and_BYPASS = 8, 104 AESMAC_and_BYPASS = 9, 105 AES_to_HASH_and_DOUT = 10, 106 DIN_RC4_DOUT = 11, 107 DES_to_HASH_and_DOUT = 12, 108 AES_to_AES_to_HASH_and_DOUT = 13, 109 AES_to_AES_to_HASH = 14, 110 AES_to_HASH_and_AES = 15, 111 DIN_SM4_DOUT = 16, 112 DIN_AES_AESMAC = 17, 113 HASH_to_DOUT = 18, 114 /* setup flows */ 115 S_DIN_to_AES = 32, 116 S_DIN_to_AES2 = 33, 117 S_DIN_to_DES = 34, 118 S_DIN_to_RC4 = 35, 119 S_DIN_to_SM4 = 36, 120 S_DIN_to_HASH = 37, 121 S_AES_to_DOUT = 38, 122 S_AES2_to_DOUT = 39, 123 S_SM4_to_DOUT = 40, 124 S_RC4_to_DOUT = 41, 125 S_DES_to_DOUT = 42, 126 S_HASH_to_DOUT = 43, 127 SET_FLOW_ID = 44, 128 FLOW_MODE_END = S32_MAX, 129 }; 130 131 enum cc_setup_op { 132 SETUP_LOAD_NOP = 0, 133 SETUP_LOAD_STATE0 = 1, 134 SETUP_LOAD_STATE1 = 2, 135 SETUP_LOAD_STATE2 = 3, 136 SETUP_LOAD_KEY0 = 4, 137 SETUP_LOAD_XEX_KEY = 5, 138 SETUP_WRITE_STATE0 = 8, 139 SETUP_WRITE_STATE1 = 9, 140 SETUP_WRITE_STATE2 = 10, 141 SETUP_WRITE_STATE3 = 11, 142 SETUP_OP_END = S32_MAX, 143 }; 144 145 enum cc_hash_conf_pad { 146 HASH_PADDING_DISABLED = 0, 147 HASH_PADDING_ENABLED = 1, 148 HASH_DIGEST_RESULT_LITTLE_ENDIAN = 2, 149 HASH_CONFIG1_PADDING_RESERVE32 = S32_MAX, 150 }; 151 152 enum cc_aes_mac_selector { 153 AES_SK = 1, 154 AES_CMAC_INIT = 2, 155 AES_CMAC_SIZE0 = 3, 156 AES_MAC_END = S32_MAX, 157 }; 158 159 #define HW_KEY_MASK_CIPHER_DO 0x3 160 #define HW_KEY_SHIFT_CIPHER_CFG2 2 161 162 /* HwCryptoKey[1:0] is mapped to cipher_do[1:0] */ 163 /* HwCryptoKey[2:3] is mapped to cipher_config2[1:0] */ 164 enum cc_hw_crypto_key { 165 USER_KEY = 0, /* 0x0000 */ 166 ROOT_KEY = 1, /* 0x0001 */ 167 PROVISIONING_KEY = 2, /* 0x0010 */ /* ==KCP */ 168 SESSION_KEY = 3, /* 0x0011 */ 169 RESERVED_KEY = 4, /* NA */ 170 PLATFORM_KEY = 5, /* 0x0101 */ 171 CUSTOMER_KEY = 6, /* 0x0110 */ 172 KFDE0_KEY = 7, /* 0x0111 */ 173 KFDE1_KEY = 9, /* 0x1001 */ 174 KFDE2_KEY = 10, /* 0x1010 */ 175 KFDE3_KEY = 11, /* 0x1011 */ 176 END_OF_KEYS = S32_MAX, 177 }; 178 179 enum cc_hw_aes_key_size { 180 AES_128_KEY = 0, 181 AES_192_KEY = 1, 182 AES_256_KEY = 2, 183 END_OF_AES_KEYS = S32_MAX, 184 }; 185 186 enum cc_hash_cipher_pad { 187 DO_NOT_PAD = 0, 188 DO_PAD = 1, 189 HASH_CIPHER_DO_PADDING_RESERVE32 = S32_MAX, 190 }; 191 192 /*****************************/ 193 /* Descriptor packing macros */ 194 /*****************************/ 195 196 /* 197 * Init a HW descriptor struct 198 * @pdesc: pointer HW descriptor struct 199 */ 200 static inline void hw_desc_init(struct cc_hw_desc *pdesc) 201 { 202 memset(pdesc, 0, sizeof(struct cc_hw_desc)); 203 } 204 205 /* 206 * Indicates the end of current HW descriptors flow and release the HW engines. 207 * 208 * @pdesc: pointer HW descriptor struct 209 */ 210 static inline void set_queue_last_ind_bit(struct cc_hw_desc *pdesc) 211 { 212 pdesc->word[3] |= FIELD_PREP(WORD3_QUEUE_LAST_IND, 1); 213 } 214 215 /* 216 * Set the DIN field of a HW descriptors 217 * 218 * @pdesc: pointer HW descriptor struct 219 * @dma_mode: dmaMode The DMA mode: NO_DMA, SRAM, DLLI, MLLI, CONSTANT 220 * @addr: dinAdr DIN address 221 * @size: Data size in bytes 222 * @axi_sec: AXI secure bit 223 */ 224 static inline void set_din_type(struct cc_hw_desc *pdesc, 225 enum cc_dma_mode dma_mode, dma_addr_t addr, 226 u32 size, enum cc_axi_sec axi_sec) 227 { 228 pdesc->word[0] = (u32)addr; 229 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 230 pdesc->word[5] |= FIELD_PREP(WORD5_DIN_ADDR_HIGH, ((u16)(addr >> 32))); 231 #endif 232 pdesc->word[1] |= FIELD_PREP(WORD1_DIN_DMA_MODE, dma_mode) | 233 FIELD_PREP(WORD1_DIN_SIZE, size) | 234 FIELD_PREP(WORD1_NS_BIT, axi_sec); 235 } 236 237 /* 238 * Set the DIN field of a HW descriptors to NO DMA mode. 239 * Used for NOP descriptor, register patches and other special modes. 240 * 241 * @pdesc: pointer HW descriptor struct 242 * @addr: DIN address 243 * @size: Data size in bytes 244 */ 245 static inline void set_din_no_dma(struct cc_hw_desc *pdesc, u32 addr, u32 size) 246 { 247 pdesc->word[0] = addr; 248 pdesc->word[1] |= FIELD_PREP(WORD1_DIN_SIZE, size); 249 } 250 251 /* 252 * Set the DIN field of a HW descriptors to SRAM mode. 253 * Note: No need to check SRAM alignment since host requests do not use SRAM and 254 * adaptor will enforce alignment check. 255 * 256 * @pdesc: pointer HW descriptor struct 257 * @addr: DIN address 258 * @size Data size in bytes 259 */ 260 static inline void set_din_sram(struct cc_hw_desc *pdesc, dma_addr_t addr, 261 u32 size) 262 { 263 pdesc->word[0] = (u32)addr; 264 pdesc->word[1] |= FIELD_PREP(WORD1_DIN_SIZE, size) | 265 FIELD_PREP(WORD1_DIN_DMA_MODE, DMA_SRAM); 266 } 267 268 /* 269 * Set the DIN field of a HW descriptors to CONST mode 270 * 271 * @pdesc: pointer HW descriptor struct 272 * @val: DIN const value 273 * @size: Data size in bytes 274 */ 275 static inline void set_din_const(struct cc_hw_desc *pdesc, u32 val, u32 size) 276 { 277 pdesc->word[0] = val; 278 pdesc->word[1] |= FIELD_PREP(WORD1_DIN_CONST_VALUE, 1) | 279 FIELD_PREP(WORD1_DIN_DMA_MODE, DMA_SRAM) | 280 FIELD_PREP(WORD1_DIN_SIZE, size); 281 } 282 283 /* 284 * Set the DIN not last input data indicator 285 * 286 * @pdesc: pointer HW descriptor struct 287 */ 288 static inline void set_din_not_last_indication(struct cc_hw_desc *pdesc) 289 { 290 pdesc->word[1] |= FIELD_PREP(WORD1_NOT_LAST, 1); 291 } 292 293 /* 294 * Set the DOUT field of a HW descriptors 295 * 296 * @pdesc: pointer HW descriptor struct 297 * @dma_mode: The DMA mode: NO_DMA, SRAM, DLLI, MLLI, CONSTANT 298 * @addr: DOUT address 299 * @size: Data size in bytes 300 * @axi_sec: AXI secure bit 301 */ 302 static inline void set_dout_type(struct cc_hw_desc *pdesc, 303 enum cc_dma_mode dma_mode, dma_addr_t addr, 304 u32 size, enum cc_axi_sec axi_sec) 305 { 306 pdesc->word[2] = (u32)addr; 307 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 308 pdesc->word[5] |= FIELD_PREP(WORD5_DOUT_ADDR_HIGH, ((u16)(addr >> 32))); 309 #endif 310 pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_DMA_MODE, dma_mode) | 311 FIELD_PREP(WORD3_DOUT_SIZE, size) | 312 FIELD_PREP(WORD3_NS_BIT, axi_sec); 313 } 314 315 /* 316 * Set the DOUT field of a HW descriptors to DLLI type 317 * The LAST INDICATION is provided by the user 318 * 319 * @pdesc pointer HW descriptor struct 320 * @addr: DOUT address 321 * @size: Data size in bytes 322 * @last_ind: The last indication bit 323 * @axi_sec: AXI secure bit 324 */ 325 static inline void set_dout_dlli(struct cc_hw_desc *pdesc, dma_addr_t addr, 326 u32 size, enum cc_axi_sec axi_sec, 327 u32 last_ind) 328 { 329 set_dout_type(pdesc, DMA_DLLI, addr, size, axi_sec); 330 pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_LAST_IND, last_ind); 331 } 332 333 /* 334 * Set the DOUT field of a HW descriptors to DLLI type 335 * The LAST INDICATION is provided by the user 336 * 337 * @pdesc: pointer HW descriptor struct 338 * @addr: DOUT address 339 * @size: Data size in bytes 340 * @last_ind: The last indication bit 341 * @axi_sec: AXI secure bit 342 */ 343 static inline void set_dout_mlli(struct cc_hw_desc *pdesc, dma_addr_t addr, 344 u32 size, enum cc_axi_sec axi_sec, 345 bool last_ind) 346 { 347 set_dout_type(pdesc, DMA_MLLI, addr, size, axi_sec); 348 pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_LAST_IND, last_ind); 349 } 350 351 /* 352 * Set the DOUT field of a HW descriptors to NO DMA mode. 353 * Used for NOP descriptor, register patches and other special modes. 354 * 355 * @pdesc: pointer HW descriptor struct 356 * @addr: DOUT address 357 * @size: Data size in bytes 358 * @write_enable: Enables a write operation to a register 359 */ 360 static inline void set_dout_no_dma(struct cc_hw_desc *pdesc, u32 addr, 361 u32 size, bool write_enable) 362 { 363 pdesc->word[2] = addr; 364 pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_SIZE, size) | 365 FIELD_PREP(WORD3_DOUT_LAST_IND, write_enable); 366 } 367 368 /* 369 * Set the word for the XOR operation. 370 * 371 * @pdesc: pointer HW descriptor struct 372 * @val: xor data value 373 */ 374 static inline void set_xor_val(struct cc_hw_desc *pdesc, u32 val) 375 { 376 pdesc->word[2] = val; 377 } 378 379 /* 380 * Sets the XOR indicator bit in the descriptor 381 * 382 * @pdesc: pointer HW descriptor struct 383 */ 384 static inline void set_xor_active(struct cc_hw_desc *pdesc) 385 { 386 pdesc->word[3] |= FIELD_PREP(WORD3_HASH_XOR_BIT, 1); 387 } 388 389 /* 390 * Select the AES engine instead of HASH engine when setting up combined mode 391 * with AES XCBC MAC 392 * 393 * @pdesc: pointer HW descriptor struct 394 */ 395 static inline void set_aes_not_hash_mode(struct cc_hw_desc *pdesc) 396 { 397 pdesc->word[4] |= FIELD_PREP(WORD4_AES_SEL_N_HASH, 1); 398 } 399 400 /* 401 * Set aes xor crypto key, this in some secenrios select SM3 engine 402 * 403 * @pdesc: pointer HW descriptor struct 404 */ 405 static inline void set_aes_xor_crypto_key(struct cc_hw_desc *pdesc) 406 { 407 pdesc->word[4] |= FIELD_PREP(WORD4_AES_XOR_CRYPTO_KEY, 1); 408 } 409 410 /* 411 * Set the DOUT field of a HW descriptors to SRAM mode 412 * Note: No need to check SRAM alignment since host requests do not use SRAM and 413 * adaptor will enforce alignment check. 414 * 415 * @pdesc: pointer HW descriptor struct 416 * @addr: DOUT address 417 * @size: Data size in bytes 418 */ 419 static inline void set_dout_sram(struct cc_hw_desc *pdesc, u32 addr, u32 size) 420 { 421 pdesc->word[2] = addr; 422 pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_DMA_MODE, DMA_SRAM) | 423 FIELD_PREP(WORD3_DOUT_SIZE, size); 424 } 425 426 /* 427 * Sets the data unit size for XEX mode in data_out_addr[15:0] 428 * 429 * @pdesc: pDesc pointer HW descriptor struct 430 * @size: data unit size for XEX mode 431 */ 432 static inline void set_xex_data_unit_size(struct cc_hw_desc *pdesc, u32 size) 433 { 434 pdesc->word[2] = size; 435 } 436 437 /* 438 * Set the number of rounds for Multi2 in data_out_addr[15:0] 439 * 440 * @pdesc: pointer HW descriptor struct 441 * @num: number of rounds for Multi2 442 */ 443 static inline void set_multi2_num_rounds(struct cc_hw_desc *pdesc, u32 num) 444 { 445 pdesc->word[2] = num; 446 } 447 448 /* 449 * Set the flow mode. 450 * 451 * @pdesc: pointer HW descriptor struct 452 * @mode: Any one of the modes defined in [CC7x-DESC] 453 */ 454 static inline void set_flow_mode(struct cc_hw_desc *pdesc, 455 enum cc_flow_mode mode) 456 { 457 pdesc->word[4] |= FIELD_PREP(WORD4_DATA_FLOW_MODE, mode); 458 } 459 460 /* 461 * Set the cipher mode. 462 * 463 * @pdesc: pointer HW descriptor struct 464 * @mode: Any one of the modes defined in [CC7x-DESC] 465 */ 466 static inline void set_cipher_mode(struct cc_hw_desc *pdesc, int mode) 467 { 468 pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_MODE, mode); 469 } 470 471 /* 472 * Set the cipher mode for hash algorithms. 473 * 474 * @pdesc: pointer HW descriptor struct 475 * @cipher_mode: Any one of the modes defined in [CC7x-DESC] 476 * @hash_mode: specifies which hash is being handled 477 */ 478 static inline void set_hash_cipher_mode(struct cc_hw_desc *pdesc, 479 enum drv_cipher_mode cipher_mode, 480 enum drv_hash_mode hash_mode) 481 { 482 set_cipher_mode(pdesc, cipher_mode); 483 if (hash_mode == DRV_HASH_SM3) 484 set_aes_xor_crypto_key(pdesc); 485 } 486 487 /* 488 * Set the cipher configuration fields. 489 * 490 * @pdesc: pointer HW descriptor struct 491 * @mode: Any one of the modes defined in [CC7x-DESC] 492 */ 493 static inline void set_cipher_config0(struct cc_hw_desc *pdesc, int mode) 494 { 495 pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_CONF0, mode); 496 } 497 498 /* 499 * Set the cipher configuration fields. 500 * 501 * @pdesc: pointer HW descriptor struct 502 * @config: Any one of the modes defined in [CC7x-DESC] 503 */ 504 static inline void set_cipher_config1(struct cc_hw_desc *pdesc, 505 enum cc_hash_conf_pad config) 506 { 507 pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_CONF1, config); 508 } 509 510 /* 511 * Set HW key configuration fields. 512 * 513 * @pdesc: pointer HW descriptor struct 514 * @hw_key: The HW key slot asdefined in enum cc_hw_crypto_key 515 */ 516 static inline void set_hw_crypto_key(struct cc_hw_desc *pdesc, 517 enum cc_hw_crypto_key hw_key) 518 { 519 pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_DO, 520 (hw_key & HW_KEY_MASK_CIPHER_DO)) | 521 FIELD_PREP(WORD4_CIPHER_CONF2, 522 (hw_key >> HW_KEY_SHIFT_CIPHER_CFG2)); 523 } 524 525 /* 526 * Set byte order of all setup-finalize descriptors. 527 * 528 * @pdesc: pointer HW descriptor struct 529 * @config: Any one of the modes defined in [CC7x-DESC] 530 */ 531 static inline void set_bytes_swap(struct cc_hw_desc *pdesc, bool config) 532 { 533 pdesc->word[4] |= FIELD_PREP(WORD4_BYTES_SWAP, config); 534 } 535 536 /* 537 * Set CMAC_SIZE0 mode. 538 * 539 * @pdesc: pointer HW descriptor struct 540 */ 541 static inline void set_cmac_size0_mode(struct cc_hw_desc *pdesc) 542 { 543 pdesc->word[4] |= FIELD_PREP(WORD4_CMAC_SIZE0, 1); 544 } 545 546 /* 547 * Set key size descriptor field. 548 * 549 * @pdesc: pointer HW descriptor struct 550 * @size: key size in bytes (NOT size code) 551 */ 552 static inline void set_key_size(struct cc_hw_desc *pdesc, u32 size) 553 { 554 pdesc->word[4] |= FIELD_PREP(WORD4_KEY_SIZE, size); 555 } 556 557 /* 558 * Set AES key size. 559 * 560 * @pdesc: pointer HW descriptor struct 561 * @size: key size in bytes (NOT size code) 562 */ 563 static inline void set_key_size_aes(struct cc_hw_desc *pdesc, u32 size) 564 { 565 set_key_size(pdesc, ((size >> 3) - 2)); 566 } 567 568 /* 569 * Set DES key size. 570 * 571 * @pdesc: pointer HW descriptor struct 572 * @size: key size in bytes (NOT size code) 573 */ 574 static inline void set_key_size_des(struct cc_hw_desc *pdesc, u32 size) 575 { 576 set_key_size(pdesc, ((size >> 3) - 1)); 577 } 578 579 /* 580 * Set the descriptor setup mode 581 * 582 * @pdesc: pointer HW descriptor struct 583 * @mode: Any one of the setup modes defined in [CC7x-DESC] 584 */ 585 static inline void set_setup_mode(struct cc_hw_desc *pdesc, 586 enum cc_setup_op mode) 587 { 588 pdesc->word[4] |= FIELD_PREP(WORD4_SETUP_OPERATION, mode); 589 } 590 591 /* 592 * Set the descriptor cipher DO 593 * 594 * @pdesc: pointer HW descriptor struct 595 * @config: Any one of the cipher do defined in [CC7x-DESC] 596 */ 597 static inline void set_cipher_do(struct cc_hw_desc *pdesc, 598 enum cc_hash_cipher_pad config) 599 { 600 pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_DO, 601 (config & HW_KEY_MASK_CIPHER_DO)); 602 } 603 604 #endif /*__CC_HW_QUEUE_DEFS_H__*/ 605