14c3f9727SGilad Ben-Yossef /* SPDX-License-Identifier: GPL-2.0 */
203963caeSGilad Ben-Yossef /* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */
34c3f9727SGilad Ben-Yossef
44c3f9727SGilad Ben-Yossef #ifndef __CC_HW_QUEUE_DEFS_H__
54c3f9727SGilad Ben-Yossef #define __CC_HW_QUEUE_DEFS_H__
64c3f9727SGilad Ben-Yossef
74c3f9727SGilad Ben-Yossef #include <linux/types.h>
84c3f9727SGilad Ben-Yossef
94c3f9727SGilad Ben-Yossef #include "cc_kernel_regs.h"
104c3f9727SGilad Ben-Yossef #include <linux/bitfield.h>
114c3f9727SGilad Ben-Yossef
124c3f9727SGilad Ben-Yossef /******************************************************************************
134c3f9727SGilad Ben-Yossef * DEFINITIONS
144c3f9727SGilad Ben-Yossef ******************************************************************************/
154c3f9727SGilad Ben-Yossef
164c3f9727SGilad Ben-Yossef #define HW_DESC_SIZE_WORDS 6
174c3f9727SGilad Ben-Yossef /* Define max. available slots in HW queue */
184c3f9727SGilad Ben-Yossef #define HW_QUEUE_SLOTS_MAX 15
194c3f9727SGilad Ben-Yossef
20d8215ff1SHadar Gat #define CC_REG_LOW(name) (name ## _BIT_SHIFT)
21d8215ff1SHadar Gat #define CC_REG_HIGH(name) (CC_REG_LOW(name) + name ## _BIT_SIZE - 1)
22d8215ff1SHadar Gat #define CC_GENMASK(name) GENMASK(CC_REG_HIGH(name), CC_REG_LOW(name))
234c3f9727SGilad Ben-Yossef
24d8215ff1SHadar Gat #define CC_HWQ_GENMASK(word, field) \
25d8215ff1SHadar Gat CC_GENMASK(CC_DSCRPTR_QUEUE_WORD ## word ## _ ## field)
264c3f9727SGilad Ben-Yossef
27d8215ff1SHadar Gat #define WORD0_VALUE CC_HWQ_GENMASK(0, VALUE)
28d8215ff1SHadar Gat #define WORD0_CPP_CIPHER_MODE CC_HWQ_GENMASK(0, CPP_CIPHER_MODE)
29d8215ff1SHadar Gat #define WORD1_DIN_CONST_VALUE CC_HWQ_GENMASK(1, DIN_CONST_VALUE)
30d8215ff1SHadar Gat #define WORD1_DIN_DMA_MODE CC_HWQ_GENMASK(1, DIN_DMA_MODE)
31d8215ff1SHadar Gat #define WORD1_DIN_SIZE CC_HWQ_GENMASK(1, DIN_SIZE)
32d8215ff1SHadar Gat #define WORD1_NOT_LAST CC_HWQ_GENMASK(1, NOT_LAST)
33d8215ff1SHadar Gat #define WORD1_NS_BIT CC_HWQ_GENMASK(1, NS_BIT)
34d8215ff1SHadar Gat #define WORD1_LOCK_QUEUE CC_HWQ_GENMASK(1, LOCK_QUEUE)
35d8215ff1SHadar Gat #define WORD2_VALUE CC_HWQ_GENMASK(2, VALUE)
36d8215ff1SHadar Gat #define WORD3_DOUT_DMA_MODE CC_HWQ_GENMASK(3, DOUT_DMA_MODE)
37d8215ff1SHadar Gat #define WORD3_DOUT_LAST_IND CC_HWQ_GENMASK(3, DOUT_LAST_IND)
38d8215ff1SHadar Gat #define WORD3_DOUT_SIZE CC_HWQ_GENMASK(3, DOUT_SIZE)
39d8215ff1SHadar Gat #define WORD3_HASH_XOR_BIT CC_HWQ_GENMASK(3, HASH_XOR_BIT)
40d8215ff1SHadar Gat #define WORD3_NS_BIT CC_HWQ_GENMASK(3, NS_BIT)
41d8215ff1SHadar Gat #define WORD3_QUEUE_LAST_IND CC_HWQ_GENMASK(3, QUEUE_LAST_IND)
42d8215ff1SHadar Gat #define WORD4_ACK_NEEDED CC_HWQ_GENMASK(4, ACK_NEEDED)
43d8215ff1SHadar Gat #define WORD4_AES_SEL_N_HASH CC_HWQ_GENMASK(4, AES_SEL_N_HASH)
44d8215ff1SHadar Gat #define WORD4_AES_XOR_CRYPTO_KEY CC_HWQ_GENMASK(4, AES_XOR_CRYPTO_KEY)
45d8215ff1SHadar Gat #define WORD4_BYTES_SWAP CC_HWQ_GENMASK(4, BYTES_SWAP)
46d8215ff1SHadar Gat #define WORD4_CIPHER_CONF0 CC_HWQ_GENMASK(4, CIPHER_CONF0)
47d8215ff1SHadar Gat #define WORD4_CIPHER_CONF1 CC_HWQ_GENMASK(4, CIPHER_CONF1)
48d8215ff1SHadar Gat #define WORD4_CIPHER_CONF2 CC_HWQ_GENMASK(4, CIPHER_CONF2)
49d8215ff1SHadar Gat #define WORD4_CIPHER_DO CC_HWQ_GENMASK(4, CIPHER_DO)
50d8215ff1SHadar Gat #define WORD4_CIPHER_MODE CC_HWQ_GENMASK(4, CIPHER_MODE)
51d8215ff1SHadar Gat #define WORD4_CMAC_SIZE0 CC_HWQ_GENMASK(4, CMAC_SIZE0)
52d8215ff1SHadar Gat #define WORD4_DATA_FLOW_MODE CC_HWQ_GENMASK(4, DATA_FLOW_MODE)
53d8215ff1SHadar Gat #define WORD4_KEY_SIZE CC_HWQ_GENMASK(4, KEY_SIZE)
54d8215ff1SHadar Gat #define WORD4_SETUP_OPERATION CC_HWQ_GENMASK(4, SETUP_OPERATION)
55d8215ff1SHadar Gat #define WORD5_DIN_ADDR_HIGH CC_HWQ_GENMASK(5, DIN_ADDR_HIGH)
56d8215ff1SHadar Gat #define WORD5_DOUT_ADDR_HIGH CC_HWQ_GENMASK(5, DOUT_ADDR_HIGH)
574c3f9727SGilad Ben-Yossef
584c3f9727SGilad Ben-Yossef /******************************************************************************
594c3f9727SGilad Ben-Yossef * TYPE DEFINITIONS
604c3f9727SGilad Ben-Yossef ******************************************************************************/
614c3f9727SGilad Ben-Yossef
624c3f9727SGilad Ben-Yossef struct cc_hw_desc {
634c3f9727SGilad Ben-Yossef union {
644c3f9727SGilad Ben-Yossef u32 word[HW_DESC_SIZE_WORDS];
654c3f9727SGilad Ben-Yossef u16 hword[HW_DESC_SIZE_WORDS * 2];
664c3f9727SGilad Ben-Yossef };
674c3f9727SGilad Ben-Yossef };
684c3f9727SGilad Ben-Yossef
694c3f9727SGilad Ben-Yossef enum cc_axi_sec {
704c3f9727SGilad Ben-Yossef AXI_SECURE = 0,
714c3f9727SGilad Ben-Yossef AXI_NOT_SECURE = 1
724c3f9727SGilad Ben-Yossef };
734c3f9727SGilad Ben-Yossef
744c3f9727SGilad Ben-Yossef enum cc_desc_direction {
754c3f9727SGilad Ben-Yossef DESC_DIRECTION_ILLEGAL = -1,
764c3f9727SGilad Ben-Yossef DESC_DIRECTION_ENCRYPT_ENCRYPT = 0,
774c3f9727SGilad Ben-Yossef DESC_DIRECTION_DECRYPT_DECRYPT = 1,
784c3f9727SGilad Ben-Yossef DESC_DIRECTION_DECRYPT_ENCRYPT = 3,
794c3f9727SGilad Ben-Yossef DESC_DIRECTION_END = S32_MAX,
804c3f9727SGilad Ben-Yossef };
814c3f9727SGilad Ben-Yossef
824c3f9727SGilad Ben-Yossef enum cc_dma_mode {
834c3f9727SGilad Ben-Yossef DMA_MODE_NULL = -1,
844c3f9727SGilad Ben-Yossef NO_DMA = 0,
854c3f9727SGilad Ben-Yossef DMA_SRAM = 1,
864c3f9727SGilad Ben-Yossef DMA_DLLI = 2,
874c3f9727SGilad Ben-Yossef DMA_MLLI = 3,
884c3f9727SGilad Ben-Yossef DMA_MODE_END = S32_MAX,
894c3f9727SGilad Ben-Yossef };
904c3f9727SGilad Ben-Yossef
914c3f9727SGilad Ben-Yossef enum cc_flow_mode {
924c3f9727SGilad Ben-Yossef FLOW_MODE_NULL = -1,
934c3f9727SGilad Ben-Yossef /* data flows */
944c3f9727SGilad Ben-Yossef BYPASS = 0,
954c3f9727SGilad Ben-Yossef DIN_AES_DOUT = 1,
964c3f9727SGilad Ben-Yossef AES_to_HASH = 2,
974c3f9727SGilad Ben-Yossef AES_and_HASH = 3,
984c3f9727SGilad Ben-Yossef DIN_DES_DOUT = 4,
994c3f9727SGilad Ben-Yossef DES_to_HASH = 5,
1004c3f9727SGilad Ben-Yossef DES_and_HASH = 6,
1014c3f9727SGilad Ben-Yossef DIN_HASH = 7,
1024c3f9727SGilad Ben-Yossef DIN_HASH_and_BYPASS = 8,
1034c3f9727SGilad Ben-Yossef AESMAC_and_BYPASS = 9,
1044c3f9727SGilad Ben-Yossef AES_to_HASH_and_DOUT = 10,
1054c3f9727SGilad Ben-Yossef DIN_RC4_DOUT = 11,
1064c3f9727SGilad Ben-Yossef DES_to_HASH_and_DOUT = 12,
1074c3f9727SGilad Ben-Yossef AES_to_AES_to_HASH_and_DOUT = 13,
1084c3f9727SGilad Ben-Yossef AES_to_AES_to_HASH = 14,
1094c3f9727SGilad Ben-Yossef AES_to_HASH_and_AES = 15,
1109b8d51f8SGilad Ben-Yossef DIN_SM4_DOUT = 16,
1114c3f9727SGilad Ben-Yossef DIN_AES_AESMAC = 17,
1124c3f9727SGilad Ben-Yossef HASH_to_DOUT = 18,
1134c3f9727SGilad Ben-Yossef /* setup flows */
1144c3f9727SGilad Ben-Yossef S_DIN_to_AES = 32,
1154c3f9727SGilad Ben-Yossef S_DIN_to_AES2 = 33,
1164c3f9727SGilad Ben-Yossef S_DIN_to_DES = 34,
1174c3f9727SGilad Ben-Yossef S_DIN_to_RC4 = 35,
1189b8d51f8SGilad Ben-Yossef S_DIN_to_SM4 = 36,
1194c3f9727SGilad Ben-Yossef S_DIN_to_HASH = 37,
1204c3f9727SGilad Ben-Yossef S_AES_to_DOUT = 38,
1214c3f9727SGilad Ben-Yossef S_AES2_to_DOUT = 39,
1229b8d51f8SGilad Ben-Yossef S_SM4_to_DOUT = 40,
1234c3f9727SGilad Ben-Yossef S_RC4_to_DOUT = 41,
1244c3f9727SGilad Ben-Yossef S_DES_to_DOUT = 42,
1254c3f9727SGilad Ben-Yossef S_HASH_to_DOUT = 43,
1264c3f9727SGilad Ben-Yossef SET_FLOW_ID = 44,
1274c3f9727SGilad Ben-Yossef FLOW_MODE_END = S32_MAX,
1284c3f9727SGilad Ben-Yossef };
1294c3f9727SGilad Ben-Yossef
1304c3f9727SGilad Ben-Yossef enum cc_setup_op {
1314c3f9727SGilad Ben-Yossef SETUP_LOAD_NOP = 0,
1324c3f9727SGilad Ben-Yossef SETUP_LOAD_STATE0 = 1,
1334c3f9727SGilad Ben-Yossef SETUP_LOAD_STATE1 = 2,
1344c3f9727SGilad Ben-Yossef SETUP_LOAD_STATE2 = 3,
1354c3f9727SGilad Ben-Yossef SETUP_LOAD_KEY0 = 4,
1364c3f9727SGilad Ben-Yossef SETUP_LOAD_XEX_KEY = 5,
1374c3f9727SGilad Ben-Yossef SETUP_WRITE_STATE0 = 8,
1384c3f9727SGilad Ben-Yossef SETUP_WRITE_STATE1 = 9,
1394c3f9727SGilad Ben-Yossef SETUP_WRITE_STATE2 = 10,
1404c3f9727SGilad Ben-Yossef SETUP_WRITE_STATE3 = 11,
1414c3f9727SGilad Ben-Yossef SETUP_OP_END = S32_MAX,
1424c3f9727SGilad Ben-Yossef };
1434c3f9727SGilad Ben-Yossef
144f444ec10SGilad Ben-Yossef enum cc_hash_conf_pad {
145f444ec10SGilad Ben-Yossef HASH_PADDING_DISABLED = 0,
146f444ec10SGilad Ben-Yossef HASH_PADDING_ENABLED = 1,
147f444ec10SGilad Ben-Yossef HASH_DIGEST_RESULT_LITTLE_ENDIAN = 2,
148f444ec10SGilad Ben-Yossef HASH_CONFIG1_PADDING_RESERVE32 = S32_MAX,
149f444ec10SGilad Ben-Yossef };
150f444ec10SGilad Ben-Yossef
1514c3f9727SGilad Ben-Yossef enum cc_aes_mac_selector {
1524c3f9727SGilad Ben-Yossef AES_SK = 1,
1534c3f9727SGilad Ben-Yossef AES_CMAC_INIT = 2,
1544c3f9727SGilad Ben-Yossef AES_CMAC_SIZE0 = 3,
1554c3f9727SGilad Ben-Yossef AES_MAC_END = S32_MAX,
1564c3f9727SGilad Ben-Yossef };
1574c3f9727SGilad Ben-Yossef
1584c3f9727SGilad Ben-Yossef #define HW_KEY_MASK_CIPHER_DO 0x3
1594c3f9727SGilad Ben-Yossef #define HW_KEY_SHIFT_CIPHER_CFG2 2
1604c3f9727SGilad Ben-Yossef
1614c3f9727SGilad Ben-Yossef /* HwCryptoKey[1:0] is mapped to cipher_do[1:0] */
1624c3f9727SGilad Ben-Yossef /* HwCryptoKey[2:3] is mapped to cipher_config2[1:0] */
1634c3f9727SGilad Ben-Yossef enum cc_hw_crypto_key {
1644c3f9727SGilad Ben-Yossef USER_KEY = 0, /* 0x0000 */
1654c3f9727SGilad Ben-Yossef ROOT_KEY = 1, /* 0x0001 */
1664c3f9727SGilad Ben-Yossef PROVISIONING_KEY = 2, /* 0x0010 */ /* ==KCP */
1674c3f9727SGilad Ben-Yossef SESSION_KEY = 3, /* 0x0011 */
1684c3f9727SGilad Ben-Yossef RESERVED_KEY = 4, /* NA */
1694c3f9727SGilad Ben-Yossef PLATFORM_KEY = 5, /* 0x0101 */
1704c3f9727SGilad Ben-Yossef CUSTOMER_KEY = 6, /* 0x0110 */
1714c3f9727SGilad Ben-Yossef KFDE0_KEY = 7, /* 0x0111 */
1724c3f9727SGilad Ben-Yossef KFDE1_KEY = 9, /* 0x1001 */
1734c3f9727SGilad Ben-Yossef KFDE2_KEY = 10, /* 0x1010 */
1744c3f9727SGilad Ben-Yossef KFDE3_KEY = 11, /* 0x1011 */
1754c3f9727SGilad Ben-Yossef END_OF_KEYS = S32_MAX,
1764c3f9727SGilad Ben-Yossef };
1774c3f9727SGilad Ben-Yossef
17852f42c65SGilad Ben-Yossef #define CC_NUM_HW_KEY_SLOTS 4
17952f42c65SGilad Ben-Yossef #define CC_FIRST_HW_KEY_SLOT 0
18052f42c65SGilad Ben-Yossef #define CC_LAST_HW_KEY_SLOT (CC_FIRST_HW_KEY_SLOT + CC_NUM_HW_KEY_SLOTS - 1)
18152f42c65SGilad Ben-Yossef
18252f42c65SGilad Ben-Yossef #define CC_NUM_CPP_KEY_SLOTS 8
18352f42c65SGilad Ben-Yossef #define CC_FIRST_CPP_KEY_SLOT 16
18452f42c65SGilad Ben-Yossef #define CC_LAST_CPP_KEY_SLOT (CC_FIRST_CPP_KEY_SLOT + \
18552f42c65SGilad Ben-Yossef CC_NUM_CPP_KEY_SLOTS - 1)
18652f42c65SGilad Ben-Yossef
1874c3f9727SGilad Ben-Yossef enum cc_hw_aes_key_size {
1884c3f9727SGilad Ben-Yossef AES_128_KEY = 0,
1894c3f9727SGilad Ben-Yossef AES_192_KEY = 1,
1904c3f9727SGilad Ben-Yossef AES_256_KEY = 2,
1914c3f9727SGilad Ben-Yossef END_OF_AES_KEYS = S32_MAX,
1924c3f9727SGilad Ben-Yossef };
1934c3f9727SGilad Ben-Yossef
1944c3f9727SGilad Ben-Yossef enum cc_hash_cipher_pad {
1954c3f9727SGilad Ben-Yossef DO_NOT_PAD = 0,
1964c3f9727SGilad Ben-Yossef DO_PAD = 1,
1974c3f9727SGilad Ben-Yossef HASH_CIPHER_DO_PADDING_RESERVE32 = S32_MAX,
1984c3f9727SGilad Ben-Yossef };
1994c3f9727SGilad Ben-Yossef
200533edf9fSGilad Ben-Yossef #define CC_CPP_DIN_ADDR 0xFF00FF00UL
201533edf9fSGilad Ben-Yossef #define CC_CPP_DIN_SIZE 0xFF00FFUL
20252f42c65SGilad Ben-Yossef
2034c3f9727SGilad Ben-Yossef /*****************************/
2044c3f9727SGilad Ben-Yossef /* Descriptor packing macros */
2054c3f9727SGilad Ben-Yossef /*****************************/
2064c3f9727SGilad Ben-Yossef
20767b74a46SGeert Uytterhoeven /**
20867b74a46SGeert Uytterhoeven * hw_desc_init() - Init a HW descriptor struct
20967b74a46SGeert Uytterhoeven * @pdesc: pointer to HW descriptor struct
2104c3f9727SGilad Ben-Yossef */
hw_desc_init(struct cc_hw_desc * pdesc)2114c3f9727SGilad Ben-Yossef static inline void hw_desc_init(struct cc_hw_desc *pdesc)
2124c3f9727SGilad Ben-Yossef {
2134c3f9727SGilad Ben-Yossef memset(pdesc, 0, sizeof(struct cc_hw_desc));
2144c3f9727SGilad Ben-Yossef }
2154c3f9727SGilad Ben-Yossef
21667b74a46SGeert Uytterhoeven /**
21767b74a46SGeert Uytterhoeven * set_queue_last_ind_bit() - Indicate the end of current HW descriptors flow
21867b74a46SGeert Uytterhoeven * and release the HW engines.
2194c3f9727SGilad Ben-Yossef *
22067b74a46SGeert Uytterhoeven * @pdesc: Pointer to HW descriptor struct
2214c3f9727SGilad Ben-Yossef */
set_queue_last_ind_bit(struct cc_hw_desc * pdesc)22227b3b22dSGilad Ben-Yossef static inline void set_queue_last_ind_bit(struct cc_hw_desc *pdesc)
2234c3f9727SGilad Ben-Yossef {
2244c3f9727SGilad Ben-Yossef pdesc->word[3] |= FIELD_PREP(WORD3_QUEUE_LAST_IND, 1);
2254c3f9727SGilad Ben-Yossef }
2264c3f9727SGilad Ben-Yossef
22767b74a46SGeert Uytterhoeven /**
22867b74a46SGeert Uytterhoeven * set_din_type() - Set the DIN field of a HW descriptor
2294c3f9727SGilad Ben-Yossef *
23067b74a46SGeert Uytterhoeven * @pdesc: Pointer to HW descriptor struct
23167b74a46SGeert Uytterhoeven * @dma_mode: The DMA mode: NO_DMA, SRAM, DLLI, MLLI, CONSTANT
23267b74a46SGeert Uytterhoeven * @addr: DIN address
2334c3f9727SGilad Ben-Yossef * @size: Data size in bytes
2344c3f9727SGilad Ben-Yossef * @axi_sec: AXI secure bit
2354c3f9727SGilad Ben-Yossef */
set_din_type(struct cc_hw_desc * pdesc,enum cc_dma_mode dma_mode,dma_addr_t addr,u32 size,enum cc_axi_sec axi_sec)2364c3f9727SGilad Ben-Yossef static inline void set_din_type(struct cc_hw_desc *pdesc,
2374c3f9727SGilad Ben-Yossef enum cc_dma_mode dma_mode, dma_addr_t addr,
2384c3f9727SGilad Ben-Yossef u32 size, enum cc_axi_sec axi_sec)
2394c3f9727SGilad Ben-Yossef {
2405fabab0dSGeert Uytterhoeven pdesc->word[0] = lower_32_bits(addr);
2414c3f9727SGilad Ben-Yossef #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2425fabab0dSGeert Uytterhoeven pdesc->word[5] |= FIELD_PREP(WORD5_DIN_ADDR_HIGH, upper_32_bits(addr));
2434c3f9727SGilad Ben-Yossef #endif
2444c3f9727SGilad Ben-Yossef pdesc->word[1] |= FIELD_PREP(WORD1_DIN_DMA_MODE, dma_mode) |
2454c3f9727SGilad Ben-Yossef FIELD_PREP(WORD1_DIN_SIZE, size) |
2464c3f9727SGilad Ben-Yossef FIELD_PREP(WORD1_NS_BIT, axi_sec);
2474c3f9727SGilad Ben-Yossef }
2484c3f9727SGilad Ben-Yossef
24967b74a46SGeert Uytterhoeven /**
25067b74a46SGeert Uytterhoeven * set_din_no_dma() - Set the DIN field of a HW descriptor to NO DMA mode.
2514c3f9727SGilad Ben-Yossef * Used for NOP descriptor, register patches and other special modes.
2524c3f9727SGilad Ben-Yossef *
25367b74a46SGeert Uytterhoeven * @pdesc: Pointer to HW descriptor struct
2544c3f9727SGilad Ben-Yossef * @addr: DIN address
2554c3f9727SGilad Ben-Yossef * @size: Data size in bytes
2564c3f9727SGilad Ben-Yossef */
set_din_no_dma(struct cc_hw_desc * pdesc,u32 addr,u32 size)2574c3f9727SGilad Ben-Yossef static inline void set_din_no_dma(struct cc_hw_desc *pdesc, u32 addr, u32 size)
2584c3f9727SGilad Ben-Yossef {
2594c3f9727SGilad Ben-Yossef pdesc->word[0] = addr;
2604c3f9727SGilad Ben-Yossef pdesc->word[1] |= FIELD_PREP(WORD1_DIN_SIZE, size);
2614c3f9727SGilad Ben-Yossef }
2624c3f9727SGilad Ben-Yossef
26367b74a46SGeert Uytterhoeven /**
26467b74a46SGeert Uytterhoeven * set_cpp_crypto_key() - Setup the special CPP descriptor
26552f42c65SGilad Ben-Yossef *
26667b74a46SGeert Uytterhoeven * @pdesc: Pointer to HW descriptor struct
26767b74a46SGeert Uytterhoeven * @slot: Slot number
26852f42c65SGilad Ben-Yossef */
set_cpp_crypto_key(struct cc_hw_desc * pdesc,u8 slot)269533edf9fSGilad Ben-Yossef static inline void set_cpp_crypto_key(struct cc_hw_desc *pdesc, u8 slot)
27052f42c65SGilad Ben-Yossef {
271533edf9fSGilad Ben-Yossef pdesc->word[0] |= CC_CPP_DIN_ADDR;
27252f42c65SGilad Ben-Yossef
273533edf9fSGilad Ben-Yossef pdesc->word[1] |= FIELD_PREP(WORD1_DIN_SIZE, CC_CPP_DIN_SIZE);
27452f42c65SGilad Ben-Yossef pdesc->word[1] |= FIELD_PREP(WORD1_LOCK_QUEUE, 1);
275533edf9fSGilad Ben-Yossef
276533edf9fSGilad Ben-Yossef pdesc->word[4] |= FIELD_PREP(WORD4_SETUP_OPERATION, slot);
27752f42c65SGilad Ben-Yossef }
27852f42c65SGilad Ben-Yossef
27967b74a46SGeert Uytterhoeven /**
28067b74a46SGeert Uytterhoeven * set_din_sram() - Set the DIN field of a HW descriptor to SRAM mode.
2814c3f9727SGilad Ben-Yossef * Note: No need to check SRAM alignment since host requests do not use SRAM and
28267b74a46SGeert Uytterhoeven * the adaptor will enforce alignment checks.
2834c3f9727SGilad Ben-Yossef *
28467b74a46SGeert Uytterhoeven * @pdesc: Pointer to HW descriptor struct
2854c3f9727SGilad Ben-Yossef * @addr: DIN address
28667b74a46SGeert Uytterhoeven * @size: Data size in bytes
2874c3f9727SGilad Ben-Yossef */
set_din_sram(struct cc_hw_desc * pdesc,u32 addr,u32 size)2881a895f1dSGeert Uytterhoeven static inline void set_din_sram(struct cc_hw_desc *pdesc, u32 addr, u32 size)
2894c3f9727SGilad Ben-Yossef {
2901a895f1dSGeert Uytterhoeven pdesc->word[0] = addr;
2914c3f9727SGilad Ben-Yossef pdesc->word[1] |= FIELD_PREP(WORD1_DIN_SIZE, size) |
2924c3f9727SGilad Ben-Yossef FIELD_PREP(WORD1_DIN_DMA_MODE, DMA_SRAM);
2934c3f9727SGilad Ben-Yossef }
2944c3f9727SGilad Ben-Yossef
29567b74a46SGeert Uytterhoeven /**
29667b74a46SGeert Uytterhoeven * set_din_const() - Set the DIN field of a HW descriptor to CONST mode
2974c3f9727SGilad Ben-Yossef *
29867b74a46SGeert Uytterhoeven * @pdesc: Pointer to HW descriptor struct
2994c3f9727SGilad Ben-Yossef * @val: DIN const value
3004c3f9727SGilad Ben-Yossef * @size: Data size in bytes
3014c3f9727SGilad Ben-Yossef */
set_din_const(struct cc_hw_desc * pdesc,u32 val,u32 size)3024c3f9727SGilad Ben-Yossef static inline void set_din_const(struct cc_hw_desc *pdesc, u32 val, u32 size)
3034c3f9727SGilad Ben-Yossef {
3044c3f9727SGilad Ben-Yossef pdesc->word[0] = val;
3054c3f9727SGilad Ben-Yossef pdesc->word[1] |= FIELD_PREP(WORD1_DIN_CONST_VALUE, 1) |
3064c3f9727SGilad Ben-Yossef FIELD_PREP(WORD1_DIN_DMA_MODE, DMA_SRAM) |
3074c3f9727SGilad Ben-Yossef FIELD_PREP(WORD1_DIN_SIZE, size);
3084c3f9727SGilad Ben-Yossef }
3094c3f9727SGilad Ben-Yossef
31067b74a46SGeert Uytterhoeven /**
31167b74a46SGeert Uytterhoeven * set_din_not_last_indication() - Set the DIN not last input data indicator
3124c3f9727SGilad Ben-Yossef *
31367b74a46SGeert Uytterhoeven * @pdesc: Pointer to HW descriptor struct
3144c3f9727SGilad Ben-Yossef */
set_din_not_last_indication(struct cc_hw_desc * pdesc)3154c3f9727SGilad Ben-Yossef static inline void set_din_not_last_indication(struct cc_hw_desc *pdesc)
3164c3f9727SGilad Ben-Yossef {
3174c3f9727SGilad Ben-Yossef pdesc->word[1] |= FIELD_PREP(WORD1_NOT_LAST, 1);
3184c3f9727SGilad Ben-Yossef }
3194c3f9727SGilad Ben-Yossef
32067b74a46SGeert Uytterhoeven /**
32167b74a46SGeert Uytterhoeven * set_dout_type() - Set the DOUT field of a HW descriptor
3224c3f9727SGilad Ben-Yossef *
32367b74a46SGeert Uytterhoeven * @pdesc: Pointer to HW descriptor struct
3244c3f9727SGilad Ben-Yossef * @dma_mode: The DMA mode: NO_DMA, SRAM, DLLI, MLLI, CONSTANT
3254c3f9727SGilad Ben-Yossef * @addr: DOUT address
3264c3f9727SGilad Ben-Yossef * @size: Data size in bytes
3274c3f9727SGilad Ben-Yossef * @axi_sec: AXI secure bit
3284c3f9727SGilad Ben-Yossef */
set_dout_type(struct cc_hw_desc * pdesc,enum cc_dma_mode dma_mode,dma_addr_t addr,u32 size,enum cc_axi_sec axi_sec)3294c3f9727SGilad Ben-Yossef static inline void set_dout_type(struct cc_hw_desc *pdesc,
3304c3f9727SGilad Ben-Yossef enum cc_dma_mode dma_mode, dma_addr_t addr,
3314c3f9727SGilad Ben-Yossef u32 size, enum cc_axi_sec axi_sec)
3324c3f9727SGilad Ben-Yossef {
3335fabab0dSGeert Uytterhoeven pdesc->word[2] = lower_32_bits(addr);
3344c3f9727SGilad Ben-Yossef #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3355fabab0dSGeert Uytterhoeven pdesc->word[5] |= FIELD_PREP(WORD5_DOUT_ADDR_HIGH, upper_32_bits(addr));
3364c3f9727SGilad Ben-Yossef #endif
3374c3f9727SGilad Ben-Yossef pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_DMA_MODE, dma_mode) |
3384c3f9727SGilad Ben-Yossef FIELD_PREP(WORD3_DOUT_SIZE, size) |
3394c3f9727SGilad Ben-Yossef FIELD_PREP(WORD3_NS_BIT, axi_sec);
3404c3f9727SGilad Ben-Yossef }
3414c3f9727SGilad Ben-Yossef
34267b74a46SGeert Uytterhoeven /**
34367b74a46SGeert Uytterhoeven * set_dout_dlli() - Set the DOUT field of a HW descriptor to DLLI type
3444c3f9727SGilad Ben-Yossef * The LAST INDICATION is provided by the user
3454c3f9727SGilad Ben-Yossef *
34667b74a46SGeert Uytterhoeven * @pdesc: Pointer to HW descriptor struct
3474c3f9727SGilad Ben-Yossef * @addr: DOUT address
3484c3f9727SGilad Ben-Yossef * @size: Data size in bytes
3494c3f9727SGilad Ben-Yossef * @axi_sec: AXI secure bit
35067b74a46SGeert Uytterhoeven * @last_ind: The last indication bit
3514c3f9727SGilad Ben-Yossef */
set_dout_dlli(struct cc_hw_desc * pdesc,dma_addr_t addr,u32 size,enum cc_axi_sec axi_sec,u32 last_ind)3524c3f9727SGilad Ben-Yossef static inline void set_dout_dlli(struct cc_hw_desc *pdesc, dma_addr_t addr,
3534c3f9727SGilad Ben-Yossef u32 size, enum cc_axi_sec axi_sec,
3544c3f9727SGilad Ben-Yossef u32 last_ind)
3554c3f9727SGilad Ben-Yossef {
3564c3f9727SGilad Ben-Yossef set_dout_type(pdesc, DMA_DLLI, addr, size, axi_sec);
3574c3f9727SGilad Ben-Yossef pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_LAST_IND, last_ind);
3584c3f9727SGilad Ben-Yossef }
3594c3f9727SGilad Ben-Yossef
36067b74a46SGeert Uytterhoeven /**
36167b74a46SGeert Uytterhoeven * set_dout_mlli() - Set the DOUT field of a HW descriptor to MLLI type
3624c3f9727SGilad Ben-Yossef * The LAST INDICATION is provided by the user
3634c3f9727SGilad Ben-Yossef *
36467b74a46SGeert Uytterhoeven * @pdesc: Pointer to HW descriptor struct
3654c3f9727SGilad Ben-Yossef * @addr: DOUT address
3664c3f9727SGilad Ben-Yossef * @size: Data size in bytes
3674c3f9727SGilad Ben-Yossef * @axi_sec: AXI secure bit
36867b74a46SGeert Uytterhoeven * @last_ind: The last indication bit
3694c3f9727SGilad Ben-Yossef */
set_dout_mlli(struct cc_hw_desc * pdesc,u32 addr,u32 size,enum cc_axi_sec axi_sec,bool last_ind)3701a895f1dSGeert Uytterhoeven static inline void set_dout_mlli(struct cc_hw_desc *pdesc, u32 addr, u32 size,
3711a895f1dSGeert Uytterhoeven enum cc_axi_sec axi_sec, bool last_ind)
3724c3f9727SGilad Ben-Yossef {
3734c3f9727SGilad Ben-Yossef set_dout_type(pdesc, DMA_MLLI, addr, size, axi_sec);
3744c3f9727SGilad Ben-Yossef pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_LAST_IND, last_ind);
3754c3f9727SGilad Ben-Yossef }
3764c3f9727SGilad Ben-Yossef
37767b74a46SGeert Uytterhoeven /**
37867b74a46SGeert Uytterhoeven * set_dout_no_dma() - Set the DOUT field of a HW descriptor to NO DMA mode.
3794c3f9727SGilad Ben-Yossef * Used for NOP descriptor, register patches and other special modes.
3804c3f9727SGilad Ben-Yossef *
38167b74a46SGeert Uytterhoeven * @pdesc: pointer to HW descriptor struct
3824c3f9727SGilad Ben-Yossef * @addr: DOUT address
3834c3f9727SGilad Ben-Yossef * @size: Data size in bytes
3844c3f9727SGilad Ben-Yossef * @write_enable: Enables a write operation to a register
3854c3f9727SGilad Ben-Yossef */
set_dout_no_dma(struct cc_hw_desc * pdesc,u32 addr,u32 size,bool write_enable)3864c3f9727SGilad Ben-Yossef static inline void set_dout_no_dma(struct cc_hw_desc *pdesc, u32 addr,
3874c3f9727SGilad Ben-Yossef u32 size, bool write_enable)
3884c3f9727SGilad Ben-Yossef {
3894c3f9727SGilad Ben-Yossef pdesc->word[2] = addr;
3904c3f9727SGilad Ben-Yossef pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_SIZE, size) |
3914c3f9727SGilad Ben-Yossef FIELD_PREP(WORD3_DOUT_LAST_IND, write_enable);
3924c3f9727SGilad Ben-Yossef }
3934c3f9727SGilad Ben-Yossef
39467b74a46SGeert Uytterhoeven /**
39567b74a46SGeert Uytterhoeven * set_xor_val() - Set the word for the XOR operation.
3964c3f9727SGilad Ben-Yossef *
39767b74a46SGeert Uytterhoeven * @pdesc: Pointer to HW descriptor struct
39867b74a46SGeert Uytterhoeven * @val: XOR data value
3994c3f9727SGilad Ben-Yossef */
set_xor_val(struct cc_hw_desc * pdesc,u32 val)4004c3f9727SGilad Ben-Yossef static inline void set_xor_val(struct cc_hw_desc *pdesc, u32 val)
4014c3f9727SGilad Ben-Yossef {
4024c3f9727SGilad Ben-Yossef pdesc->word[2] = val;
4034c3f9727SGilad Ben-Yossef }
4044c3f9727SGilad Ben-Yossef
40567b74a46SGeert Uytterhoeven /**
40667b74a46SGeert Uytterhoeven * set_xor_active() - Set the XOR indicator bit in the descriptor
4074c3f9727SGilad Ben-Yossef *
40867b74a46SGeert Uytterhoeven * @pdesc: Pointer to HW descriptor struct
4094c3f9727SGilad Ben-Yossef */
set_xor_active(struct cc_hw_desc * pdesc)4104c3f9727SGilad Ben-Yossef static inline void set_xor_active(struct cc_hw_desc *pdesc)
4114c3f9727SGilad Ben-Yossef {
4124c3f9727SGilad Ben-Yossef pdesc->word[3] |= FIELD_PREP(WORD3_HASH_XOR_BIT, 1);
4134c3f9727SGilad Ben-Yossef }
4144c3f9727SGilad Ben-Yossef
41567b74a46SGeert Uytterhoeven /**
41667b74a46SGeert Uytterhoeven * set_aes_not_hash_mode() - Select the AES engine instead of HASH engine when
41767b74a46SGeert Uytterhoeven * setting up combined mode with AES XCBC MAC
4184c3f9727SGilad Ben-Yossef *
41967b74a46SGeert Uytterhoeven * @pdesc: Pointer to HW descriptor struct
4204c3f9727SGilad Ben-Yossef */
set_aes_not_hash_mode(struct cc_hw_desc * pdesc)4214c3f9727SGilad Ben-Yossef static inline void set_aes_not_hash_mode(struct cc_hw_desc *pdesc)
4224c3f9727SGilad Ben-Yossef {
4234c3f9727SGilad Ben-Yossef pdesc->word[4] |= FIELD_PREP(WORD4_AES_SEL_N_HASH, 1);
4244c3f9727SGilad Ben-Yossef }
4254c3f9727SGilad Ben-Yossef
42667b74a46SGeert Uytterhoeven /**
42767b74a46SGeert Uytterhoeven * set_aes_xor_crypto_key() - Set aes xor crypto key, which in some scenarios
42867b74a46SGeert Uytterhoeven * selects the SM3 engine
429927574e0SYael Chemla *
43067b74a46SGeert Uytterhoeven * @pdesc: Pointer to HW descriptor struct
431927574e0SYael Chemla */
set_aes_xor_crypto_key(struct cc_hw_desc * pdesc)432927574e0SYael Chemla static inline void set_aes_xor_crypto_key(struct cc_hw_desc *pdesc)
433927574e0SYael Chemla {
434927574e0SYael Chemla pdesc->word[4] |= FIELD_PREP(WORD4_AES_XOR_CRYPTO_KEY, 1);
435927574e0SYael Chemla }
436927574e0SYael Chemla
43767b74a46SGeert Uytterhoeven /**
43867b74a46SGeert Uytterhoeven * set_dout_sram() - Set the DOUT field of a HW descriptor to SRAM mode
4394c3f9727SGilad Ben-Yossef * Note: No need to check SRAM alignment since host requests do not use SRAM and
44067b74a46SGeert Uytterhoeven * the adaptor will enforce alignment checks.
4414c3f9727SGilad Ben-Yossef *
44267b74a46SGeert Uytterhoeven * @pdesc: Pointer to HW descriptor struct
4434c3f9727SGilad Ben-Yossef * @addr: DOUT address
4444c3f9727SGilad Ben-Yossef * @size: Data size in bytes
4454c3f9727SGilad Ben-Yossef */
set_dout_sram(struct cc_hw_desc * pdesc,u32 addr,u32 size)4464c3f9727SGilad Ben-Yossef static inline void set_dout_sram(struct cc_hw_desc *pdesc, u32 addr, u32 size)
4474c3f9727SGilad Ben-Yossef {
4484c3f9727SGilad Ben-Yossef pdesc->word[2] = addr;
4494c3f9727SGilad Ben-Yossef pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_DMA_MODE, DMA_SRAM) |
4504c3f9727SGilad Ben-Yossef FIELD_PREP(WORD3_DOUT_SIZE, size);
4514c3f9727SGilad Ben-Yossef }
4524c3f9727SGilad Ben-Yossef
45367b74a46SGeert Uytterhoeven /**
45467b74a46SGeert Uytterhoeven * set_xex_data_unit_size() - Set the data unit size for XEX mode in
45567b74a46SGeert Uytterhoeven * data_out_addr[15:0]
4564c3f9727SGilad Ben-Yossef *
45767b74a46SGeert Uytterhoeven * @pdesc: Pointer to HW descriptor struct
45867b74a46SGeert Uytterhoeven * @size: Data unit size for XEX mode
4594c3f9727SGilad Ben-Yossef */
set_xex_data_unit_size(struct cc_hw_desc * pdesc,u32 size)4604c3f9727SGilad Ben-Yossef static inline void set_xex_data_unit_size(struct cc_hw_desc *pdesc, u32 size)
4614c3f9727SGilad Ben-Yossef {
4624c3f9727SGilad Ben-Yossef pdesc->word[2] = size;
4634c3f9727SGilad Ben-Yossef }
4644c3f9727SGilad Ben-Yossef
46567b74a46SGeert Uytterhoeven /**
46667b74a46SGeert Uytterhoeven * set_multi2_num_rounds() - Set the number of rounds for Multi2 in
46767b74a46SGeert Uytterhoeven * data_out_addr[15:0]
4684c3f9727SGilad Ben-Yossef *
46967b74a46SGeert Uytterhoeven * @pdesc: Pointer to HW descriptor struct
47067b74a46SGeert Uytterhoeven * @num: Number of rounds for Multi2
4714c3f9727SGilad Ben-Yossef */
set_multi2_num_rounds(struct cc_hw_desc * pdesc,u32 num)4724c3f9727SGilad Ben-Yossef static inline void set_multi2_num_rounds(struct cc_hw_desc *pdesc, u32 num)
4734c3f9727SGilad Ben-Yossef {
4744c3f9727SGilad Ben-Yossef pdesc->word[2] = num;
4754c3f9727SGilad Ben-Yossef }
4764c3f9727SGilad Ben-Yossef
47767b74a46SGeert Uytterhoeven /**
47867b74a46SGeert Uytterhoeven * set_flow_mode() - Set the flow mode.
4794c3f9727SGilad Ben-Yossef *
48067b74a46SGeert Uytterhoeven * @pdesc: Pointer to HW descriptor struct
4814c3f9727SGilad Ben-Yossef * @mode: Any one of the modes defined in [CC7x-DESC]
4824c3f9727SGilad Ben-Yossef */
set_flow_mode(struct cc_hw_desc * pdesc,enum cc_flow_mode mode)4834c3f9727SGilad Ben-Yossef static inline void set_flow_mode(struct cc_hw_desc *pdesc,
4844c3f9727SGilad Ben-Yossef enum cc_flow_mode mode)
4854c3f9727SGilad Ben-Yossef {
4864c3f9727SGilad Ben-Yossef pdesc->word[4] |= FIELD_PREP(WORD4_DATA_FLOW_MODE, mode);
4874c3f9727SGilad Ben-Yossef }
4884c3f9727SGilad Ben-Yossef
48967b74a46SGeert Uytterhoeven /**
49067b74a46SGeert Uytterhoeven * set_cipher_mode() - Set the cipher mode.
4914c3f9727SGilad Ben-Yossef *
49267b74a46SGeert Uytterhoeven * @pdesc: Pointer to HW descriptor struct
4934c3f9727SGilad Ben-Yossef * @mode: Any one of the modes defined in [CC7x-DESC]
4944c3f9727SGilad Ben-Yossef */
set_cipher_mode(struct cc_hw_desc * pdesc,int mode)49518e732b8SNathan Chancellor static inline void set_cipher_mode(struct cc_hw_desc *pdesc, int mode)
4964c3f9727SGilad Ben-Yossef {
4974c3f9727SGilad Ben-Yossef pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_MODE, mode);
4984c3f9727SGilad Ben-Yossef }
4994c3f9727SGilad Ben-Yossef
50067b74a46SGeert Uytterhoeven /**
50167b74a46SGeert Uytterhoeven * set_hash_cipher_mode() - Set the cipher mode for hash algorithms.
50218a1dc1fSYael Chemla *
50367b74a46SGeert Uytterhoeven * @pdesc: Pointer to HW descriptor struct
50418a1dc1fSYael Chemla * @cipher_mode: Any one of the modes defined in [CC7x-DESC]
50518a1dc1fSYael Chemla * @hash_mode: specifies which hash is being handled
50618a1dc1fSYael Chemla */
set_hash_cipher_mode(struct cc_hw_desc * pdesc,enum drv_cipher_mode cipher_mode,enum drv_hash_mode hash_mode)50718a1dc1fSYael Chemla static inline void set_hash_cipher_mode(struct cc_hw_desc *pdesc,
50818a1dc1fSYael Chemla enum drv_cipher_mode cipher_mode,
50918a1dc1fSYael Chemla enum drv_hash_mode hash_mode)
51018a1dc1fSYael Chemla {
51118a1dc1fSYael Chemla set_cipher_mode(pdesc, cipher_mode);
512927574e0SYael Chemla if (hash_mode == DRV_HASH_SM3)
513927574e0SYael Chemla set_aes_xor_crypto_key(pdesc);
51418a1dc1fSYael Chemla }
51518a1dc1fSYael Chemla
51667b74a46SGeert Uytterhoeven /**
51767b74a46SGeert Uytterhoeven * set_cipher_config0() - Set the cipher configuration fields.
5184c3f9727SGilad Ben-Yossef *
51967b74a46SGeert Uytterhoeven * @pdesc: Pointer to HW descriptor struct
5204c3f9727SGilad Ben-Yossef * @mode: Any one of the modes defined in [CC7x-DESC]
5214c3f9727SGilad Ben-Yossef */
set_cipher_config0(struct cc_hw_desc * pdesc,int mode)52218e732b8SNathan Chancellor static inline void set_cipher_config0(struct cc_hw_desc *pdesc, int mode)
5234c3f9727SGilad Ben-Yossef {
5244c3f9727SGilad Ben-Yossef pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_CONF0, mode);
5254c3f9727SGilad Ben-Yossef }
5264c3f9727SGilad Ben-Yossef
52767b74a46SGeert Uytterhoeven /**
52867b74a46SGeert Uytterhoeven * set_cipher_config1() - Set the cipher configuration fields.
5294c3f9727SGilad Ben-Yossef *
53067b74a46SGeert Uytterhoeven * @pdesc: Pointer to HW descriptor struct
53167b74a46SGeert Uytterhoeven * @config: Padding mode
5324c3f9727SGilad Ben-Yossef */
set_cipher_config1(struct cc_hw_desc * pdesc,enum cc_hash_conf_pad config)5334c3f9727SGilad Ben-Yossef static inline void set_cipher_config1(struct cc_hw_desc *pdesc,
5344c3f9727SGilad Ben-Yossef enum cc_hash_conf_pad config)
5354c3f9727SGilad Ben-Yossef {
5364c3f9727SGilad Ben-Yossef pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_CONF1, config);
5374c3f9727SGilad Ben-Yossef }
5384c3f9727SGilad Ben-Yossef
53967b74a46SGeert Uytterhoeven /**
54067b74a46SGeert Uytterhoeven * set_hw_crypto_key() - Set HW key configuration fields.
5414c3f9727SGilad Ben-Yossef *
54267b74a46SGeert Uytterhoeven * @pdesc: Pointer to HW descriptor struct
5434c3f9727SGilad Ben-Yossef * @hw_key: The HW key slot asdefined in enum cc_hw_crypto_key
5444c3f9727SGilad Ben-Yossef */
set_hw_crypto_key(struct cc_hw_desc * pdesc,enum cc_hw_crypto_key hw_key)5454c3f9727SGilad Ben-Yossef static inline void set_hw_crypto_key(struct cc_hw_desc *pdesc,
5464c3f9727SGilad Ben-Yossef enum cc_hw_crypto_key hw_key)
5474c3f9727SGilad Ben-Yossef {
5484c3f9727SGilad Ben-Yossef pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_DO,
5494c3f9727SGilad Ben-Yossef (hw_key & HW_KEY_MASK_CIPHER_DO)) |
5504c3f9727SGilad Ben-Yossef FIELD_PREP(WORD4_CIPHER_CONF2,
5514c3f9727SGilad Ben-Yossef (hw_key >> HW_KEY_SHIFT_CIPHER_CFG2));
5524c3f9727SGilad Ben-Yossef }
5534c3f9727SGilad Ben-Yossef
55467b74a46SGeert Uytterhoeven /**
55567b74a46SGeert Uytterhoeven * set_bytes_swap() - Set byte order of all setup-finalize descriptors.
5564c3f9727SGilad Ben-Yossef *
55767b74a46SGeert Uytterhoeven * @pdesc: Pointer to HW descriptor struct
55867b74a46SGeert Uytterhoeven * @config: True to enable byte swapping
5594c3f9727SGilad Ben-Yossef */
set_bytes_swap(struct cc_hw_desc * pdesc,bool config)5604c3f9727SGilad Ben-Yossef static inline void set_bytes_swap(struct cc_hw_desc *pdesc, bool config)
5614c3f9727SGilad Ben-Yossef {
5624c3f9727SGilad Ben-Yossef pdesc->word[4] |= FIELD_PREP(WORD4_BYTES_SWAP, config);
5634c3f9727SGilad Ben-Yossef }
5644c3f9727SGilad Ben-Yossef
56567b74a46SGeert Uytterhoeven /**
56667b74a46SGeert Uytterhoeven * set_cmac_size0_mode() - Set CMAC_SIZE0 mode.
5674c3f9727SGilad Ben-Yossef *
56867b74a46SGeert Uytterhoeven * @pdesc: Pointer to HW descriptor struct
5694c3f9727SGilad Ben-Yossef */
set_cmac_size0_mode(struct cc_hw_desc * pdesc)5704c3f9727SGilad Ben-Yossef static inline void set_cmac_size0_mode(struct cc_hw_desc *pdesc)
5714c3f9727SGilad Ben-Yossef {
5724c3f9727SGilad Ben-Yossef pdesc->word[4] |= FIELD_PREP(WORD4_CMAC_SIZE0, 1);
5734c3f9727SGilad Ben-Yossef }
5744c3f9727SGilad Ben-Yossef
57567b74a46SGeert Uytterhoeven /**
57667b74a46SGeert Uytterhoeven * set_key_size() - Set key size descriptor field.
5774c3f9727SGilad Ben-Yossef *
57867b74a46SGeert Uytterhoeven * @pdesc: Pointer to HW descriptor struct
57967b74a46SGeert Uytterhoeven * @size: Key size in bytes (NOT size code)
5804c3f9727SGilad Ben-Yossef */
set_key_size(struct cc_hw_desc * pdesc,u32 size)5814c3f9727SGilad Ben-Yossef static inline void set_key_size(struct cc_hw_desc *pdesc, u32 size)
5824c3f9727SGilad Ben-Yossef {
5834c3f9727SGilad Ben-Yossef pdesc->word[4] |= FIELD_PREP(WORD4_KEY_SIZE, size);
5844c3f9727SGilad Ben-Yossef }
5854c3f9727SGilad Ben-Yossef
58667b74a46SGeert Uytterhoeven /**
58767b74a46SGeert Uytterhoeven * set_key_size_aes() - Set AES key size.
5884c3f9727SGilad Ben-Yossef *
58967b74a46SGeert Uytterhoeven * @pdesc: Pointer to HW descriptor struct
59067b74a46SGeert Uytterhoeven * @size: Key size in bytes (NOT size code)
5914c3f9727SGilad Ben-Yossef */
set_key_size_aes(struct cc_hw_desc * pdesc,u32 size)5924c3f9727SGilad Ben-Yossef static inline void set_key_size_aes(struct cc_hw_desc *pdesc, u32 size)
5934c3f9727SGilad Ben-Yossef {
5944c3f9727SGilad Ben-Yossef set_key_size(pdesc, ((size >> 3) - 2));
5954c3f9727SGilad Ben-Yossef }
5964c3f9727SGilad Ben-Yossef
59767b74a46SGeert Uytterhoeven /**
59867b74a46SGeert Uytterhoeven * set_key_size_des() - Set DES key size.
5994c3f9727SGilad Ben-Yossef *
60067b74a46SGeert Uytterhoeven * @pdesc: Pointer to HW descriptor struct
60167b74a46SGeert Uytterhoeven * @size: Key size in bytes (NOT size code)
6024c3f9727SGilad Ben-Yossef */
set_key_size_des(struct cc_hw_desc * pdesc,u32 size)6034c3f9727SGilad Ben-Yossef static inline void set_key_size_des(struct cc_hw_desc *pdesc, u32 size)
6044c3f9727SGilad Ben-Yossef {
6054c3f9727SGilad Ben-Yossef set_key_size(pdesc, ((size >> 3) - 1));
6064c3f9727SGilad Ben-Yossef }
6074c3f9727SGilad Ben-Yossef
60867b74a46SGeert Uytterhoeven /**
60967b74a46SGeert Uytterhoeven * set_setup_mode() - Set the descriptor setup mode
6104c3f9727SGilad Ben-Yossef *
61167b74a46SGeert Uytterhoeven * @pdesc: Pointer to HW descriptor struct
6124c3f9727SGilad Ben-Yossef * @mode: Any one of the setup modes defined in [CC7x-DESC]
6134c3f9727SGilad Ben-Yossef */
set_setup_mode(struct cc_hw_desc * pdesc,enum cc_setup_op mode)6144c3f9727SGilad Ben-Yossef static inline void set_setup_mode(struct cc_hw_desc *pdesc,
6154c3f9727SGilad Ben-Yossef enum cc_setup_op mode)
6164c3f9727SGilad Ben-Yossef {
6174c3f9727SGilad Ben-Yossef pdesc->word[4] |= FIELD_PREP(WORD4_SETUP_OPERATION, mode);
6184c3f9727SGilad Ben-Yossef }
6194c3f9727SGilad Ben-Yossef
62067b74a46SGeert Uytterhoeven /**
62167b74a46SGeert Uytterhoeven * set_cipher_do() - Set the descriptor cipher DO
6224c3f9727SGilad Ben-Yossef *
62367b74a46SGeert Uytterhoeven * @pdesc: Pointer to HW descriptor struct
6244c3f9727SGilad Ben-Yossef * @config: Any one of the cipher do defined in [CC7x-DESC]
6254c3f9727SGilad Ben-Yossef */
set_cipher_do(struct cc_hw_desc * pdesc,enum cc_hash_cipher_pad config)6264c3f9727SGilad Ben-Yossef static inline void set_cipher_do(struct cc_hw_desc *pdesc,
6274c3f9727SGilad Ben-Yossef enum cc_hash_cipher_pad config)
6284c3f9727SGilad Ben-Yossef {
6294c3f9727SGilad Ben-Yossef pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_DO,
6304c3f9727SGilad Ben-Yossef (config & HW_KEY_MASK_CIPHER_DO));
6314c3f9727SGilad Ben-Yossef }
6324c3f9727SGilad Ben-Yossef
6334c3f9727SGilad Ben-Yossef #endif /*__CC_HW_QUEUE_DEFS_H__*/
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