163893811SGilad Ben-Yossef /* SPDX-License-Identifier: GPL-2.0 */ 263893811SGilad Ben-Yossef /* Copyright (C) 2012-2018 ARM Limited or its affiliates. */ 363893811SGilad Ben-Yossef 463893811SGilad Ben-Yossef /* \file cc_hash.h 563893811SGilad Ben-Yossef * ARM CryptoCell Hash Crypto API 663893811SGilad Ben-Yossef */ 763893811SGilad Ben-Yossef 863893811SGilad Ben-Yossef #ifndef __CC_HASH_H__ 963893811SGilad Ben-Yossef #define __CC_HASH_H__ 1063893811SGilad Ben-Yossef 1163893811SGilad Ben-Yossef #include "cc_buffer_mgr.h" 1263893811SGilad Ben-Yossef 1363893811SGilad Ben-Yossef #define HMAC_IPAD_CONST 0x36363636 1463893811SGilad Ben-Yossef #define HMAC_OPAD_CONST 0x5C5C5C5C 1563893811SGilad Ben-Yossef #if (CC_DEV_SHA_MAX > 256) 1663893811SGilad Ben-Yossef #define HASH_LEN_SIZE 16 1763893811SGilad Ben-Yossef #define CC_MAX_HASH_DIGEST_SIZE SHA512_DIGEST_SIZE 1863893811SGilad Ben-Yossef #define CC_MAX_HASH_BLCK_SIZE SHA512_BLOCK_SIZE 1963893811SGilad Ben-Yossef #else 2063893811SGilad Ben-Yossef #define HASH_LEN_SIZE 8 2163893811SGilad Ben-Yossef #define CC_MAX_HASH_DIGEST_SIZE SHA256_DIGEST_SIZE 2263893811SGilad Ben-Yossef #define CC_MAX_HASH_BLCK_SIZE SHA256_BLOCK_SIZE 2363893811SGilad Ben-Yossef #endif 2463893811SGilad Ben-Yossef 2563893811SGilad Ben-Yossef #define XCBC_MAC_K1_OFFSET 0 2663893811SGilad Ben-Yossef #define XCBC_MAC_K2_OFFSET 16 2763893811SGilad Ben-Yossef #define XCBC_MAC_K3_OFFSET 32 2863893811SGilad Ben-Yossef 2963893811SGilad Ben-Yossef #define CC_EXPORT_MAGIC 0xC2EE1070U 3063893811SGilad Ben-Yossef 3163893811SGilad Ben-Yossef /* this struct was taken from drivers/crypto/nx/nx-aes-xcbc.c and it is used 3263893811SGilad Ben-Yossef * for xcbc/cmac statesize 3363893811SGilad Ben-Yossef */ 3463893811SGilad Ben-Yossef struct aeshash_state { 3563893811SGilad Ben-Yossef u8 state[AES_BLOCK_SIZE]; 3663893811SGilad Ben-Yossef unsigned int count; 3763893811SGilad Ben-Yossef u8 buffer[AES_BLOCK_SIZE]; 3863893811SGilad Ben-Yossef }; 3963893811SGilad Ben-Yossef 4063893811SGilad Ben-Yossef /* ahash state */ 4163893811SGilad Ben-Yossef struct ahash_req_ctx { 4263893811SGilad Ben-Yossef u8 buffers[2][CC_MAX_HASH_BLCK_SIZE] ____cacheline_aligned; 4363893811SGilad Ben-Yossef u8 digest_result_buff[CC_MAX_HASH_DIGEST_SIZE] ____cacheline_aligned; 4463893811SGilad Ben-Yossef u8 digest_buff[CC_MAX_HASH_DIGEST_SIZE] ____cacheline_aligned; 4563893811SGilad Ben-Yossef u8 opad_digest_buff[CC_MAX_HASH_DIGEST_SIZE] ____cacheline_aligned; 4663893811SGilad Ben-Yossef u8 digest_bytes_len[HASH_LEN_SIZE] ____cacheline_aligned; 4763893811SGilad Ben-Yossef struct async_gen_req_ctx gen_ctx ____cacheline_aligned; 4863893811SGilad Ben-Yossef enum cc_req_dma_buf_type data_dma_buf_type; 4963893811SGilad Ben-Yossef dma_addr_t opad_digest_dma_addr; 5063893811SGilad Ben-Yossef dma_addr_t digest_buff_dma_addr; 5163893811SGilad Ben-Yossef dma_addr_t digest_bytes_len_dma_addr; 5263893811SGilad Ben-Yossef dma_addr_t digest_result_dma_addr; 5363893811SGilad Ben-Yossef u32 buf_cnt[2]; 5463893811SGilad Ben-Yossef u32 buff_index; 5563893811SGilad Ben-Yossef u32 xcbc_count; /* count xcbc update operatations */ 5663893811SGilad Ben-Yossef struct scatterlist buff_sg[2]; 5763893811SGilad Ben-Yossef struct scatterlist *curr_sg; 5863893811SGilad Ben-Yossef u32 in_nents; 5963893811SGilad Ben-Yossef u32 mlli_nents; 6063893811SGilad Ben-Yossef struct mlli_params mlli_params; 6163893811SGilad Ben-Yossef }; 6263893811SGilad Ben-Yossef 6363893811SGilad Ben-Yossef static inline u32 *cc_hash_buf_cnt(struct ahash_req_ctx *state) 6463893811SGilad Ben-Yossef { 6563893811SGilad Ben-Yossef return &state->buf_cnt[state->buff_index]; 6663893811SGilad Ben-Yossef } 6763893811SGilad Ben-Yossef 6863893811SGilad Ben-Yossef static inline u8 *cc_hash_buf(struct ahash_req_ctx *state) 6963893811SGilad Ben-Yossef { 7063893811SGilad Ben-Yossef return state->buffers[state->buff_index]; 7163893811SGilad Ben-Yossef } 7263893811SGilad Ben-Yossef 7363893811SGilad Ben-Yossef static inline u32 *cc_next_buf_cnt(struct ahash_req_ctx *state) 7463893811SGilad Ben-Yossef { 7563893811SGilad Ben-Yossef return &state->buf_cnt[state->buff_index ^ 1]; 7663893811SGilad Ben-Yossef } 7763893811SGilad Ben-Yossef 7863893811SGilad Ben-Yossef static inline u8 *cc_next_buf(struct ahash_req_ctx *state) 7963893811SGilad Ben-Yossef { 8063893811SGilad Ben-Yossef return state->buffers[state->buff_index ^ 1]; 8163893811SGilad Ben-Yossef } 8263893811SGilad Ben-Yossef 8363893811SGilad Ben-Yossef int cc_hash_alloc(struct cc_drvdata *drvdata); 8463893811SGilad Ben-Yossef int cc_init_hash_sram(struct cc_drvdata *drvdata); 8563893811SGilad Ben-Yossef int cc_hash_free(struct cc_drvdata *drvdata); 8663893811SGilad Ben-Yossef 8763893811SGilad Ben-Yossef /*! 8863893811SGilad Ben-Yossef * Gets the initial digest length 8963893811SGilad Ben-Yossef * 9063893811SGilad Ben-Yossef * \param drvdata 9163893811SGilad Ben-Yossef * \param mode The Hash mode. Supported modes: 9263893811SGilad Ben-Yossef * MD5/SHA1/SHA224/SHA256/SHA384/SHA512 9363893811SGilad Ben-Yossef * 9463893811SGilad Ben-Yossef * \return u32 returns the address of the initial digest length in SRAM 9563893811SGilad Ben-Yossef */ 9663893811SGilad Ben-Yossef cc_sram_addr_t 9763893811SGilad Ben-Yossef cc_digest_len_addr(void *drvdata, u32 mode); 9863893811SGilad Ben-Yossef 9963893811SGilad Ben-Yossef /*! 10063893811SGilad Ben-Yossef * Gets the address of the initial digest in SRAM 10163893811SGilad Ben-Yossef * according to the given hash mode 10263893811SGilad Ben-Yossef * 10363893811SGilad Ben-Yossef * \param drvdata 10463893811SGilad Ben-Yossef * \param mode The Hash mode. Supported modes: 10563893811SGilad Ben-Yossef * MD5/SHA1/SHA224/SHA256/SHA384/SHA512 10663893811SGilad Ben-Yossef * 10763893811SGilad Ben-Yossef * \return u32 The address of the initial digest in SRAM 10863893811SGilad Ben-Yossef */ 10963893811SGilad Ben-Yossef cc_sram_addr_t cc_larval_digest_addr(void *drvdata, u32 mode); 11063893811SGilad Ben-Yossef 11163893811SGilad Ben-Yossef void cc_hash_global_init(void); 11263893811SGilad Ben-Yossef 11363893811SGilad Ben-Yossef #endif /*__CC_HASH_H__*/ 114