xref: /openbmc/linux/drivers/crypto/ccree/cc_driver.h (revision b8d312aa)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */
3 
4 /* \file cc_driver.h
5  * ARM CryptoCell Linux Crypto Driver
6  */
7 
8 #ifndef __CC_DRIVER_H__
9 #define __CC_DRIVER_H__
10 
11 #ifdef COMP_IN_WQ
12 #include <linux/workqueue.h>
13 #else
14 #include <linux/interrupt.h>
15 #endif
16 #include <linux/dma-mapping.h>
17 #include <crypto/algapi.h>
18 #include <crypto/internal/skcipher.h>
19 #include <crypto/aes.h>
20 #include <crypto/sha.h>
21 #include <crypto/aead.h>
22 #include <crypto/authenc.h>
23 #include <crypto/hash.h>
24 #include <crypto/skcipher.h>
25 #include <linux/version.h>
26 #include <linux/clk.h>
27 #include <linux/platform_device.h>
28 
29 /* Registers definitions from shared/hw/ree_include */
30 #include "cc_host_regs.h"
31 #define CC_DEV_SHA_MAX 512
32 #include "cc_crypto_ctx.h"
33 #include "cc_hw_queue_defs.h"
34 #include "cc_sram_mgr.h"
35 
36 extern bool cc_dump_desc;
37 extern bool cc_dump_bytes;
38 
39 #define DRV_MODULE_VERSION "5.0"
40 
41 enum cc_hw_rev {
42 	CC_HW_REV_630 = 630,
43 	CC_HW_REV_710 = 710,
44 	CC_HW_REV_712 = 712,
45 	CC_HW_REV_713 = 713
46 };
47 
48 enum cc_std_body {
49 	CC_STD_NIST = 0x1,
50 	CC_STD_OSCCA = 0x2,
51 	CC_STD_ALL = 0x3
52 };
53 
54 #define CC_COHERENT_CACHE_PARAMS 0xEEE
55 
56 #define CC_PINS_FULL	0x0
57 #define CC_PINS_SLIM	0x9F
58 
59 /* Maximum DMA mask supported by IP */
60 #define DMA_BIT_MASK_LEN 48
61 
62 #define CC_AXI_IRQ_MASK ((1 << CC_AXIM_CFG_BRESPMASK_BIT_SHIFT) | \
63 			  (1 << CC_AXIM_CFG_RRESPMASK_BIT_SHIFT) | \
64 			  (1 << CC_AXIM_CFG_INFLTMASK_BIT_SHIFT) | \
65 			  (1 << CC_AXIM_CFG_COMPMASK_BIT_SHIFT))
66 
67 #define CC_AXI_ERR_IRQ_MASK BIT(CC_HOST_IRR_AXI_ERR_INT_BIT_SHIFT)
68 
69 #define CC_COMP_IRQ_MASK BIT(CC_HOST_IRR_AXIM_COMP_INT_BIT_SHIFT)
70 
71 #define CC_SECURITY_DISABLED_MASK BIT(CC_SECURITY_DISABLED_VALUE_BIT_SHIFT)
72 
73 #define CC_NVM_IS_IDLE_MASK BIT(CC_NVM_IS_IDLE_VALUE_BIT_SHIFT)
74 
75 #define AXIM_MON_COMP_VALUE GENMASK(CC_AXIM_MON_COMP_VALUE_BIT_SIZE + \
76 				    CC_AXIM_MON_COMP_VALUE_BIT_SHIFT, \
77 				    CC_AXIM_MON_COMP_VALUE_BIT_SHIFT)
78 
79 #define CC_CPP_AES_ABORT_MASK ( \
80 	BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_0_MASK_BIT_SHIFT) | \
81 	BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_1_MASK_BIT_SHIFT) | \
82 	BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_2_MASK_BIT_SHIFT) | \
83 	BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_3_MASK_BIT_SHIFT) | \
84 	BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_4_MASK_BIT_SHIFT) | \
85 	BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_5_MASK_BIT_SHIFT) | \
86 	BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_6_MASK_BIT_SHIFT) | \
87 	BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_7_MASK_BIT_SHIFT))
88 
89 #define CC_CPP_SM4_ABORT_MASK ( \
90 	BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_0_MASK_BIT_SHIFT) | \
91 	BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_1_MASK_BIT_SHIFT) | \
92 	BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_2_MASK_BIT_SHIFT) | \
93 	BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_3_MASK_BIT_SHIFT) | \
94 	BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_4_MASK_BIT_SHIFT) | \
95 	BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_5_MASK_BIT_SHIFT) | \
96 	BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_6_MASK_BIT_SHIFT) | \
97 	BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_7_MASK_BIT_SHIFT))
98 
99 /* Register name mangling macro */
100 #define CC_REG(reg_name) CC_ ## reg_name ## _REG_OFFSET
101 
102 /* TEE FIPS status interrupt */
103 #define CC_GPR0_IRQ_MASK BIT(CC_HOST_IRR_GPR0_BIT_SHIFT)
104 
105 #define CC_CRA_PRIO 400
106 
107 #define MIN_HW_QUEUE_SIZE 50 /* Minimum size required for proper function */
108 
109 #define MAX_REQUEST_QUEUE_SIZE 4096
110 #define MAX_MLLI_BUFF_SIZE 2080
111 
112 /* Definitions for HW descriptors DIN/DOUT fields */
113 #define NS_BIT 1
114 #define AXI_ID 0
115 /* AXI_ID is not actually the AXI ID of the transaction but the value of AXI_ID
116  * field in the HW descriptor. The DMA engine +8 that value.
117  */
118 
119 struct cc_cpp_req {
120 	bool is_cpp;
121 	enum cc_cpp_alg alg;
122 	u8 slot;
123 };
124 
125 #define CC_MAX_IVGEN_DMA_ADDRESSES	3
126 struct cc_crypto_req {
127 	void (*user_cb)(struct device *dev, void *req, int err);
128 	void *user_arg;
129 	dma_addr_t ivgen_dma_addr[CC_MAX_IVGEN_DMA_ADDRESSES];
130 	/* For the first 'ivgen_dma_addr_len' addresses of this array,
131 	 * generated IV would be placed in it by send_request().
132 	 * Same generated IV for all addresses!
133 	 */
134 	/* Amount of 'ivgen_dma_addr' elements to be filled. */
135 	unsigned int ivgen_dma_addr_len;
136 	/* The generated IV size required, 8/16 B allowed. */
137 	unsigned int ivgen_size;
138 	struct completion seq_compl; /* request completion */
139 	struct cc_cpp_req cpp;
140 };
141 
142 /**
143  * struct cc_drvdata - driver private data context
144  * @cc_base:	virt address of the CC registers
145  * @irq:	device IRQ number
146  * @irq_mask:	Interrupt mask shadow (1 for masked interrupts)
147  */
148 struct cc_drvdata {
149 	void __iomem *cc_base;
150 	int irq;
151 	u32 irq_mask;
152 	struct completion hw_queue_avail; /* wait for HW queue availability */
153 	struct platform_device *plat_dev;
154 	cc_sram_addr_t mlli_sram_addr;
155 	void *buff_mgr_handle;
156 	void *cipher_handle;
157 	void *hash_handle;
158 	void *aead_handle;
159 	void *request_mgr_handle;
160 	void *fips_handle;
161 	void *ivgen_handle;
162 	void *sram_mgr_handle;
163 	void *debugfs;
164 	struct clk *clk;
165 	bool coherent;
166 	char *hw_rev_name;
167 	enum cc_hw_rev hw_rev;
168 	u32 axim_mon_offset;
169 	u32 sig_offset;
170 	u32 ver_offset;
171 	int std_bodies;
172 	bool sec_disabled;
173 	u32 comp_mask;
174 };
175 
176 struct cc_crypto_alg {
177 	struct list_head entry;
178 	int cipher_mode;
179 	int flow_mode; /* Note: currently, refers to the cipher mode only. */
180 	int auth_mode;
181 	unsigned int data_unit;
182 	struct cc_drvdata *drvdata;
183 	struct skcipher_alg skcipher_alg;
184 	struct aead_alg aead_alg;
185 };
186 
187 struct cc_alg_template {
188 	char name[CRYPTO_MAX_ALG_NAME];
189 	char driver_name[CRYPTO_MAX_ALG_NAME];
190 	unsigned int blocksize;
191 	union {
192 		struct skcipher_alg skcipher;
193 		struct aead_alg aead;
194 	} template_u;
195 	int cipher_mode;
196 	int flow_mode; /* Note: currently, refers to the cipher mode only. */
197 	int auth_mode;
198 	u32 min_hw_rev;
199 	enum cc_std_body std_body;
200 	bool sec_func;
201 	unsigned int data_unit;
202 	struct cc_drvdata *drvdata;
203 };
204 
205 struct async_gen_req_ctx {
206 	dma_addr_t iv_dma_addr;
207 	u8 *iv;
208 	enum drv_crypto_direction op_type;
209 };
210 
211 static inline struct device *drvdata_to_dev(struct cc_drvdata *drvdata)
212 {
213 	return &drvdata->plat_dev->dev;
214 }
215 
216 void __dump_byte_array(const char *name, const u8 *buf, size_t len);
217 static inline void dump_byte_array(const char *name, const u8 *the_array,
218 				   size_t size)
219 {
220 	if (cc_dump_bytes)
221 		__dump_byte_array(name, the_array, size);
222 }
223 
224 bool cc_wait_for_reset_completion(struct cc_drvdata *drvdata);
225 int init_cc_regs(struct cc_drvdata *drvdata, bool is_probe);
226 void fini_cc_regs(struct cc_drvdata *drvdata);
227 int cc_clk_on(struct cc_drvdata *drvdata);
228 void cc_clk_off(struct cc_drvdata *drvdata);
229 unsigned int cc_get_default_hash_len(struct cc_drvdata *drvdata);
230 
231 static inline void cc_iowrite(struct cc_drvdata *drvdata, u32 reg, u32 val)
232 {
233 	iowrite32(val, (drvdata->cc_base + reg));
234 }
235 
236 static inline u32 cc_ioread(struct cc_drvdata *drvdata, u32 reg)
237 {
238 	return ioread32(drvdata->cc_base + reg);
239 }
240 
241 static inline gfp_t cc_gfp_flags(struct crypto_async_request *req)
242 {
243 	return (req->flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
244 			GFP_KERNEL : GFP_ATOMIC;
245 }
246 
247 static inline void set_queue_last_ind(struct cc_drvdata *drvdata,
248 				      struct cc_hw_desc *pdesc)
249 {
250 	if (drvdata->hw_rev >= CC_HW_REV_712)
251 		set_queue_last_ind_bit(pdesc);
252 }
253 
254 #endif /*__CC_DRIVER_H__*/
255