1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (C) 2012-2018 ARM Limited or its affiliates. */ 3 4 /* \file cc_driver.h 5 * ARM CryptoCell Linux Crypto Driver 6 */ 7 8 #ifndef __CC_DRIVER_H__ 9 #define __CC_DRIVER_H__ 10 11 #ifdef COMP_IN_WQ 12 #include <linux/workqueue.h> 13 #else 14 #include <linux/interrupt.h> 15 #endif 16 #include <linux/dma-mapping.h> 17 #include <crypto/algapi.h> 18 #include <crypto/internal/skcipher.h> 19 #include <crypto/aes.h> 20 #include <crypto/sha.h> 21 #include <crypto/aead.h> 22 #include <crypto/authenc.h> 23 #include <crypto/hash.h> 24 #include <crypto/skcipher.h> 25 #include <linux/version.h> 26 #include <linux/clk.h> 27 #include <linux/platform_device.h> 28 29 /* Registers definitions from shared/hw/ree_include */ 30 #include "cc_host_regs.h" 31 #define CC_DEV_SHA_MAX 512 32 #include "cc_crypto_ctx.h" 33 #include "cc_hw_queue_defs.h" 34 #include "cc_sram_mgr.h" 35 36 extern bool cc_dump_desc; 37 extern bool cc_dump_bytes; 38 39 #define DRV_MODULE_VERSION "5.0" 40 41 enum cc_hw_rev { 42 CC_HW_REV_630 = 630, 43 CC_HW_REV_710 = 710, 44 CC_HW_REV_712 = 712, 45 CC_HW_REV_713 = 713 46 }; 47 48 enum cc_std_body { 49 CC_STD_NIST = 0x1, 50 CC_STD_OSCCA = 0x2, 51 CC_STD_ALL = 0x3 52 }; 53 54 #define CC_COHERENT_CACHE_PARAMS 0xEEE 55 56 /* Maximum DMA mask supported by IP */ 57 #define DMA_BIT_MASK_LEN 48 58 59 #define CC_AXI_IRQ_MASK ((1 << CC_AXIM_CFG_BRESPMASK_BIT_SHIFT) | \ 60 (1 << CC_AXIM_CFG_RRESPMASK_BIT_SHIFT) | \ 61 (1 << CC_AXIM_CFG_INFLTMASK_BIT_SHIFT) | \ 62 (1 << CC_AXIM_CFG_COMPMASK_BIT_SHIFT)) 63 64 #define CC_AXI_ERR_IRQ_MASK BIT(CC_HOST_IRR_AXI_ERR_INT_BIT_SHIFT) 65 66 #define CC_COMP_IRQ_MASK BIT(CC_HOST_IRR_AXIM_COMP_INT_BIT_SHIFT) 67 68 #define AXIM_MON_COMP_VALUE GENMASK(CC_AXIM_MON_COMP_VALUE_BIT_SIZE + \ 69 CC_AXIM_MON_COMP_VALUE_BIT_SHIFT, \ 70 CC_AXIM_MON_COMP_VALUE_BIT_SHIFT) 71 72 /* Register name mangling macro */ 73 #define CC_REG(reg_name) CC_ ## reg_name ## _REG_OFFSET 74 75 /* TEE FIPS status interrupt */ 76 #define CC_GPR0_IRQ_MASK BIT(CC_HOST_IRR_GPR0_BIT_SHIFT) 77 78 #define CC_CRA_PRIO 400 79 80 #define MIN_HW_QUEUE_SIZE 50 /* Minimum size required for proper function */ 81 82 #define MAX_REQUEST_QUEUE_SIZE 4096 83 #define MAX_MLLI_BUFF_SIZE 2080 84 #define MAX_ICV_NENTS_SUPPORTED 2 85 86 /* Definitions for HW descriptors DIN/DOUT fields */ 87 #define NS_BIT 1 88 #define AXI_ID 0 89 /* AXI_ID is not actually the AXI ID of the transaction but the value of AXI_ID 90 * field in the HW descriptor. The DMA engine +8 that value. 91 */ 92 93 #define CC_MAX_IVGEN_DMA_ADDRESSES 3 94 struct cc_crypto_req { 95 void (*user_cb)(struct device *dev, void *req, int err); 96 void *user_arg; 97 dma_addr_t ivgen_dma_addr[CC_MAX_IVGEN_DMA_ADDRESSES]; 98 /* For the first 'ivgen_dma_addr_len' addresses of this array, 99 * generated IV would be placed in it by send_request(). 100 * Same generated IV for all addresses! 101 */ 102 /* Amount of 'ivgen_dma_addr' elements to be filled. */ 103 unsigned int ivgen_dma_addr_len; 104 /* The generated IV size required, 8/16 B allowed. */ 105 unsigned int ivgen_size; 106 struct completion seq_compl; /* request completion */ 107 }; 108 109 /** 110 * struct cc_drvdata - driver private data context 111 * @cc_base: virt address of the CC registers 112 * @irq: device IRQ number 113 * @irq_mask: Interrupt mask shadow (1 for masked interrupts) 114 */ 115 struct cc_drvdata { 116 void __iomem *cc_base; 117 int irq; 118 u32 irq_mask; 119 struct completion hw_queue_avail; /* wait for HW queue availability */ 120 struct platform_device *plat_dev; 121 cc_sram_addr_t mlli_sram_addr; 122 void *buff_mgr_handle; 123 void *cipher_handle; 124 void *hash_handle; 125 void *aead_handle; 126 void *request_mgr_handle; 127 void *fips_handle; 128 void *ivgen_handle; 129 void *sram_mgr_handle; 130 void *debugfs; 131 struct clk *clk; 132 bool coherent; 133 char *hw_rev_name; 134 enum cc_hw_rev hw_rev; 135 u32 axim_mon_offset; 136 u32 sig_offset; 137 u32 ver_offset; 138 int std_bodies; 139 }; 140 141 struct cc_crypto_alg { 142 struct list_head entry; 143 int cipher_mode; 144 int flow_mode; /* Note: currently, refers to the cipher mode only. */ 145 int auth_mode; 146 unsigned int data_unit; 147 struct cc_drvdata *drvdata; 148 struct skcipher_alg skcipher_alg; 149 struct aead_alg aead_alg; 150 }; 151 152 struct cc_alg_template { 153 char name[CRYPTO_MAX_ALG_NAME]; 154 char driver_name[CRYPTO_MAX_ALG_NAME]; 155 unsigned int blocksize; 156 union { 157 struct skcipher_alg skcipher; 158 struct aead_alg aead; 159 } template_u; 160 int cipher_mode; 161 int flow_mode; /* Note: currently, refers to the cipher mode only. */ 162 int auth_mode; 163 u32 min_hw_rev; 164 enum cc_std_body std_body; 165 unsigned int data_unit; 166 struct cc_drvdata *drvdata; 167 }; 168 169 struct async_gen_req_ctx { 170 dma_addr_t iv_dma_addr; 171 enum drv_crypto_direction op_type; 172 }; 173 174 static inline struct device *drvdata_to_dev(struct cc_drvdata *drvdata) 175 { 176 return &drvdata->plat_dev->dev; 177 } 178 179 void __dump_byte_array(const char *name, const u8 *buf, size_t len); 180 static inline void dump_byte_array(const char *name, const u8 *the_array, 181 size_t size) 182 { 183 if (cc_dump_bytes) 184 __dump_byte_array(name, the_array, size); 185 } 186 187 int init_cc_regs(struct cc_drvdata *drvdata, bool is_probe); 188 void fini_cc_regs(struct cc_drvdata *drvdata); 189 int cc_clk_on(struct cc_drvdata *drvdata); 190 void cc_clk_off(struct cc_drvdata *drvdata); 191 unsigned int cc_get_default_hash_len(struct cc_drvdata *drvdata); 192 193 static inline void cc_iowrite(struct cc_drvdata *drvdata, u32 reg, u32 val) 194 { 195 iowrite32(val, (drvdata->cc_base + reg)); 196 } 197 198 static inline u32 cc_ioread(struct cc_drvdata *drvdata, u32 reg) 199 { 200 return ioread32(drvdata->cc_base + reg); 201 } 202 203 static inline gfp_t cc_gfp_flags(struct crypto_async_request *req) 204 { 205 return (req->flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? 206 GFP_KERNEL : GFP_ATOMIC; 207 } 208 209 static inline void set_queue_last_ind(struct cc_drvdata *drvdata, 210 struct cc_hw_desc *pdesc) 211 { 212 if (drvdata->hw_rev >= CC_HW_REV_712) 213 set_queue_last_ind_bit(pdesc); 214 } 215 216 #endif /*__CC_DRIVER_H__*/ 217