1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */ 3 4 /* \file cc_driver.h 5 * ARM CryptoCell Linux Crypto Driver 6 */ 7 8 #ifndef __CC_DRIVER_H__ 9 #define __CC_DRIVER_H__ 10 11 #ifdef COMP_IN_WQ 12 #include <linux/workqueue.h> 13 #else 14 #include <linux/interrupt.h> 15 #endif 16 #include <linux/dma-mapping.h> 17 #include <crypto/algapi.h> 18 #include <crypto/internal/skcipher.h> 19 #include <crypto/aes.h> 20 #include <crypto/sha1.h> 21 #include <crypto/sha2.h> 22 #include <crypto/aead.h> 23 #include <crypto/authenc.h> 24 #include <crypto/hash.h> 25 #include <crypto/skcipher.h> 26 #include <linux/version.h> 27 #include <linux/clk.h> 28 #include <linux/platform_device.h> 29 30 #include "cc_host_regs.h" 31 #include "cc_crypto_ctx.h" 32 #include "cc_hw_queue_defs.h" 33 #include "cc_sram_mgr.h" 34 35 extern bool cc_dump_desc; 36 extern bool cc_dump_bytes; 37 38 #define DRV_MODULE_VERSION "5.0" 39 40 enum cc_hw_rev { 41 CC_HW_REV_630 = 630, 42 CC_HW_REV_710 = 710, 43 CC_HW_REV_712 = 712, 44 CC_HW_REV_713 = 713 45 }; 46 47 enum cc_std_body { 48 CC_STD_NIST = 0x1, 49 CC_STD_OSCCA = 0x2, 50 CC_STD_ALL = 0x3 51 }; 52 53 #define CC_PINS_FULL 0x0 54 #define CC_PINS_SLIM 0x9F 55 56 /* Maximum DMA mask supported by IP */ 57 #define DMA_BIT_MASK_LEN 48 58 59 #define CC_AXI_IRQ_MASK ((1 << CC_AXIM_CFG_BRESPMASK_BIT_SHIFT) | \ 60 (1 << CC_AXIM_CFG_RRESPMASK_BIT_SHIFT) | \ 61 (1 << CC_AXIM_CFG_INFLTMASK_BIT_SHIFT) | \ 62 (1 << CC_AXIM_CFG_COMPMASK_BIT_SHIFT)) 63 64 #define CC_AXI_ERR_IRQ_MASK BIT(CC_HOST_IRR_AXI_ERR_INT_BIT_SHIFT) 65 66 #define CC_COMP_IRQ_MASK BIT(CC_HOST_IRR_AXIM_COMP_INT_BIT_SHIFT) 67 68 #define CC_SECURITY_DISABLED_MASK BIT(CC_SECURITY_DISABLED_VALUE_BIT_SHIFT) 69 70 #define CC_NVM_IS_IDLE_MASK BIT(CC_NVM_IS_IDLE_VALUE_BIT_SHIFT) 71 72 #define AXIM_MON_COMP_VALUE CC_GENMASK(CC_AXIM_MON_COMP_VALUE) 73 74 #define CC_CPP_AES_ABORT_MASK ( \ 75 BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_0_MASK_BIT_SHIFT) | \ 76 BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_1_MASK_BIT_SHIFT) | \ 77 BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_2_MASK_BIT_SHIFT) | \ 78 BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_3_MASK_BIT_SHIFT) | \ 79 BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_4_MASK_BIT_SHIFT) | \ 80 BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_5_MASK_BIT_SHIFT) | \ 81 BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_6_MASK_BIT_SHIFT) | \ 82 BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_7_MASK_BIT_SHIFT)) 83 84 #define CC_CPP_SM4_ABORT_MASK ( \ 85 BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_0_MASK_BIT_SHIFT) | \ 86 BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_1_MASK_BIT_SHIFT) | \ 87 BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_2_MASK_BIT_SHIFT) | \ 88 BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_3_MASK_BIT_SHIFT) | \ 89 BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_4_MASK_BIT_SHIFT) | \ 90 BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_5_MASK_BIT_SHIFT) | \ 91 BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_6_MASK_BIT_SHIFT) | \ 92 BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_7_MASK_BIT_SHIFT)) 93 94 /* Register name mangling macro */ 95 #define CC_REG(reg_name) CC_ ## reg_name ## _REG_OFFSET 96 97 /* TEE FIPS status interrupt */ 98 #define CC_GPR0_IRQ_MASK BIT(CC_HOST_IRR_GPR0_BIT_SHIFT) 99 100 #define CC_CRA_PRIO 400 101 102 #define MIN_HW_QUEUE_SIZE 50 /* Minimum size required for proper function */ 103 104 #define MAX_REQUEST_QUEUE_SIZE 4096 105 #define MAX_MLLI_BUFF_SIZE 2080 106 107 /* Definitions for HW descriptors DIN/DOUT fields */ 108 #define NS_BIT 1 109 #define AXI_ID 0 110 /* AXI_ID is not actually the AXI ID of the transaction but the value of AXI_ID 111 * field in the HW descriptor. The DMA engine +8 that value. 112 */ 113 114 struct cc_cpp_req { 115 bool is_cpp; 116 enum cc_cpp_alg alg; 117 u8 slot; 118 }; 119 120 #define CC_MAX_IVGEN_DMA_ADDRESSES 3 121 struct cc_crypto_req { 122 void (*user_cb)(struct device *dev, void *req, int err); 123 void *user_arg; 124 struct completion seq_compl; /* request completion */ 125 struct cc_cpp_req cpp; 126 }; 127 128 /** 129 * struct cc_drvdata - driver private data context 130 * @cc_base: virt address of the CC registers 131 * @irq: bitmap indicating source of last interrupt 132 */ 133 struct cc_drvdata { 134 void __iomem *cc_base; 135 int irq; 136 struct completion hw_queue_avail; /* wait for HW queue availability */ 137 struct platform_device *plat_dev; 138 u32 mlli_sram_addr; 139 struct dma_pool *mlli_buffs_pool; 140 struct list_head alg_list; 141 void *hash_handle; 142 void *aead_handle; 143 void *request_mgr_handle; 144 void *fips_handle; 145 u32 sram_free_offset; /* offset to non-allocated area in SRAM */ 146 struct dentry *dir; /* for debugfs */ 147 struct clk *clk; 148 bool coherent; 149 char *hw_rev_name; 150 enum cc_hw_rev hw_rev; 151 u32 axim_mon_offset; 152 u32 sig_offset; 153 u32 ver_offset; 154 int std_bodies; 155 bool sec_disabled; 156 u32 comp_mask; 157 u32 cache_params; 158 u32 ace_const; 159 }; 160 161 struct cc_crypto_alg { 162 struct list_head entry; 163 int cipher_mode; 164 int flow_mode; /* Note: currently, refers to the cipher mode only. */ 165 int auth_mode; 166 struct cc_drvdata *drvdata; 167 struct skcipher_alg skcipher_alg; 168 struct aead_alg aead_alg; 169 }; 170 171 struct cc_alg_template { 172 char name[CRYPTO_MAX_ALG_NAME]; 173 char driver_name[CRYPTO_MAX_ALG_NAME]; 174 unsigned int blocksize; 175 union { 176 struct skcipher_alg skcipher; 177 struct aead_alg aead; 178 } template_u; 179 int cipher_mode; 180 int flow_mode; /* Note: currently, refers to the cipher mode only. */ 181 int auth_mode; 182 u32 min_hw_rev; 183 enum cc_std_body std_body; 184 bool sec_func; 185 unsigned int data_unit; 186 struct cc_drvdata *drvdata; 187 }; 188 189 struct async_gen_req_ctx { 190 dma_addr_t iv_dma_addr; 191 u8 *iv; 192 enum drv_crypto_direction op_type; 193 }; 194 195 static inline struct device *drvdata_to_dev(struct cc_drvdata *drvdata) 196 { 197 return &drvdata->plat_dev->dev; 198 } 199 200 void __dump_byte_array(const char *name, const u8 *buf, size_t len); 201 static inline void dump_byte_array(const char *name, const u8 *the_array, 202 size_t size) 203 { 204 if (cc_dump_bytes) 205 __dump_byte_array(name, the_array, size); 206 } 207 208 bool cc_wait_for_reset_completion(struct cc_drvdata *drvdata); 209 int init_cc_regs(struct cc_drvdata *drvdata); 210 void fini_cc_regs(struct cc_drvdata *drvdata); 211 unsigned int cc_get_default_hash_len(struct cc_drvdata *drvdata); 212 213 static inline void cc_iowrite(struct cc_drvdata *drvdata, u32 reg, u32 val) 214 { 215 iowrite32(val, (drvdata->cc_base + reg)); 216 } 217 218 static inline u32 cc_ioread(struct cc_drvdata *drvdata, u32 reg) 219 { 220 return ioread32(drvdata->cc_base + reg); 221 } 222 223 static inline gfp_t cc_gfp_flags(struct crypto_async_request *req) 224 { 225 return (req->flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? 226 GFP_KERNEL : GFP_ATOMIC; 227 } 228 229 static inline void set_queue_last_ind(struct cc_drvdata *drvdata, 230 struct cc_hw_desc *pdesc) 231 { 232 if (drvdata->hw_rev >= CC_HW_REV_712) 233 set_queue_last_ind_bit(pdesc); 234 } 235 236 #endif /*__CC_DRIVER_H__*/ 237