1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (C) 2012-2019 ARM Limited or its affiliates. */ 3 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 7 #include <linux/crypto.h> 8 #include <linux/moduleparam.h> 9 #include <linux/types.h> 10 #include <linux/interrupt.h> 11 #include <linux/platform_device.h> 12 #include <linux/slab.h> 13 #include <linux/spinlock.h> 14 #include <linux/of.h> 15 #include <linux/clk.h> 16 #include <linux/of_address.h> 17 #include <linux/of_device.h> 18 #include <linux/pm_runtime.h> 19 20 #include "cc_driver.h" 21 #include "cc_request_mgr.h" 22 #include "cc_buffer_mgr.h" 23 #include "cc_debugfs.h" 24 #include "cc_cipher.h" 25 #include "cc_aead.h" 26 #include "cc_hash.h" 27 #include "cc_sram_mgr.h" 28 #include "cc_pm.h" 29 #include "cc_fips.h" 30 31 bool cc_dump_desc; 32 module_param_named(dump_desc, cc_dump_desc, bool, 0600); 33 MODULE_PARM_DESC(cc_dump_desc, "Dump descriptors to kernel log as debugging aid"); 34 bool cc_dump_bytes; 35 module_param_named(dump_bytes, cc_dump_bytes, bool, 0600); 36 MODULE_PARM_DESC(cc_dump_bytes, "Dump buffers to kernel log as debugging aid"); 37 38 static bool cc_sec_disable; 39 module_param_named(sec_disable, cc_sec_disable, bool, 0600); 40 MODULE_PARM_DESC(cc_sec_disable, "Disable security functions"); 41 42 struct cc_hw_data { 43 char *name; 44 enum cc_hw_rev rev; 45 u32 sig; 46 u32 cidr_0123; 47 u32 pidr_0124; 48 int std_bodies; 49 }; 50 51 #define CC_NUM_IDRS 4 52 #define CC_HW_RESET_LOOP_COUNT 10 53 54 /* Note: PIDR3 holds CMOD/Rev so ignored for HW identification purposes */ 55 static const u32 pidr_0124_offsets[CC_NUM_IDRS] = { 56 CC_REG(PERIPHERAL_ID_0), CC_REG(PERIPHERAL_ID_1), 57 CC_REG(PERIPHERAL_ID_2), CC_REG(PERIPHERAL_ID_4) 58 }; 59 60 static const u32 cidr_0123_offsets[CC_NUM_IDRS] = { 61 CC_REG(COMPONENT_ID_0), CC_REG(COMPONENT_ID_1), 62 CC_REG(COMPONENT_ID_2), CC_REG(COMPONENT_ID_3) 63 }; 64 65 /* Hardware revisions defs. */ 66 67 /* The 703 is a OSCCA only variant of the 713 */ 68 static const struct cc_hw_data cc703_hw = { 69 .name = "703", .rev = CC_HW_REV_713, .cidr_0123 = 0xB105F00DU, 70 .pidr_0124 = 0x040BB0D0U, .std_bodies = CC_STD_OSCCA 71 }; 72 73 static const struct cc_hw_data cc713_hw = { 74 .name = "713", .rev = CC_HW_REV_713, .cidr_0123 = 0xB105F00DU, 75 .pidr_0124 = 0x040BB0D0U, .std_bodies = CC_STD_ALL 76 }; 77 78 static const struct cc_hw_data cc712_hw = { 79 .name = "712", .rev = CC_HW_REV_712, .sig = 0xDCC71200U, 80 .std_bodies = CC_STD_ALL 81 }; 82 83 static const struct cc_hw_data cc710_hw = { 84 .name = "710", .rev = CC_HW_REV_710, .sig = 0xDCC63200U, 85 .std_bodies = CC_STD_ALL 86 }; 87 88 static const struct cc_hw_data cc630p_hw = { 89 .name = "630P", .rev = CC_HW_REV_630, .sig = 0xDCC63000U, 90 .std_bodies = CC_STD_ALL 91 }; 92 93 static const struct of_device_id arm_ccree_dev_of_match[] = { 94 { .compatible = "arm,cryptocell-703-ree", .data = &cc703_hw }, 95 { .compatible = "arm,cryptocell-713-ree", .data = &cc713_hw }, 96 { .compatible = "arm,cryptocell-712-ree", .data = &cc712_hw }, 97 { .compatible = "arm,cryptocell-710-ree", .data = &cc710_hw }, 98 { .compatible = "arm,cryptocell-630p-ree", .data = &cc630p_hw }, 99 {} 100 }; 101 MODULE_DEVICE_TABLE(of, arm_ccree_dev_of_match); 102 103 static void init_cc_cache_params(struct cc_drvdata *drvdata) 104 { 105 struct device *dev = drvdata_to_dev(drvdata); 106 u32 cache_params, ace_const, val; 107 u64 mask; 108 109 /* compute CC_AXIM_CACHE_PARAMS */ 110 cache_params = cc_ioread(drvdata, CC_REG(AXIM_CACHE_PARAMS)); 111 dev_dbg(dev, "Cache params previous: 0x%08X\n", cache_params); 112 113 /* non cached or write-back, write allocate */ 114 val = drvdata->coherent ? 0xb : 0x2; 115 116 mask = CC_GENMASK(CC_AXIM_CACHE_PARAMS_AWCACHE); 117 cache_params &= ~mask; 118 cache_params |= FIELD_PREP(mask, val); 119 120 mask = CC_GENMASK(CC_AXIM_CACHE_PARAMS_AWCACHE_LAST); 121 cache_params &= ~mask; 122 cache_params |= FIELD_PREP(mask, val); 123 124 mask = CC_GENMASK(CC_AXIM_CACHE_PARAMS_ARCACHE); 125 cache_params &= ~mask; 126 cache_params |= FIELD_PREP(mask, val); 127 128 drvdata->cache_params = cache_params; 129 130 dev_dbg(dev, "Cache params current: 0x%08X\n", cache_params); 131 132 if (drvdata->hw_rev <= CC_HW_REV_710) 133 return; 134 135 /* compute CC_AXIM_ACE_CONST */ 136 ace_const = cc_ioread(drvdata, CC_REG(AXIM_ACE_CONST)); 137 dev_dbg(dev, "ACE-const previous: 0x%08X\n", ace_const); 138 139 /* system or outer-sharable */ 140 val = drvdata->coherent ? 0x2 : 0x3; 141 142 mask = CC_GENMASK(CC_AXIM_ACE_CONST_ARDOMAIN); 143 ace_const &= ~mask; 144 ace_const |= FIELD_PREP(mask, val); 145 146 mask = CC_GENMASK(CC_AXIM_ACE_CONST_AWDOMAIN); 147 ace_const &= ~mask; 148 ace_const |= FIELD_PREP(mask, val); 149 150 dev_dbg(dev, "ACE-const current: 0x%08X\n", ace_const); 151 152 drvdata->ace_const = ace_const; 153 } 154 155 static u32 cc_read_idr(struct cc_drvdata *drvdata, const u32 *idr_offsets) 156 { 157 int i; 158 union { 159 u8 regs[CC_NUM_IDRS]; 160 __le32 val; 161 } idr; 162 163 for (i = 0; i < CC_NUM_IDRS; ++i) 164 idr.regs[i] = cc_ioread(drvdata, idr_offsets[i]); 165 166 return le32_to_cpu(idr.val); 167 } 168 169 void __dump_byte_array(const char *name, const u8 *buf, size_t len) 170 { 171 char prefix[64]; 172 173 if (!buf) 174 return; 175 176 snprintf(prefix, sizeof(prefix), "%s[%zu]: ", name, len); 177 178 print_hex_dump(KERN_DEBUG, prefix, DUMP_PREFIX_ADDRESS, 16, 1, buf, 179 len, false); 180 } 181 182 static irqreturn_t cc_isr(int irq, void *dev_id) 183 { 184 struct cc_drvdata *drvdata = (struct cc_drvdata *)dev_id; 185 struct device *dev = drvdata_to_dev(drvdata); 186 u32 irr; 187 u32 imr; 188 189 /* STAT_OP_TYPE_GENERIC STAT_PHASE_0: Interrupt */ 190 /* if driver suspended return, probably shared interrupt */ 191 if (pm_runtime_suspended(dev)) 192 return IRQ_NONE; 193 194 /* read the interrupt status */ 195 irr = cc_ioread(drvdata, CC_REG(HOST_IRR)); 196 dev_dbg(dev, "Got IRR=0x%08X\n", irr); 197 198 if (irr == 0) /* Probably shared interrupt line */ 199 return IRQ_NONE; 200 201 imr = cc_ioread(drvdata, CC_REG(HOST_IMR)); 202 203 /* clear interrupt - must be before processing events */ 204 cc_iowrite(drvdata, CC_REG(HOST_ICR), irr); 205 206 drvdata->irq = irr; 207 /* Completion interrupt - most probable */ 208 if (irr & drvdata->comp_mask) { 209 /* Mask all completion interrupts - will be unmasked in 210 * deferred service handler 211 */ 212 cc_iowrite(drvdata, CC_REG(HOST_IMR), imr | drvdata->comp_mask); 213 irr &= ~drvdata->comp_mask; 214 complete_request(drvdata); 215 } 216 #ifdef CONFIG_CRYPTO_FIPS 217 /* TEE FIPS interrupt */ 218 if (irr & CC_GPR0_IRQ_MASK) { 219 /* Mask interrupt - will be unmasked in Deferred service 220 * handler 221 */ 222 cc_iowrite(drvdata, CC_REG(HOST_IMR), imr | CC_GPR0_IRQ_MASK); 223 irr &= ~CC_GPR0_IRQ_MASK; 224 fips_handler(drvdata); 225 } 226 #endif 227 /* AXI error interrupt */ 228 if (irr & CC_AXI_ERR_IRQ_MASK) { 229 u32 axi_err; 230 231 /* Read the AXI error ID */ 232 axi_err = cc_ioread(drvdata, CC_REG(AXIM_MON_ERR)); 233 dev_dbg(dev, "AXI completion error: axim_mon_err=0x%08X\n", 234 axi_err); 235 236 irr &= ~CC_AXI_ERR_IRQ_MASK; 237 } 238 239 if (irr) { 240 dev_dbg_ratelimited(dev, "IRR includes unknown cause bits (0x%08X)\n", 241 irr); 242 /* Just warning */ 243 } 244 245 return IRQ_HANDLED; 246 } 247 248 bool cc_wait_for_reset_completion(struct cc_drvdata *drvdata) 249 { 250 unsigned int val; 251 unsigned int i; 252 253 /* 712/710/63 has no reset completion indication, always return true */ 254 if (drvdata->hw_rev <= CC_HW_REV_712) 255 return true; 256 257 for (i = 0; i < CC_HW_RESET_LOOP_COUNT; i++) { 258 /* in cc7x3 NVM_IS_IDLE indicates that CC reset is 259 * completed and device is fully functional 260 */ 261 val = cc_ioread(drvdata, CC_REG(NVM_IS_IDLE)); 262 if (val & CC_NVM_IS_IDLE_MASK) { 263 /* hw indicate reset completed */ 264 return true; 265 } 266 /* allow scheduling other process on the processor */ 267 schedule(); 268 } 269 /* reset not completed */ 270 return false; 271 } 272 273 int init_cc_regs(struct cc_drvdata *drvdata) 274 { 275 unsigned int val; 276 struct device *dev = drvdata_to_dev(drvdata); 277 278 /* Unmask all AXI interrupt sources AXI_CFG1 register */ 279 /* AXI interrupt config are obsoleted startign at cc7x3 */ 280 if (drvdata->hw_rev <= CC_HW_REV_712) { 281 val = cc_ioread(drvdata, CC_REG(AXIM_CFG)); 282 cc_iowrite(drvdata, CC_REG(AXIM_CFG), val & ~CC_AXI_IRQ_MASK); 283 dev_dbg(dev, "AXIM_CFG=0x%08X\n", 284 cc_ioread(drvdata, CC_REG(AXIM_CFG))); 285 } 286 287 /* Clear all pending interrupts */ 288 val = cc_ioread(drvdata, CC_REG(HOST_IRR)); 289 dev_dbg(dev, "IRR=0x%08X\n", val); 290 cc_iowrite(drvdata, CC_REG(HOST_ICR), val); 291 292 /* Unmask relevant interrupt cause */ 293 val = drvdata->comp_mask | CC_AXI_ERR_IRQ_MASK; 294 295 if (drvdata->hw_rev >= CC_HW_REV_712) 296 val |= CC_GPR0_IRQ_MASK; 297 298 cc_iowrite(drvdata, CC_REG(HOST_IMR), ~val); 299 300 cc_iowrite(drvdata, CC_REG(AXIM_CACHE_PARAMS), drvdata->cache_params); 301 if (drvdata->hw_rev >= CC_HW_REV_712) 302 cc_iowrite(drvdata, CC_REG(AXIM_ACE_CONST), drvdata->ace_const); 303 304 return 0; 305 } 306 307 static int init_cc_resources(struct platform_device *plat_dev) 308 { 309 struct resource *req_mem_cc_regs = NULL; 310 struct cc_drvdata *new_drvdata; 311 struct device *dev = &plat_dev->dev; 312 struct device_node *np = dev->of_node; 313 u32 val, hw_rev_pidr, sig_cidr; 314 u64 dma_mask; 315 const struct cc_hw_data *hw_rev; 316 struct clk *clk; 317 int irq; 318 int rc = 0; 319 320 new_drvdata = devm_kzalloc(dev, sizeof(*new_drvdata), GFP_KERNEL); 321 if (!new_drvdata) 322 return -ENOMEM; 323 324 hw_rev = of_device_get_match_data(dev); 325 new_drvdata->hw_rev_name = hw_rev->name; 326 new_drvdata->hw_rev = hw_rev->rev; 327 new_drvdata->std_bodies = hw_rev->std_bodies; 328 329 if (hw_rev->rev >= CC_HW_REV_712) { 330 new_drvdata->axim_mon_offset = CC_REG(AXIM_MON_COMP); 331 new_drvdata->sig_offset = CC_REG(HOST_SIGNATURE_712); 332 new_drvdata->ver_offset = CC_REG(HOST_VERSION_712); 333 } else { 334 new_drvdata->axim_mon_offset = CC_REG(AXIM_MON_COMP8); 335 new_drvdata->sig_offset = CC_REG(HOST_SIGNATURE_630); 336 new_drvdata->ver_offset = CC_REG(HOST_VERSION_630); 337 } 338 339 new_drvdata->comp_mask = CC_COMP_IRQ_MASK; 340 341 platform_set_drvdata(plat_dev, new_drvdata); 342 new_drvdata->plat_dev = plat_dev; 343 344 clk = devm_clk_get_optional(dev, NULL); 345 if (IS_ERR(clk)) 346 return dev_err_probe(dev, PTR_ERR(clk), "Error getting clock\n"); 347 new_drvdata->clk = clk; 348 349 new_drvdata->coherent = of_dma_is_coherent(np); 350 351 /* Get device resources */ 352 /* First CC registers space */ 353 req_mem_cc_regs = platform_get_resource(plat_dev, IORESOURCE_MEM, 0); 354 /* Map registers space */ 355 new_drvdata->cc_base = devm_ioremap_resource(dev, req_mem_cc_regs); 356 if (IS_ERR(new_drvdata->cc_base)) 357 return PTR_ERR(new_drvdata->cc_base); 358 359 dev_dbg(dev, "Got MEM resource (%s): %pR\n", req_mem_cc_regs->name, 360 req_mem_cc_regs); 361 dev_dbg(dev, "CC registers mapped from %pa to 0x%p\n", 362 &req_mem_cc_regs->start, new_drvdata->cc_base); 363 364 /* Then IRQ */ 365 irq = platform_get_irq(plat_dev, 0); 366 if (irq < 0) 367 return irq; 368 369 init_completion(&new_drvdata->hw_queue_avail); 370 371 if (!dev->dma_mask) 372 dev->dma_mask = &dev->coherent_dma_mask; 373 374 dma_mask = DMA_BIT_MASK(DMA_BIT_MASK_LEN); 375 rc = dma_set_coherent_mask(dev, dma_mask); 376 if (rc) { 377 dev_err(dev, "Failed in dma_set_coherent_mask, mask=%llx\n", 378 dma_mask); 379 return rc; 380 } 381 382 rc = clk_prepare_enable(new_drvdata->clk); 383 if (rc) { 384 dev_err(dev, "Failed to enable clock"); 385 return rc; 386 } 387 388 new_drvdata->sec_disabled = cc_sec_disable; 389 390 pm_runtime_set_autosuspend_delay(dev, CC_SUSPEND_TIMEOUT); 391 pm_runtime_use_autosuspend(dev); 392 pm_runtime_set_active(dev); 393 pm_runtime_enable(dev); 394 rc = pm_runtime_get_sync(dev); 395 if (rc < 0) { 396 dev_err(dev, "pm_runtime_get_sync() failed: %d\n", rc); 397 goto post_pm_err; 398 } 399 400 /* Wait for Cryptocell reset completion */ 401 if (!cc_wait_for_reset_completion(new_drvdata)) { 402 dev_err(dev, "Cryptocell reset not completed"); 403 } 404 405 if (hw_rev->rev <= CC_HW_REV_712) { 406 /* Verify correct mapping */ 407 val = cc_ioread(new_drvdata, new_drvdata->sig_offset); 408 if (val != hw_rev->sig) { 409 dev_err(dev, "Invalid CC signature: SIGNATURE=0x%08X != expected=0x%08X\n", 410 val, hw_rev->sig); 411 rc = -EINVAL; 412 goto post_pm_err; 413 } 414 sig_cidr = val; 415 hw_rev_pidr = cc_ioread(new_drvdata, new_drvdata->ver_offset); 416 } else { 417 /* Verify correct mapping */ 418 val = cc_read_idr(new_drvdata, pidr_0124_offsets); 419 if (val != hw_rev->pidr_0124) { 420 dev_err(dev, "Invalid CC PIDR: PIDR0124=0x%08X != expected=0x%08X\n", 421 val, hw_rev->pidr_0124); 422 rc = -EINVAL; 423 goto post_pm_err; 424 } 425 hw_rev_pidr = val; 426 427 val = cc_read_idr(new_drvdata, cidr_0123_offsets); 428 if (val != hw_rev->cidr_0123) { 429 dev_err(dev, "Invalid CC CIDR: CIDR0123=0x%08X != expected=0x%08X\n", 430 val, hw_rev->cidr_0123); 431 rc = -EINVAL; 432 goto post_pm_err; 433 } 434 sig_cidr = val; 435 436 /* Check HW engine configuration */ 437 val = cc_ioread(new_drvdata, CC_REG(HOST_REMOVE_INPUT_PINS)); 438 switch (val) { 439 case CC_PINS_FULL: 440 /* This is fine */ 441 break; 442 case CC_PINS_SLIM: 443 if (new_drvdata->std_bodies & CC_STD_NIST) { 444 dev_warn(dev, "703 mode forced due to HW configuration.\n"); 445 new_drvdata->std_bodies = CC_STD_OSCCA; 446 } 447 break; 448 default: 449 dev_err(dev, "Unsupported engines configuration.\n"); 450 rc = -EINVAL; 451 goto post_pm_err; 452 } 453 454 /* Check security disable state */ 455 val = cc_ioread(new_drvdata, CC_REG(SECURITY_DISABLED)); 456 val &= CC_SECURITY_DISABLED_MASK; 457 new_drvdata->sec_disabled |= !!val; 458 459 if (!new_drvdata->sec_disabled) { 460 new_drvdata->comp_mask |= CC_CPP_SM4_ABORT_MASK; 461 if (new_drvdata->std_bodies & CC_STD_NIST) 462 new_drvdata->comp_mask |= CC_CPP_AES_ABORT_MASK; 463 } 464 } 465 466 if (new_drvdata->sec_disabled) 467 dev_info(dev, "Security Disabled mode is in effect. Security functions disabled.\n"); 468 469 /* Display HW versions */ 470 dev_info(dev, "ARM CryptoCell %s Driver: HW version 0x%08X/0x%8X, Driver version %s\n", 471 hw_rev->name, hw_rev_pidr, sig_cidr, DRV_MODULE_VERSION); 472 /* register the driver isr function */ 473 rc = devm_request_irq(dev, irq, cc_isr, IRQF_SHARED, "ccree", 474 new_drvdata); 475 if (rc) { 476 dev_err(dev, "Could not register to interrupt %d\n", irq); 477 goto post_pm_err; 478 } 479 dev_dbg(dev, "Registered to IRQ: %d\n", irq); 480 481 init_cc_cache_params(new_drvdata); 482 483 rc = init_cc_regs(new_drvdata); 484 if (rc) { 485 dev_err(dev, "init_cc_regs failed\n"); 486 goto post_pm_err; 487 } 488 489 rc = cc_debugfs_init(new_drvdata); 490 if (rc) { 491 dev_err(dev, "Failed registering debugfs interface\n"); 492 goto post_regs_err; 493 } 494 495 rc = cc_fips_init(new_drvdata); 496 if (rc) { 497 dev_err(dev, "cc_fips_init failed 0x%x\n", rc); 498 goto post_debugfs_err; 499 } 500 rc = cc_sram_mgr_init(new_drvdata); 501 if (rc) { 502 dev_err(dev, "cc_sram_mgr_init failed\n"); 503 goto post_fips_init_err; 504 } 505 506 new_drvdata->mlli_sram_addr = 507 cc_sram_alloc(new_drvdata, MAX_MLLI_BUFF_SIZE); 508 if (new_drvdata->mlli_sram_addr == NULL_SRAM_ADDR) { 509 rc = -ENOMEM; 510 goto post_fips_init_err; 511 } 512 513 rc = cc_req_mgr_init(new_drvdata); 514 if (rc) { 515 dev_err(dev, "cc_req_mgr_init failed\n"); 516 goto post_fips_init_err; 517 } 518 519 rc = cc_buffer_mgr_init(new_drvdata); 520 if (rc) { 521 dev_err(dev, "cc_buffer_mgr_init failed\n"); 522 goto post_req_mgr_err; 523 } 524 525 /* hash must be allocated first due to use of send_request_init() 526 * and dependency of AEAD on it 527 */ 528 rc = cc_hash_alloc(new_drvdata); 529 if (rc) { 530 dev_err(dev, "cc_hash_alloc failed\n"); 531 goto post_buf_mgr_err; 532 } 533 534 /* Allocate crypto algs */ 535 rc = cc_cipher_alloc(new_drvdata); 536 if (rc) { 537 dev_err(dev, "cc_cipher_alloc failed\n"); 538 goto post_hash_err; 539 } 540 541 rc = cc_aead_alloc(new_drvdata); 542 if (rc) { 543 dev_err(dev, "cc_aead_alloc failed\n"); 544 goto post_cipher_err; 545 } 546 547 /* If we got here and FIPS mode is enabled 548 * it means all FIPS test passed, so let TEE 549 * know we're good. 550 */ 551 cc_set_ree_fips_status(new_drvdata, true); 552 553 pm_runtime_put(dev); 554 return 0; 555 556 post_cipher_err: 557 cc_cipher_free(new_drvdata); 558 post_hash_err: 559 cc_hash_free(new_drvdata); 560 post_buf_mgr_err: 561 cc_buffer_mgr_fini(new_drvdata); 562 post_req_mgr_err: 563 cc_req_mgr_fini(new_drvdata); 564 post_fips_init_err: 565 cc_fips_fini(new_drvdata); 566 post_debugfs_err: 567 cc_debugfs_fini(new_drvdata); 568 post_regs_err: 569 fini_cc_regs(new_drvdata); 570 post_pm_err: 571 pm_runtime_put_noidle(dev); 572 pm_runtime_disable(dev); 573 pm_runtime_set_suspended(dev); 574 clk_disable_unprepare(new_drvdata->clk); 575 return rc; 576 } 577 578 void fini_cc_regs(struct cc_drvdata *drvdata) 579 { 580 /* Mask all interrupts */ 581 cc_iowrite(drvdata, CC_REG(HOST_IMR), 0xFFFFFFFF); 582 } 583 584 static void cleanup_cc_resources(struct platform_device *plat_dev) 585 { 586 struct device *dev = &plat_dev->dev; 587 struct cc_drvdata *drvdata = 588 (struct cc_drvdata *)platform_get_drvdata(plat_dev); 589 590 cc_aead_free(drvdata); 591 cc_cipher_free(drvdata); 592 cc_hash_free(drvdata); 593 cc_buffer_mgr_fini(drvdata); 594 cc_req_mgr_fini(drvdata); 595 cc_fips_fini(drvdata); 596 cc_debugfs_fini(drvdata); 597 fini_cc_regs(drvdata); 598 pm_runtime_put_noidle(dev); 599 pm_runtime_disable(dev); 600 pm_runtime_set_suspended(dev); 601 clk_disable_unprepare(drvdata->clk); 602 } 603 604 unsigned int cc_get_default_hash_len(struct cc_drvdata *drvdata) 605 { 606 if (drvdata->hw_rev >= CC_HW_REV_712) 607 return HASH_LEN_SIZE_712; 608 else 609 return HASH_LEN_SIZE_630; 610 } 611 612 static int ccree_probe(struct platform_device *plat_dev) 613 { 614 int rc; 615 struct device *dev = &plat_dev->dev; 616 617 /* Map registers space */ 618 rc = init_cc_resources(plat_dev); 619 if (rc) 620 return rc; 621 622 dev_info(dev, "ARM ccree device initialized\n"); 623 624 return 0; 625 } 626 627 static int ccree_remove(struct platform_device *plat_dev) 628 { 629 struct device *dev = &plat_dev->dev; 630 631 dev_dbg(dev, "Releasing ccree resources...\n"); 632 633 cleanup_cc_resources(plat_dev); 634 635 dev_info(dev, "ARM ccree device terminated\n"); 636 637 return 0; 638 } 639 640 static struct platform_driver ccree_driver = { 641 .driver = { 642 .name = "ccree", 643 .of_match_table = arm_ccree_dev_of_match, 644 #ifdef CONFIG_PM 645 .pm = &ccree_pm, 646 #endif 647 }, 648 .probe = ccree_probe, 649 .remove = ccree_remove, 650 }; 651 652 static int __init ccree_init(void) 653 { 654 cc_debugfs_global_init(); 655 656 return platform_driver_register(&ccree_driver); 657 } 658 module_init(ccree_init); 659 660 static void __exit ccree_exit(void) 661 { 662 platform_driver_unregister(&ccree_driver); 663 cc_debugfs_global_fini(); 664 } 665 module_exit(ccree_exit); 666 667 /* Module description */ 668 MODULE_DESCRIPTION("ARM TrustZone CryptoCell REE Driver"); 669 MODULE_VERSION(DRV_MODULE_VERSION); 670 MODULE_AUTHOR("ARM"); 671 MODULE_LICENSE("GPL v2"); 672