1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (C) 2012-2019 ARM Limited or its affiliates. */ 3 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 7 #include <linux/crypto.h> 8 #include <linux/moduleparam.h> 9 #include <linux/types.h> 10 #include <linux/interrupt.h> 11 #include <linux/platform_device.h> 12 #include <linux/slab.h> 13 #include <linux/spinlock.h> 14 #include <linux/of.h> 15 #include <linux/clk.h> 16 #include <linux/of_address.h> 17 #include <linux/of_device.h> 18 #include <linux/pm_runtime.h> 19 20 #include "cc_driver.h" 21 #include "cc_request_mgr.h" 22 #include "cc_buffer_mgr.h" 23 #include "cc_debugfs.h" 24 #include "cc_cipher.h" 25 #include "cc_aead.h" 26 #include "cc_hash.h" 27 #include "cc_sram_mgr.h" 28 #include "cc_pm.h" 29 #include "cc_fips.h" 30 31 bool cc_dump_desc; 32 module_param_named(dump_desc, cc_dump_desc, bool, 0600); 33 MODULE_PARM_DESC(cc_dump_desc, "Dump descriptors to kernel log as debugging aid"); 34 bool cc_dump_bytes; 35 module_param_named(dump_bytes, cc_dump_bytes, bool, 0600); 36 MODULE_PARM_DESC(cc_dump_bytes, "Dump buffers to kernel log as debugging aid"); 37 38 static bool cc_sec_disable; 39 module_param_named(sec_disable, cc_sec_disable, bool, 0600); 40 MODULE_PARM_DESC(cc_sec_disable, "Disable security functions"); 41 42 struct cc_hw_data { 43 char *name; 44 enum cc_hw_rev rev; 45 u32 sig; 46 u32 cidr_0123; 47 u32 pidr_0124; 48 int std_bodies; 49 }; 50 51 #define CC_NUM_IDRS 4 52 #define CC_HW_RESET_LOOP_COUNT 10 53 54 /* Note: PIDR3 holds CMOD/Rev so ignored for HW identification purposes */ 55 static const u32 pidr_0124_offsets[CC_NUM_IDRS] = { 56 CC_REG(PERIPHERAL_ID_0), CC_REG(PERIPHERAL_ID_1), 57 CC_REG(PERIPHERAL_ID_2), CC_REG(PERIPHERAL_ID_4) 58 }; 59 60 static const u32 cidr_0123_offsets[CC_NUM_IDRS] = { 61 CC_REG(COMPONENT_ID_0), CC_REG(COMPONENT_ID_1), 62 CC_REG(COMPONENT_ID_2), CC_REG(COMPONENT_ID_3) 63 }; 64 65 /* Hardware revisions defs. */ 66 67 /* The 703 is a OSCCA only variant of the 713 */ 68 static const struct cc_hw_data cc703_hw = { 69 .name = "703", .rev = CC_HW_REV_713, .cidr_0123 = 0xB105F00DU, 70 .pidr_0124 = 0x040BB0D0U, .std_bodies = CC_STD_OSCCA 71 }; 72 73 static const struct cc_hw_data cc713_hw = { 74 .name = "713", .rev = CC_HW_REV_713, .cidr_0123 = 0xB105F00DU, 75 .pidr_0124 = 0x040BB0D0U, .std_bodies = CC_STD_ALL 76 }; 77 78 static const struct cc_hw_data cc712_hw = { 79 .name = "712", .rev = CC_HW_REV_712, .sig = 0xDCC71200U, 80 .std_bodies = CC_STD_ALL 81 }; 82 83 static const struct cc_hw_data cc710_hw = { 84 .name = "710", .rev = CC_HW_REV_710, .sig = 0xDCC63200U, 85 .std_bodies = CC_STD_ALL 86 }; 87 88 static const struct cc_hw_data cc630p_hw = { 89 .name = "630P", .rev = CC_HW_REV_630, .sig = 0xDCC63000U, 90 .std_bodies = CC_STD_ALL 91 }; 92 93 static const struct of_device_id arm_ccree_dev_of_match[] = { 94 { .compatible = "arm,cryptocell-703-ree", .data = &cc703_hw }, 95 { .compatible = "arm,cryptocell-713-ree", .data = &cc713_hw }, 96 { .compatible = "arm,cryptocell-712-ree", .data = &cc712_hw }, 97 { .compatible = "arm,cryptocell-710-ree", .data = &cc710_hw }, 98 { .compatible = "arm,cryptocell-630p-ree", .data = &cc630p_hw }, 99 {} 100 }; 101 MODULE_DEVICE_TABLE(of, arm_ccree_dev_of_match); 102 103 static void init_cc_cache_params(struct cc_drvdata *drvdata) 104 { 105 struct device *dev = drvdata_to_dev(drvdata); 106 u32 cache_params, ace_const, val, mask; 107 108 /* compute CC_AXIM_CACHE_PARAMS */ 109 cache_params = cc_ioread(drvdata, CC_REG(AXIM_CACHE_PARAMS)); 110 dev_dbg(dev, "Cache params previous: 0x%08X\n", cache_params); 111 112 /* non cached or write-back, write allocate */ 113 val = drvdata->coherent ? 0xb : 0x2; 114 115 mask = CC_GENMASK(CC_AXIM_CACHE_PARAMS_AWCACHE); 116 cache_params &= ~mask; 117 cache_params |= FIELD_PREP(mask, val); 118 119 mask = CC_GENMASK(CC_AXIM_CACHE_PARAMS_AWCACHE_LAST); 120 cache_params &= ~mask; 121 cache_params |= FIELD_PREP(mask, val); 122 123 mask = CC_GENMASK(CC_AXIM_CACHE_PARAMS_ARCACHE); 124 cache_params &= ~mask; 125 cache_params |= FIELD_PREP(mask, val); 126 127 drvdata->cache_params = cache_params; 128 129 dev_dbg(dev, "Cache params current: 0x%08X\n", cache_params); 130 131 if (drvdata->hw_rev <= CC_HW_REV_710) 132 return; 133 134 /* compute CC_AXIM_ACE_CONST */ 135 ace_const = cc_ioread(drvdata, CC_REG(AXIM_ACE_CONST)); 136 dev_dbg(dev, "ACE-const previous: 0x%08X\n", ace_const); 137 138 /* system or outer-sharable */ 139 val = drvdata->coherent ? 0x2 : 0x3; 140 141 mask = CC_GENMASK(CC_AXIM_ACE_CONST_ARDOMAIN); 142 ace_const &= ~mask; 143 ace_const |= FIELD_PREP(mask, val); 144 145 mask = CC_GENMASK(CC_AXIM_ACE_CONST_AWDOMAIN); 146 ace_const &= ~mask; 147 ace_const |= FIELD_PREP(mask, val); 148 149 dev_dbg(dev, "ACE-const current: 0x%08X\n", ace_const); 150 151 drvdata->ace_const = ace_const; 152 } 153 154 static u32 cc_read_idr(struct cc_drvdata *drvdata, const u32 *idr_offsets) 155 { 156 int i; 157 union { 158 u8 regs[CC_NUM_IDRS]; 159 __le32 val; 160 } idr; 161 162 for (i = 0; i < CC_NUM_IDRS; ++i) 163 idr.regs[i] = cc_ioread(drvdata, idr_offsets[i]); 164 165 return le32_to_cpu(idr.val); 166 } 167 168 void __dump_byte_array(const char *name, const u8 *buf, size_t len) 169 { 170 char prefix[64]; 171 172 if (!buf) 173 return; 174 175 snprintf(prefix, sizeof(prefix), "%s[%zu]: ", name, len); 176 177 print_hex_dump(KERN_DEBUG, prefix, DUMP_PREFIX_ADDRESS, 16, 1, buf, 178 len, false); 179 } 180 181 static irqreturn_t cc_isr(int irq, void *dev_id) 182 { 183 struct cc_drvdata *drvdata = (struct cc_drvdata *)dev_id; 184 struct device *dev = drvdata_to_dev(drvdata); 185 u32 irr; 186 u32 imr; 187 188 /* STAT_OP_TYPE_GENERIC STAT_PHASE_0: Interrupt */ 189 /* if driver suspended return, probably shared interrupt */ 190 if (pm_runtime_suspended(dev)) 191 return IRQ_NONE; 192 193 /* read the interrupt status */ 194 irr = cc_ioread(drvdata, CC_REG(HOST_IRR)); 195 dev_dbg(dev, "Got IRR=0x%08X\n", irr); 196 197 if (irr == 0) /* Probably shared interrupt line */ 198 return IRQ_NONE; 199 200 imr = cc_ioread(drvdata, CC_REG(HOST_IMR)); 201 202 /* clear interrupt - must be before processing events */ 203 cc_iowrite(drvdata, CC_REG(HOST_ICR), irr); 204 205 drvdata->irq = irr; 206 /* Completion interrupt - most probable */ 207 if (irr & drvdata->comp_mask) { 208 /* Mask all completion interrupts - will be unmasked in 209 * deferred service handler 210 */ 211 cc_iowrite(drvdata, CC_REG(HOST_IMR), imr | drvdata->comp_mask); 212 irr &= ~drvdata->comp_mask; 213 complete_request(drvdata); 214 } 215 #ifdef CONFIG_CRYPTO_FIPS 216 /* TEE FIPS interrupt */ 217 if (irr & CC_GPR0_IRQ_MASK) { 218 /* Mask interrupt - will be unmasked in Deferred service 219 * handler 220 */ 221 cc_iowrite(drvdata, CC_REG(HOST_IMR), imr | CC_GPR0_IRQ_MASK); 222 irr &= ~CC_GPR0_IRQ_MASK; 223 fips_handler(drvdata); 224 } 225 #endif 226 /* AXI error interrupt */ 227 if (irr & CC_AXI_ERR_IRQ_MASK) { 228 u32 axi_err; 229 230 /* Read the AXI error ID */ 231 axi_err = cc_ioread(drvdata, CC_REG(AXIM_MON_ERR)); 232 dev_dbg(dev, "AXI completion error: axim_mon_err=0x%08X\n", 233 axi_err); 234 235 irr &= ~CC_AXI_ERR_IRQ_MASK; 236 } 237 238 if (irr) { 239 dev_dbg_ratelimited(dev, "IRR includes unknown cause bits (0x%08X)\n", 240 irr); 241 /* Just warning */ 242 } 243 244 return IRQ_HANDLED; 245 } 246 247 bool cc_wait_for_reset_completion(struct cc_drvdata *drvdata) 248 { 249 unsigned int val; 250 unsigned int i; 251 252 /* 712/710/63 has no reset completion indication, always return true */ 253 if (drvdata->hw_rev <= CC_HW_REV_712) 254 return true; 255 256 for (i = 0; i < CC_HW_RESET_LOOP_COUNT; i++) { 257 /* in cc7x3 NVM_IS_IDLE indicates that CC reset is 258 * completed and device is fully functional 259 */ 260 val = cc_ioread(drvdata, CC_REG(NVM_IS_IDLE)); 261 if (val & CC_NVM_IS_IDLE_MASK) { 262 /* hw indicate reset completed */ 263 return true; 264 } 265 /* allow scheduling other process on the processor */ 266 schedule(); 267 } 268 /* reset not completed */ 269 return false; 270 } 271 272 int init_cc_regs(struct cc_drvdata *drvdata) 273 { 274 unsigned int val; 275 struct device *dev = drvdata_to_dev(drvdata); 276 277 /* Unmask all AXI interrupt sources AXI_CFG1 register */ 278 /* AXI interrupt config are obsoleted startign at cc7x3 */ 279 if (drvdata->hw_rev <= CC_HW_REV_712) { 280 val = cc_ioread(drvdata, CC_REG(AXIM_CFG)); 281 cc_iowrite(drvdata, CC_REG(AXIM_CFG), val & ~CC_AXI_IRQ_MASK); 282 dev_dbg(dev, "AXIM_CFG=0x%08X\n", 283 cc_ioread(drvdata, CC_REG(AXIM_CFG))); 284 } 285 286 /* Clear all pending interrupts */ 287 val = cc_ioread(drvdata, CC_REG(HOST_IRR)); 288 dev_dbg(dev, "IRR=0x%08X\n", val); 289 cc_iowrite(drvdata, CC_REG(HOST_ICR), val); 290 291 /* Unmask relevant interrupt cause */ 292 val = drvdata->comp_mask | CC_AXI_ERR_IRQ_MASK; 293 294 if (drvdata->hw_rev >= CC_HW_REV_712) 295 val |= CC_GPR0_IRQ_MASK; 296 297 cc_iowrite(drvdata, CC_REG(HOST_IMR), ~val); 298 299 cc_iowrite(drvdata, CC_REG(AXIM_CACHE_PARAMS), drvdata->cache_params); 300 if (drvdata->hw_rev >= CC_HW_REV_712) 301 cc_iowrite(drvdata, CC_REG(AXIM_ACE_CONST), drvdata->ace_const); 302 303 return 0; 304 } 305 306 static int init_cc_resources(struct platform_device *plat_dev) 307 { 308 struct resource *req_mem_cc_regs = NULL; 309 struct cc_drvdata *new_drvdata; 310 struct device *dev = &plat_dev->dev; 311 struct device_node *np = dev->of_node; 312 u32 val, hw_rev_pidr, sig_cidr; 313 u64 dma_mask; 314 const struct cc_hw_data *hw_rev; 315 struct clk *clk; 316 int irq; 317 int rc = 0; 318 319 new_drvdata = devm_kzalloc(dev, sizeof(*new_drvdata), GFP_KERNEL); 320 if (!new_drvdata) 321 return -ENOMEM; 322 323 hw_rev = of_device_get_match_data(dev); 324 new_drvdata->hw_rev_name = hw_rev->name; 325 new_drvdata->hw_rev = hw_rev->rev; 326 new_drvdata->std_bodies = hw_rev->std_bodies; 327 328 if (hw_rev->rev >= CC_HW_REV_712) { 329 new_drvdata->axim_mon_offset = CC_REG(AXIM_MON_COMP); 330 new_drvdata->sig_offset = CC_REG(HOST_SIGNATURE_712); 331 new_drvdata->ver_offset = CC_REG(HOST_VERSION_712); 332 } else { 333 new_drvdata->axim_mon_offset = CC_REG(AXIM_MON_COMP8); 334 new_drvdata->sig_offset = CC_REG(HOST_SIGNATURE_630); 335 new_drvdata->ver_offset = CC_REG(HOST_VERSION_630); 336 } 337 338 new_drvdata->comp_mask = CC_COMP_IRQ_MASK; 339 340 platform_set_drvdata(plat_dev, new_drvdata); 341 new_drvdata->plat_dev = plat_dev; 342 343 clk = devm_clk_get_optional(dev, NULL); 344 if (IS_ERR(clk)) 345 return dev_err_probe(dev, PTR_ERR(clk), "Error getting clock\n"); 346 new_drvdata->clk = clk; 347 348 new_drvdata->coherent = of_dma_is_coherent(np); 349 350 /* Get device resources */ 351 /* First CC registers space */ 352 req_mem_cc_regs = platform_get_resource(plat_dev, IORESOURCE_MEM, 0); 353 /* Map registers space */ 354 new_drvdata->cc_base = devm_ioremap_resource(dev, req_mem_cc_regs); 355 if (IS_ERR(new_drvdata->cc_base)) { 356 dev_err(dev, "Failed to ioremap registers"); 357 return PTR_ERR(new_drvdata->cc_base); 358 } 359 360 dev_dbg(dev, "Got MEM resource (%s): %pR\n", req_mem_cc_regs->name, 361 req_mem_cc_regs); 362 dev_dbg(dev, "CC registers mapped from %pa to 0x%p\n", 363 &req_mem_cc_regs->start, new_drvdata->cc_base); 364 365 /* Then IRQ */ 366 irq = platform_get_irq(plat_dev, 0); 367 if (irq < 0) 368 return irq; 369 370 init_completion(&new_drvdata->hw_queue_avail); 371 372 if (!dev->dma_mask) 373 dev->dma_mask = &dev->coherent_dma_mask; 374 375 dma_mask = DMA_BIT_MASK(DMA_BIT_MASK_LEN); 376 while (dma_mask > 0x7fffffffUL) { 377 if (dma_supported(dev, dma_mask)) { 378 rc = dma_set_coherent_mask(dev, dma_mask); 379 if (!rc) 380 break; 381 } 382 dma_mask >>= 1; 383 } 384 385 if (rc) { 386 dev_err(dev, "Failed in dma_set_mask, mask=%llx\n", dma_mask); 387 return rc; 388 } 389 390 rc = clk_prepare_enable(new_drvdata->clk); 391 if (rc) { 392 dev_err(dev, "Failed to enable clock"); 393 return rc; 394 } 395 396 new_drvdata->sec_disabled = cc_sec_disable; 397 398 pm_runtime_set_autosuspend_delay(dev, CC_SUSPEND_TIMEOUT); 399 pm_runtime_use_autosuspend(dev); 400 pm_runtime_set_active(dev); 401 pm_runtime_enable(dev); 402 rc = pm_runtime_get_sync(dev); 403 if (rc < 0) { 404 dev_err(dev, "pm_runtime_get_sync() failed: %d\n", rc); 405 goto post_pm_err; 406 } 407 408 /* Wait for Cryptocell reset completion */ 409 if (!cc_wait_for_reset_completion(new_drvdata)) { 410 dev_err(dev, "Cryptocell reset not completed"); 411 } 412 413 if (hw_rev->rev <= CC_HW_REV_712) { 414 /* Verify correct mapping */ 415 val = cc_ioread(new_drvdata, new_drvdata->sig_offset); 416 if (val != hw_rev->sig) { 417 dev_err(dev, "Invalid CC signature: SIGNATURE=0x%08X != expected=0x%08X\n", 418 val, hw_rev->sig); 419 rc = -EINVAL; 420 goto post_pm_err; 421 } 422 sig_cidr = val; 423 hw_rev_pidr = cc_ioread(new_drvdata, new_drvdata->ver_offset); 424 } else { 425 /* Verify correct mapping */ 426 val = cc_read_idr(new_drvdata, pidr_0124_offsets); 427 if (val != hw_rev->pidr_0124) { 428 dev_err(dev, "Invalid CC PIDR: PIDR0124=0x%08X != expected=0x%08X\n", 429 val, hw_rev->pidr_0124); 430 rc = -EINVAL; 431 goto post_pm_err; 432 } 433 hw_rev_pidr = val; 434 435 val = cc_read_idr(new_drvdata, cidr_0123_offsets); 436 if (val != hw_rev->cidr_0123) { 437 dev_err(dev, "Invalid CC CIDR: CIDR0123=0x%08X != expected=0x%08X\n", 438 val, hw_rev->cidr_0123); 439 rc = -EINVAL; 440 goto post_pm_err; 441 } 442 sig_cidr = val; 443 444 /* Check HW engine configuration */ 445 val = cc_ioread(new_drvdata, CC_REG(HOST_REMOVE_INPUT_PINS)); 446 switch (val) { 447 case CC_PINS_FULL: 448 /* This is fine */ 449 break; 450 case CC_PINS_SLIM: 451 if (new_drvdata->std_bodies & CC_STD_NIST) { 452 dev_warn(dev, "703 mode forced due to HW configuration.\n"); 453 new_drvdata->std_bodies = CC_STD_OSCCA; 454 } 455 break; 456 default: 457 dev_err(dev, "Unsupported engines configuration.\n"); 458 rc = -EINVAL; 459 goto post_pm_err; 460 } 461 462 /* Check security disable state */ 463 val = cc_ioread(new_drvdata, CC_REG(SECURITY_DISABLED)); 464 val &= CC_SECURITY_DISABLED_MASK; 465 new_drvdata->sec_disabled |= !!val; 466 467 if (!new_drvdata->sec_disabled) { 468 new_drvdata->comp_mask |= CC_CPP_SM4_ABORT_MASK; 469 if (new_drvdata->std_bodies & CC_STD_NIST) 470 new_drvdata->comp_mask |= CC_CPP_AES_ABORT_MASK; 471 } 472 } 473 474 if (new_drvdata->sec_disabled) 475 dev_info(dev, "Security Disabled mode is in effect. Security functions disabled.\n"); 476 477 /* Display HW versions */ 478 dev_info(dev, "ARM CryptoCell %s Driver: HW version 0x%08X/0x%8X, Driver version %s\n", 479 hw_rev->name, hw_rev_pidr, sig_cidr, DRV_MODULE_VERSION); 480 /* register the driver isr function */ 481 rc = devm_request_irq(dev, irq, cc_isr, IRQF_SHARED, "ccree", 482 new_drvdata); 483 if (rc) { 484 dev_err(dev, "Could not register to interrupt %d\n", irq); 485 goto post_pm_err; 486 } 487 dev_dbg(dev, "Registered to IRQ: %d\n", irq); 488 489 init_cc_cache_params(new_drvdata); 490 491 rc = init_cc_regs(new_drvdata); 492 if (rc) { 493 dev_err(dev, "init_cc_regs failed\n"); 494 goto post_pm_err; 495 } 496 497 rc = cc_debugfs_init(new_drvdata); 498 if (rc) { 499 dev_err(dev, "Failed registering debugfs interface\n"); 500 goto post_regs_err; 501 } 502 503 rc = cc_fips_init(new_drvdata); 504 if (rc) { 505 dev_err(dev, "cc_fips_init failed 0x%x\n", rc); 506 goto post_debugfs_err; 507 } 508 rc = cc_sram_mgr_init(new_drvdata); 509 if (rc) { 510 dev_err(dev, "cc_sram_mgr_init failed\n"); 511 goto post_fips_init_err; 512 } 513 514 new_drvdata->mlli_sram_addr = 515 cc_sram_alloc(new_drvdata, MAX_MLLI_BUFF_SIZE); 516 if (new_drvdata->mlli_sram_addr == NULL_SRAM_ADDR) { 517 rc = -ENOMEM; 518 goto post_fips_init_err; 519 } 520 521 rc = cc_req_mgr_init(new_drvdata); 522 if (rc) { 523 dev_err(dev, "cc_req_mgr_init failed\n"); 524 goto post_fips_init_err; 525 } 526 527 rc = cc_buffer_mgr_init(new_drvdata); 528 if (rc) { 529 dev_err(dev, "cc_buffer_mgr_init failed\n"); 530 goto post_req_mgr_err; 531 } 532 533 /* Allocate crypto algs */ 534 rc = cc_cipher_alloc(new_drvdata); 535 if (rc) { 536 dev_err(dev, "cc_cipher_alloc failed\n"); 537 goto post_buf_mgr_err; 538 } 539 540 /* hash must be allocated before aead since hash exports APIs */ 541 rc = cc_hash_alloc(new_drvdata); 542 if (rc) { 543 dev_err(dev, "cc_hash_alloc failed\n"); 544 goto post_cipher_err; 545 } 546 547 rc = cc_aead_alloc(new_drvdata); 548 if (rc) { 549 dev_err(dev, "cc_aead_alloc failed\n"); 550 goto post_hash_err; 551 } 552 553 /* If we got here and FIPS mode is enabled 554 * it means all FIPS test passed, so let TEE 555 * know we're good. 556 */ 557 cc_set_ree_fips_status(new_drvdata, true); 558 559 pm_runtime_put(dev); 560 return 0; 561 562 post_hash_err: 563 cc_hash_free(new_drvdata); 564 post_cipher_err: 565 cc_cipher_free(new_drvdata); 566 post_buf_mgr_err: 567 cc_buffer_mgr_fini(new_drvdata); 568 post_req_mgr_err: 569 cc_req_mgr_fini(new_drvdata); 570 post_fips_init_err: 571 cc_fips_fini(new_drvdata); 572 post_debugfs_err: 573 cc_debugfs_fini(new_drvdata); 574 post_regs_err: 575 fini_cc_regs(new_drvdata); 576 post_pm_err: 577 pm_runtime_put_noidle(dev); 578 pm_runtime_disable(dev); 579 pm_runtime_set_suspended(dev); 580 clk_disable_unprepare(new_drvdata->clk); 581 return rc; 582 } 583 584 void fini_cc_regs(struct cc_drvdata *drvdata) 585 { 586 /* Mask all interrupts */ 587 cc_iowrite(drvdata, CC_REG(HOST_IMR), 0xFFFFFFFF); 588 } 589 590 static void cleanup_cc_resources(struct platform_device *plat_dev) 591 { 592 struct device *dev = &plat_dev->dev; 593 struct cc_drvdata *drvdata = 594 (struct cc_drvdata *)platform_get_drvdata(plat_dev); 595 596 cc_aead_free(drvdata); 597 cc_hash_free(drvdata); 598 cc_cipher_free(drvdata); 599 cc_buffer_mgr_fini(drvdata); 600 cc_req_mgr_fini(drvdata); 601 cc_fips_fini(drvdata); 602 cc_debugfs_fini(drvdata); 603 fini_cc_regs(drvdata); 604 pm_runtime_put_noidle(dev); 605 pm_runtime_disable(dev); 606 pm_runtime_set_suspended(dev); 607 clk_disable_unprepare(drvdata->clk); 608 } 609 610 unsigned int cc_get_default_hash_len(struct cc_drvdata *drvdata) 611 { 612 if (drvdata->hw_rev >= CC_HW_REV_712) 613 return HASH_LEN_SIZE_712; 614 else 615 return HASH_LEN_SIZE_630; 616 } 617 618 static int ccree_probe(struct platform_device *plat_dev) 619 { 620 int rc; 621 struct device *dev = &plat_dev->dev; 622 623 /* Map registers space */ 624 rc = init_cc_resources(plat_dev); 625 if (rc) 626 return rc; 627 628 dev_info(dev, "ARM ccree device initialized\n"); 629 630 return 0; 631 } 632 633 static int ccree_remove(struct platform_device *plat_dev) 634 { 635 struct device *dev = &plat_dev->dev; 636 637 dev_dbg(dev, "Releasing ccree resources...\n"); 638 639 cleanup_cc_resources(plat_dev); 640 641 dev_info(dev, "ARM ccree device terminated\n"); 642 643 return 0; 644 } 645 646 static struct platform_driver ccree_driver = { 647 .driver = { 648 .name = "ccree", 649 .of_match_table = arm_ccree_dev_of_match, 650 #ifdef CONFIG_PM 651 .pm = &ccree_pm, 652 #endif 653 }, 654 .probe = ccree_probe, 655 .remove = ccree_remove, 656 }; 657 658 static int __init ccree_init(void) 659 { 660 cc_debugfs_global_init(); 661 662 return platform_driver_register(&ccree_driver); 663 } 664 module_init(ccree_init); 665 666 static void __exit ccree_exit(void) 667 { 668 platform_driver_unregister(&ccree_driver); 669 cc_debugfs_global_fini(); 670 } 671 module_exit(ccree_exit); 672 673 /* Module description */ 674 MODULE_DESCRIPTION("ARM TrustZone CryptoCell REE Driver"); 675 MODULE_VERSION(DRV_MODULE_VERSION); 676 MODULE_AUTHOR("ARM"); 677 MODULE_LICENSE("GPL v2"); 678