xref: /openbmc/linux/drivers/crypto/ccp/ccp-dev.h (revision 5d0e4d78)
1 /*
2  * AMD Cryptographic Coprocessor (CCP) driver
3  *
4  * Copyright (C) 2013,2016 Advanced Micro Devices, Inc.
5  *
6  * Author: Tom Lendacky <thomas.lendacky@amd.com>
7  * Author: Gary R Hook <gary.hook@amd.com>
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License version 2 as
11  * published by the Free Software Foundation.
12  */
13 
14 #ifndef __CCP_DEV_H__
15 #define __CCP_DEV_H__
16 
17 #include <linux/device.h>
18 #include <linux/pci.h>
19 #include <linux/spinlock.h>
20 #include <linux/mutex.h>
21 #include <linux/list.h>
22 #include <linux/wait.h>
23 #include <linux/dmapool.h>
24 #include <linux/hw_random.h>
25 #include <linux/bitops.h>
26 #include <linux/interrupt.h>
27 #include <linux/irqreturn.h>
28 #include <linux/dmaengine.h>
29 
30 #define MAX_CCP_NAME_LEN		16
31 #define MAX_DMAPOOL_NAME_LEN		32
32 
33 #define MAX_HW_QUEUES			5
34 #define MAX_CMD_QLEN			100
35 
36 #define TRNG_RETRIES			10
37 
38 #define CACHE_NONE			0x00
39 #define CACHE_WB_NO_ALLOC		0xb7
40 
41 /****** Register Mappings ******/
42 #define Q_MASK_REG			0x000
43 #define TRNG_OUT_REG			0x00c
44 #define IRQ_MASK_REG			0x040
45 #define IRQ_STATUS_REG			0x200
46 
47 #define DEL_CMD_Q_JOB			0x124
48 #define DEL_Q_ACTIVE			0x00000200
49 #define DEL_Q_ID_SHIFT			6
50 
51 #define CMD_REQ0			0x180
52 #define CMD_REQ_INCR			0x04
53 
54 #define CMD_Q_STATUS_BASE		0x210
55 #define CMD_Q_INT_STATUS_BASE		0x214
56 #define CMD_Q_STATUS_INCR		0x20
57 
58 #define CMD_Q_CACHE_BASE		0x228
59 #define CMD_Q_CACHE_INC			0x20
60 
61 #define CMD_Q_ERROR(__qs)		((__qs) & 0x0000003f)
62 #define CMD_Q_DEPTH(__qs)		(((__qs) >> 12) & 0x0000000f)
63 
64 /* ------------------------ CCP Version 5 Specifics ------------------------ */
65 #define CMD5_QUEUE_MASK_OFFSET		0x00
66 #define	CMD5_QUEUE_PRIO_OFFSET		0x04
67 #define CMD5_REQID_CONFIG_OFFSET	0x08
68 #define	CMD5_CMD_TIMEOUT_OFFSET		0x10
69 #define LSB_PUBLIC_MASK_LO_OFFSET	0x18
70 #define LSB_PUBLIC_MASK_HI_OFFSET	0x1C
71 #define LSB_PRIVATE_MASK_LO_OFFSET	0x20
72 #define LSB_PRIVATE_MASK_HI_OFFSET	0x24
73 #define CMD5_PSP_CCP_VERSION		0x100
74 
75 #define CMD5_Q_CONTROL_BASE		0x0000
76 #define CMD5_Q_TAIL_LO_BASE		0x0004
77 #define CMD5_Q_HEAD_LO_BASE		0x0008
78 #define CMD5_Q_INT_ENABLE_BASE		0x000C
79 #define CMD5_Q_INTERRUPT_STATUS_BASE	0x0010
80 
81 #define CMD5_Q_STATUS_BASE		0x0100
82 #define CMD5_Q_INT_STATUS_BASE		0x0104
83 #define CMD5_Q_DMA_STATUS_BASE		0x0108
84 #define CMD5_Q_DMA_READ_STATUS_BASE	0x010C
85 #define CMD5_Q_DMA_WRITE_STATUS_BASE	0x0110
86 #define CMD5_Q_ABORT_BASE		0x0114
87 #define CMD5_Q_AX_CACHE_BASE		0x0118
88 
89 #define	CMD5_CONFIG_0_OFFSET		0x6000
90 #define	CMD5_TRNG_CTL_OFFSET		0x6008
91 #define	CMD5_AES_MASK_OFFSET		0x6010
92 #define	CMD5_CLK_GATE_CTL_OFFSET	0x603C
93 
94 /* Address offset between two virtual queue registers */
95 #define CMD5_Q_STATUS_INCR		0x1000
96 
97 /* Bit masks */
98 #define CMD5_Q_RUN			0x1
99 #define CMD5_Q_HALT			0x2
100 #define CMD5_Q_MEM_LOCATION		0x4
101 #define CMD5_Q_SIZE			0x1F
102 #define CMD5_Q_SHIFT			3
103 #define COMMANDS_PER_QUEUE		16
104 #define QUEUE_SIZE_VAL			((ffs(COMMANDS_PER_QUEUE) - 2) & \
105 					  CMD5_Q_SIZE)
106 #define Q_PTR_MASK			(2 << (QUEUE_SIZE_VAL + 5) - 1)
107 #define Q_DESC_SIZE			sizeof(struct ccp5_desc)
108 #define Q_SIZE(n)			(COMMANDS_PER_QUEUE*(n))
109 
110 #define INT_COMPLETION			0x1
111 #define INT_ERROR			0x2
112 #define INT_QUEUE_STOPPED		0x4
113 #define	INT_EMPTY_QUEUE			0x8
114 #define SUPPORTED_INTERRUPTS		(INT_COMPLETION | INT_ERROR)
115 
116 #define LSB_REGION_WIDTH		5
117 #define MAX_LSB_CNT			8
118 
119 #define LSB_SIZE			16
120 #define LSB_ITEM_SIZE			32
121 #define PLSB_MAP_SIZE			(LSB_SIZE)
122 #define SLSB_MAP_SIZE			(MAX_LSB_CNT * LSB_SIZE)
123 
124 #define LSB_ENTRY_NUMBER(LSB_ADDR)	(LSB_ADDR / LSB_ITEM_SIZE)
125 
126 /* ------------------------ CCP Version 3 Specifics ------------------------ */
127 #define REQ0_WAIT_FOR_WRITE		0x00000004
128 #define REQ0_INT_ON_COMPLETE		0x00000002
129 #define REQ0_STOP_ON_COMPLETE		0x00000001
130 
131 #define REQ0_CMD_Q_SHIFT		9
132 #define REQ0_JOBID_SHIFT		3
133 
134 /****** REQ1 Related Values ******/
135 #define REQ1_PROTECT_SHIFT		27
136 #define REQ1_ENGINE_SHIFT		23
137 #define REQ1_KEY_KSB_SHIFT		2
138 
139 #define REQ1_EOM			0x00000002
140 #define REQ1_INIT			0x00000001
141 
142 /* AES Related Values */
143 #define REQ1_AES_TYPE_SHIFT		21
144 #define REQ1_AES_MODE_SHIFT		18
145 #define REQ1_AES_ACTION_SHIFT		17
146 #define REQ1_AES_CFB_SIZE_SHIFT		10
147 
148 /* XTS-AES Related Values */
149 #define REQ1_XTS_AES_SIZE_SHIFT		10
150 
151 /* SHA Related Values */
152 #define REQ1_SHA_TYPE_SHIFT		21
153 
154 /* RSA Related Values */
155 #define REQ1_RSA_MOD_SIZE_SHIFT		10
156 
157 /* Pass-Through Related Values */
158 #define REQ1_PT_BW_SHIFT		12
159 #define REQ1_PT_BS_SHIFT		10
160 
161 /* ECC Related Values */
162 #define REQ1_ECC_AFFINE_CONVERT		0x00200000
163 #define REQ1_ECC_FUNCTION_SHIFT		18
164 
165 /****** REQ4 Related Values ******/
166 #define REQ4_KSB_SHIFT			18
167 #define REQ4_MEMTYPE_SHIFT		16
168 
169 /****** REQ6 Related Values ******/
170 #define REQ6_MEMTYPE_SHIFT		16
171 
172 /****** Key Storage Block ******/
173 #define KSB_START			77
174 #define KSB_END				127
175 #define KSB_COUNT			(KSB_END - KSB_START + 1)
176 #define CCP_SB_BITS			256
177 
178 #define CCP_JOBID_MASK			0x0000003f
179 
180 /* ------------------------ General CCP Defines ------------------------ */
181 
182 #define	CCP_DMA_DFLT			0x0
183 #define	CCP_DMA_PRIV			0x1
184 #define	CCP_DMA_PUB			0x2
185 
186 #define CCP_DMAPOOL_MAX_SIZE		64
187 #define CCP_DMAPOOL_ALIGN		BIT(5)
188 
189 #define CCP_REVERSE_BUF_SIZE		64
190 
191 #define CCP_AES_KEY_SB_COUNT		1
192 #define CCP_AES_CTX_SB_COUNT		1
193 
194 #define CCP_XTS_AES_KEY_SB_COUNT	1
195 #define CCP_XTS_AES_CTX_SB_COUNT	1
196 
197 #define CCP_DES3_KEY_SB_COUNT		1
198 #define CCP_DES3_CTX_SB_COUNT		1
199 
200 #define CCP_SHA_SB_COUNT		1
201 
202 #define CCP_RSA_MAX_WIDTH		4096
203 
204 #define CCP_PASSTHRU_BLOCKSIZE		256
205 #define CCP_PASSTHRU_MASKSIZE		32
206 #define CCP_PASSTHRU_SB_COUNT		1
207 
208 #define CCP_ECC_MODULUS_BYTES		48      /* 384-bits */
209 #define CCP_ECC_MAX_OPERANDS		6
210 #define CCP_ECC_MAX_OUTPUTS		3
211 #define CCP_ECC_SRC_BUF_SIZE		448
212 #define CCP_ECC_DST_BUF_SIZE		192
213 #define CCP_ECC_OPERAND_SIZE		64
214 #define CCP_ECC_OUTPUT_SIZE		64
215 #define CCP_ECC_RESULT_OFFSET		60
216 #define CCP_ECC_RESULT_SUCCESS		0x0001
217 
218 #define CCP_SB_BYTES			32
219 
220 struct ccp_op;
221 struct ccp_device;
222 struct ccp_cmd;
223 struct ccp_fns;
224 
225 struct ccp_dma_cmd {
226 	struct list_head entry;
227 
228 	struct ccp_cmd ccp_cmd;
229 };
230 
231 struct ccp_dma_desc {
232 	struct list_head entry;
233 
234 	struct ccp_device *ccp;
235 
236 	struct list_head pending;
237 	struct list_head active;
238 
239 	enum dma_status status;
240 	struct dma_async_tx_descriptor tx_desc;
241 	size_t len;
242 };
243 
244 struct ccp_dma_chan {
245 	struct ccp_device *ccp;
246 
247 	spinlock_t lock;
248 	struct list_head created;
249 	struct list_head pending;
250 	struct list_head active;
251 	struct list_head complete;
252 
253 	struct tasklet_struct cleanup_tasklet;
254 
255 	enum dma_status status;
256 	struct dma_chan dma_chan;
257 };
258 
259 struct ccp_cmd_queue {
260 	struct ccp_device *ccp;
261 
262 	/* Queue identifier */
263 	u32 id;
264 
265 	/* Queue dma pool */
266 	struct dma_pool *dma_pool;
267 
268 	/* Queue base address (not neccessarily aligned)*/
269 	struct ccp5_desc *qbase;
270 
271 	/* Aligned queue start address (per requirement) */
272 	struct mutex q_mutex ____cacheline_aligned;
273 	unsigned int qidx;
274 
275 	/* Version 5 has different requirements for queue memory */
276 	unsigned int qsize;
277 	dma_addr_t qbase_dma;
278 	dma_addr_t qdma_tail;
279 
280 	/* Per-queue reserved storage block(s) */
281 	u32 sb_key;
282 	u32 sb_ctx;
283 
284 	/* Bitmap of LSBs that can be accessed by this queue */
285 	DECLARE_BITMAP(lsbmask, MAX_LSB_CNT);
286 	/* Private LSB that is assigned to this queue, or -1 if none.
287 	 * Bitmap for my private LSB, unused otherwise
288 	 */
289 	int lsb;
290 	DECLARE_BITMAP(lsbmap, PLSB_MAP_SIZE);
291 
292 	/* Queue processing thread */
293 	struct task_struct *kthread;
294 	unsigned int active;
295 	unsigned int suspended;
296 
297 	/* Number of free command slots available */
298 	unsigned int free_slots;
299 
300 	/* Interrupt masks */
301 	u32 int_ok;
302 	u32 int_err;
303 
304 	/* Register addresses for queue */
305 	void __iomem *reg_control;
306 	void __iomem *reg_tail_lo;
307 	void __iomem *reg_head_lo;
308 	void __iomem *reg_int_enable;
309 	void __iomem *reg_interrupt_status;
310 	void __iomem *reg_status;
311 	void __iomem *reg_int_status;
312 	void __iomem *reg_dma_status;
313 	void __iomem *reg_dma_read_status;
314 	void __iomem *reg_dma_write_status;
315 	u32 qcontrol; /* Cached control register */
316 
317 	/* Status values from job */
318 	u32 int_status;
319 	u32 q_status;
320 	u32 q_int_status;
321 	u32 cmd_error;
322 
323 	/* Interrupt wait queue */
324 	wait_queue_head_t int_queue;
325 	unsigned int int_rcvd;
326 
327 	/* Per-queue Statistics */
328 	unsigned long total_ops;
329 	unsigned long total_aes_ops;
330 	unsigned long total_xts_aes_ops;
331 	unsigned long total_3des_ops;
332 	unsigned long total_sha_ops;
333 	unsigned long total_rsa_ops;
334 	unsigned long total_pt_ops;
335 	unsigned long total_ecc_ops;
336 } ____cacheline_aligned;
337 
338 struct ccp_device {
339 	struct list_head entry;
340 
341 	struct ccp_vdata *vdata;
342 	unsigned int ord;
343 	char name[MAX_CCP_NAME_LEN];
344 	char rngname[MAX_CCP_NAME_LEN];
345 
346 	struct device *dev;
347 
348 	/* Bus specific device information
349 	 */
350 	void *dev_specific;
351 	int (*get_irq)(struct ccp_device *ccp);
352 	void (*free_irq)(struct ccp_device *ccp);
353 	unsigned int qim;
354 	unsigned int irq;
355 	bool use_tasklet;
356 	struct tasklet_struct irq_tasklet;
357 
358 	/* I/O area used for device communication. The register mapping
359 	 * starts at an offset into the mapped bar.
360 	 *   The CMD_REQx registers and the Delete_Cmd_Queue_Job register
361 	 *   need to be protected while a command queue thread is accessing
362 	 *   them.
363 	 */
364 	struct mutex req_mutex ____cacheline_aligned;
365 	void __iomem *io_map;
366 	void __iomem *io_regs;
367 
368 	/* Master lists that all cmds are queued on. Because there can be
369 	 * more than one CCP command queue that can process a cmd a separate
370 	 * backlog list is neeeded so that the backlog completion call
371 	 * completes before the cmd is available for execution.
372 	 */
373 	spinlock_t cmd_lock ____cacheline_aligned;
374 	unsigned int cmd_count;
375 	struct list_head cmd;
376 	struct list_head backlog;
377 
378 	/* The command queues. These represent the queues available on the
379 	 * CCP that are available for processing cmds
380 	 */
381 	struct ccp_cmd_queue cmd_q[MAX_HW_QUEUES];
382 	unsigned int cmd_q_count;
383 
384 	/* Support for the CCP True RNG
385 	 */
386 	struct hwrng hwrng;
387 	unsigned int hwrng_retries;
388 
389 	/* Support for the CCP DMA capabilities
390 	 */
391 	struct dma_device dma_dev;
392 	struct ccp_dma_chan *ccp_dma_chan;
393 	struct kmem_cache *dma_cmd_cache;
394 	struct kmem_cache *dma_desc_cache;
395 
396 	/* A counter used to generate job-ids for cmds submitted to the CCP
397 	 */
398 	atomic_t current_id ____cacheline_aligned;
399 
400 	/* The v3 CCP uses key storage blocks (SB) to maintain context for
401 	 * certain operations. To prevent multiple cmds from using the same
402 	 * SB range a command queue reserves an SB range for the duration of
403 	 * the cmd. Each queue, will however, reserve 2 SB blocks for
404 	 * operations that only require single SB entries (eg. AES context/iv
405 	 * and key) in order to avoid allocation contention.  This will reserve
406 	 * at most 10 SB entries, leaving 40 SB entries available for dynamic
407 	 * allocation.
408 	 *
409 	 * The v5 CCP Local Storage Block (LSB) is broken up into 8
410 	 * memrory ranges, each of which can be enabled for access by one
411 	 * or more queues. Device initialization takes this into account,
412 	 * and attempts to assign one region for exclusive use by each
413 	 * available queue; the rest are then aggregated as "public" use.
414 	 * If there are fewer regions than queues, all regions are shared
415 	 * amongst all queues.
416 	 */
417 	struct mutex sb_mutex ____cacheline_aligned;
418 	DECLARE_BITMAP(sb, KSB_COUNT);
419 	wait_queue_head_t sb_queue;
420 	unsigned int sb_avail;
421 	unsigned int sb_count;
422 	u32 sb_start;
423 
424 	/* Bitmap of shared LSBs, if any */
425 	DECLARE_BITMAP(lsbmap, SLSB_MAP_SIZE);
426 
427 	/* Suspend support */
428 	unsigned int suspending;
429 	wait_queue_head_t suspend_queue;
430 
431 	/* DMA caching attribute support */
432 	unsigned int axcache;
433 
434 	/* Device Statistics */
435 	unsigned long total_interrupts;
436 
437 	/* DebugFS info */
438 	struct dentry *debugfs_instance;
439 };
440 
441 enum ccp_memtype {
442 	CCP_MEMTYPE_SYSTEM = 0,
443 	CCP_MEMTYPE_SB,
444 	CCP_MEMTYPE_LOCAL,
445 	CCP_MEMTYPE__LAST,
446 };
447 #define	CCP_MEMTYPE_LSB	CCP_MEMTYPE_KSB
448 
449 
450 struct ccp_dma_info {
451 	dma_addr_t address;
452 	unsigned int offset;
453 	unsigned int length;
454 	enum dma_data_direction dir;
455 } __packed __aligned(4);
456 
457 struct ccp_dm_workarea {
458 	struct device *dev;
459 	struct dma_pool *dma_pool;
460 
461 	u8 *address;
462 	struct ccp_dma_info dma;
463 	unsigned int length;
464 };
465 
466 struct ccp_sg_workarea {
467 	struct scatterlist *sg;
468 	int nents;
469 	unsigned int sg_used;
470 
471 	struct scatterlist *dma_sg;
472 	struct device *dma_dev;
473 	unsigned int dma_count;
474 	enum dma_data_direction dma_dir;
475 
476 	u64 bytes_left;
477 };
478 
479 struct ccp_data {
480 	struct ccp_sg_workarea sg_wa;
481 	struct ccp_dm_workarea dm_wa;
482 };
483 
484 struct ccp_mem {
485 	enum ccp_memtype type;
486 	union {
487 		struct ccp_dma_info dma;
488 		u32 sb;
489 	} u;
490 };
491 
492 struct ccp_aes_op {
493 	enum ccp_aes_type type;
494 	enum ccp_aes_mode mode;
495 	enum ccp_aes_action action;
496 	unsigned int size;
497 };
498 
499 struct ccp_xts_aes_op {
500 	enum ccp_aes_action action;
501 	enum ccp_xts_aes_unit_size unit_size;
502 };
503 
504 struct ccp_des3_op {
505 	enum ccp_des3_type type;
506 	enum ccp_des3_mode mode;
507 	enum ccp_des3_action action;
508 };
509 
510 struct ccp_sha_op {
511 	enum ccp_sha_type type;
512 	u64 msg_bits;
513 };
514 
515 struct ccp_rsa_op {
516 	u32 mod_size;
517 	u32 input_len;
518 };
519 
520 struct ccp_passthru_op {
521 	enum ccp_passthru_bitwise bit_mod;
522 	enum ccp_passthru_byteswap byte_swap;
523 };
524 
525 struct ccp_ecc_op {
526 	enum ccp_ecc_function function;
527 };
528 
529 struct ccp_op {
530 	struct ccp_cmd_queue *cmd_q;
531 
532 	u32 jobid;
533 	u32 ioc;
534 	u32 soc;
535 	u32 sb_key;
536 	u32 sb_ctx;
537 	u32 init;
538 	u32 eom;
539 
540 	struct ccp_mem src;
541 	struct ccp_mem dst;
542 	struct ccp_mem exp;
543 
544 	union {
545 		struct ccp_aes_op aes;
546 		struct ccp_xts_aes_op xts;
547 		struct ccp_des3_op des3;
548 		struct ccp_sha_op sha;
549 		struct ccp_rsa_op rsa;
550 		struct ccp_passthru_op passthru;
551 		struct ccp_ecc_op ecc;
552 	} u;
553 };
554 
555 static inline u32 ccp_addr_lo(struct ccp_dma_info *info)
556 {
557 	return lower_32_bits(info->address + info->offset);
558 }
559 
560 static inline u32 ccp_addr_hi(struct ccp_dma_info *info)
561 {
562 	return upper_32_bits(info->address + info->offset) & 0x0000ffff;
563 }
564 
565 /**
566  * descriptor for version 5 CPP commands
567  * 8 32-bit words:
568  * word 0: function; engine; control bits
569  * word 1: length of source data
570  * word 2: low 32 bits of source pointer
571  * word 3: upper 16 bits of source pointer; source memory type
572  * word 4: low 32 bits of destination pointer
573  * word 5: upper 16 bits of destination pointer; destination memory type
574  * word 6: low 32 bits of key pointer
575  * word 7: upper 16 bits of key pointer; key memory type
576  */
577 struct dword0 {
578 	unsigned int soc:1;
579 	unsigned int ioc:1;
580 	unsigned int rsvd1:1;
581 	unsigned int init:1;
582 	unsigned int eom:1;		/* AES/SHA only */
583 	unsigned int function:15;
584 	unsigned int engine:4;
585 	unsigned int prot:1;
586 	unsigned int rsvd2:7;
587 };
588 
589 struct dword3 {
590 	unsigned int  src_hi:16;
591 	unsigned int  src_mem:2;
592 	unsigned int  lsb_cxt_id:8;
593 	unsigned int  rsvd1:5;
594 	unsigned int  fixed:1;
595 };
596 
597 union dword4 {
598 	__le32 dst_lo;		/* NON-SHA	*/
599 	__le32 sha_len_lo;	/* SHA		*/
600 };
601 
602 union dword5 {
603 	struct {
604 		unsigned int  dst_hi:16;
605 		unsigned int  dst_mem:2;
606 		unsigned int  rsvd1:13;
607 		unsigned int  fixed:1;
608 	} fields;
609 	__le32 sha_len_hi;
610 };
611 
612 struct dword7 {
613 	unsigned int  key_hi:16;
614 	unsigned int  key_mem:2;
615 	unsigned int  rsvd1:14;
616 };
617 
618 struct ccp5_desc {
619 	struct dword0 dw0;
620 	__le32 length;
621 	__le32 src_lo;
622 	struct dword3 dw3;
623 	union dword4 dw4;
624 	union dword5 dw5;
625 	__le32 key_lo;
626 	struct dword7 dw7;
627 };
628 
629 int ccp_pci_init(void);
630 void ccp_pci_exit(void);
631 
632 int ccp_platform_init(void);
633 void ccp_platform_exit(void);
634 
635 void ccp_add_device(struct ccp_device *ccp);
636 void ccp_del_device(struct ccp_device *ccp);
637 
638 extern void ccp_log_error(struct ccp_device *, int);
639 
640 struct ccp_device *ccp_alloc_struct(struct device *dev);
641 bool ccp_queues_suspended(struct ccp_device *ccp);
642 int ccp_cmd_queue_thread(void *data);
643 int ccp_trng_read(struct hwrng *rng, void *data, size_t max, bool wait);
644 
645 int ccp_run_cmd(struct ccp_cmd_queue *cmd_q, struct ccp_cmd *cmd);
646 
647 int ccp_register_rng(struct ccp_device *ccp);
648 void ccp_unregister_rng(struct ccp_device *ccp);
649 int ccp_dmaengine_register(struct ccp_device *ccp);
650 void ccp_dmaengine_unregister(struct ccp_device *ccp);
651 
652 void ccp5_debugfs_setup(struct ccp_device *ccp);
653 void ccp5_debugfs_destroy(void);
654 
655 /* Structure for computation functions that are device-specific */
656 struct ccp_actions {
657 	int (*aes)(struct ccp_op *);
658 	int (*xts_aes)(struct ccp_op *);
659 	int (*des3)(struct ccp_op *);
660 	int (*sha)(struct ccp_op *);
661 	int (*rsa)(struct ccp_op *);
662 	int (*passthru)(struct ccp_op *);
663 	int (*ecc)(struct ccp_op *);
664 	u32 (*sballoc)(struct ccp_cmd_queue *, unsigned int);
665 	void (*sbfree)(struct ccp_cmd_queue *, unsigned int, unsigned int);
666 	unsigned int (*get_free_slots)(struct ccp_cmd_queue *);
667 	int (*init)(struct ccp_device *);
668 	void (*destroy)(struct ccp_device *);
669 	irqreturn_t (*irqhandler)(int, void *);
670 };
671 
672 /* Structure to hold CCP version-specific values */
673 struct ccp_vdata {
674 	const unsigned int version;
675 	const unsigned int dma_chan_attr;
676 	void (*setup)(struct ccp_device *);
677 	const struct ccp_actions *perform;
678 	const unsigned int bar;
679 	const unsigned int offset;
680 };
681 
682 extern const struct ccp_vdata ccpv3;
683 extern const struct ccp_vdata ccpv5a;
684 extern const struct ccp_vdata ccpv5b;
685 
686 #endif
687