1 /* 2 * AMD Cryptographic Coprocessor (CCP) driver 3 * 4 * Copyright (C) 2013,2016 Advanced Micro Devices, Inc. 5 * 6 * Author: Tom Lendacky <thomas.lendacky@amd.com> 7 * Author: Gary R Hook <gary.hook@amd.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14 #ifndef __CCP_DEV_H__ 15 #define __CCP_DEV_H__ 16 17 #include <linux/device.h> 18 #include <linux/pci.h> 19 #include <linux/spinlock.h> 20 #include <linux/mutex.h> 21 #include <linux/list.h> 22 #include <linux/wait.h> 23 #include <linux/dmapool.h> 24 #include <linux/hw_random.h> 25 #include <linux/bitops.h> 26 #include <linux/interrupt.h> 27 #include <linux/irqreturn.h> 28 #include <linux/dmaengine.h> 29 30 #define MAX_CCP_NAME_LEN 16 31 #define MAX_DMAPOOL_NAME_LEN 32 32 33 #define MAX_HW_QUEUES 5 34 #define MAX_CMD_QLEN 100 35 36 #define TRNG_RETRIES 10 37 38 #define CACHE_NONE 0x00 39 #define CACHE_WB_NO_ALLOC 0xb7 40 41 /****** Register Mappings ******/ 42 #define Q_MASK_REG 0x000 43 #define TRNG_OUT_REG 0x00c 44 #define IRQ_MASK_REG 0x040 45 #define IRQ_STATUS_REG 0x200 46 47 #define DEL_CMD_Q_JOB 0x124 48 #define DEL_Q_ACTIVE 0x00000200 49 #define DEL_Q_ID_SHIFT 6 50 51 #define CMD_REQ0 0x180 52 #define CMD_REQ_INCR 0x04 53 54 #define CMD_Q_STATUS_BASE 0x210 55 #define CMD_Q_INT_STATUS_BASE 0x214 56 #define CMD_Q_STATUS_INCR 0x20 57 58 #define CMD_Q_CACHE_BASE 0x228 59 #define CMD_Q_CACHE_INC 0x20 60 61 #define CMD_Q_ERROR(__qs) ((__qs) & 0x0000003f) 62 #define CMD_Q_DEPTH(__qs) (((__qs) >> 12) & 0x0000000f) 63 64 /* ------------------------ CCP Version 5 Specifics ------------------------ */ 65 #define CMD5_QUEUE_MASK_OFFSET 0x00 66 #define CMD5_QUEUE_PRIO_OFFSET 0x04 67 #define CMD5_REQID_CONFIG_OFFSET 0x08 68 #define CMD5_CMD_TIMEOUT_OFFSET 0x10 69 #define LSB_PUBLIC_MASK_LO_OFFSET 0x18 70 #define LSB_PUBLIC_MASK_HI_OFFSET 0x1C 71 #define LSB_PRIVATE_MASK_LO_OFFSET 0x20 72 #define LSB_PRIVATE_MASK_HI_OFFSET 0x24 73 74 #define CMD5_Q_CONTROL_BASE 0x0000 75 #define CMD5_Q_TAIL_LO_BASE 0x0004 76 #define CMD5_Q_HEAD_LO_BASE 0x0008 77 #define CMD5_Q_INT_ENABLE_BASE 0x000C 78 #define CMD5_Q_INTERRUPT_STATUS_BASE 0x0010 79 80 #define CMD5_Q_STATUS_BASE 0x0100 81 #define CMD5_Q_INT_STATUS_BASE 0x0104 82 #define CMD5_Q_DMA_STATUS_BASE 0x0108 83 #define CMD5_Q_DMA_READ_STATUS_BASE 0x010C 84 #define CMD5_Q_DMA_WRITE_STATUS_BASE 0x0110 85 #define CMD5_Q_ABORT_BASE 0x0114 86 #define CMD5_Q_AX_CACHE_BASE 0x0118 87 88 #define CMD5_CONFIG_0_OFFSET 0x6000 89 #define CMD5_TRNG_CTL_OFFSET 0x6008 90 #define CMD5_AES_MASK_OFFSET 0x6010 91 #define CMD5_CLK_GATE_CTL_OFFSET 0x603C 92 93 /* Address offset between two virtual queue registers */ 94 #define CMD5_Q_STATUS_INCR 0x1000 95 96 /* Bit masks */ 97 #define CMD5_Q_RUN 0x1 98 #define CMD5_Q_HALT 0x2 99 #define CMD5_Q_MEM_LOCATION 0x4 100 #define CMD5_Q_SIZE 0x1F 101 #define CMD5_Q_SHIFT 3 102 #define COMMANDS_PER_QUEUE 16 103 #define QUEUE_SIZE_VAL ((ffs(COMMANDS_PER_QUEUE) - 2) & \ 104 CMD5_Q_SIZE) 105 #define Q_PTR_MASK (2 << (QUEUE_SIZE_VAL + 5) - 1) 106 #define Q_DESC_SIZE sizeof(struct ccp5_desc) 107 #define Q_SIZE(n) (COMMANDS_PER_QUEUE*(n)) 108 109 #define INT_COMPLETION 0x1 110 #define INT_ERROR 0x2 111 #define INT_QUEUE_STOPPED 0x4 112 #define INT_EMPTY_QUEUE 0x8 113 #define SUPPORTED_INTERRUPTS (INT_COMPLETION | INT_ERROR) 114 115 #define LSB_REGION_WIDTH 5 116 #define MAX_LSB_CNT 8 117 118 #define LSB_SIZE 16 119 #define LSB_ITEM_SIZE 32 120 #define PLSB_MAP_SIZE (LSB_SIZE) 121 #define SLSB_MAP_SIZE (MAX_LSB_CNT * LSB_SIZE) 122 123 #define LSB_ENTRY_NUMBER(LSB_ADDR) (LSB_ADDR / LSB_ITEM_SIZE) 124 125 /* ------------------------ CCP Version 3 Specifics ------------------------ */ 126 #define REQ0_WAIT_FOR_WRITE 0x00000004 127 #define REQ0_INT_ON_COMPLETE 0x00000002 128 #define REQ0_STOP_ON_COMPLETE 0x00000001 129 130 #define REQ0_CMD_Q_SHIFT 9 131 #define REQ0_JOBID_SHIFT 3 132 133 /****** REQ1 Related Values ******/ 134 #define REQ1_PROTECT_SHIFT 27 135 #define REQ1_ENGINE_SHIFT 23 136 #define REQ1_KEY_KSB_SHIFT 2 137 138 #define REQ1_EOM 0x00000002 139 #define REQ1_INIT 0x00000001 140 141 /* AES Related Values */ 142 #define REQ1_AES_TYPE_SHIFT 21 143 #define REQ1_AES_MODE_SHIFT 18 144 #define REQ1_AES_ACTION_SHIFT 17 145 #define REQ1_AES_CFB_SIZE_SHIFT 10 146 147 /* XTS-AES Related Values */ 148 #define REQ1_XTS_AES_SIZE_SHIFT 10 149 150 /* SHA Related Values */ 151 #define REQ1_SHA_TYPE_SHIFT 21 152 153 /* RSA Related Values */ 154 #define REQ1_RSA_MOD_SIZE_SHIFT 10 155 156 /* Pass-Through Related Values */ 157 #define REQ1_PT_BW_SHIFT 12 158 #define REQ1_PT_BS_SHIFT 10 159 160 /* ECC Related Values */ 161 #define REQ1_ECC_AFFINE_CONVERT 0x00200000 162 #define REQ1_ECC_FUNCTION_SHIFT 18 163 164 /****** REQ4 Related Values ******/ 165 #define REQ4_KSB_SHIFT 18 166 #define REQ4_MEMTYPE_SHIFT 16 167 168 /****** REQ6 Related Values ******/ 169 #define REQ6_MEMTYPE_SHIFT 16 170 171 /****** Key Storage Block ******/ 172 #define KSB_START 77 173 #define KSB_END 127 174 #define KSB_COUNT (KSB_END - KSB_START + 1) 175 #define CCP_SB_BITS 256 176 177 #define CCP_JOBID_MASK 0x0000003f 178 179 /* ------------------------ General CCP Defines ------------------------ */ 180 181 #define CCP_DMA_DFLT 0x0 182 #define CCP_DMA_PRIV 0x1 183 #define CCP_DMA_PUB 0x2 184 185 #define CCP_DMAPOOL_MAX_SIZE 64 186 #define CCP_DMAPOOL_ALIGN BIT(5) 187 188 #define CCP_REVERSE_BUF_SIZE 64 189 190 #define CCP_AES_KEY_SB_COUNT 1 191 #define CCP_AES_CTX_SB_COUNT 1 192 193 #define CCP_XTS_AES_KEY_SB_COUNT 1 194 #define CCP_XTS_AES_CTX_SB_COUNT 1 195 196 #define CCP_DES3_KEY_SB_COUNT 1 197 #define CCP_DES3_CTX_SB_COUNT 1 198 199 #define CCP_SHA_SB_COUNT 1 200 201 #define CCP_RSA_MAX_WIDTH 4096 202 203 #define CCP_PASSTHRU_BLOCKSIZE 256 204 #define CCP_PASSTHRU_MASKSIZE 32 205 #define CCP_PASSTHRU_SB_COUNT 1 206 207 #define CCP_ECC_MODULUS_BYTES 48 /* 384-bits */ 208 #define CCP_ECC_MAX_OPERANDS 6 209 #define CCP_ECC_MAX_OUTPUTS 3 210 #define CCP_ECC_SRC_BUF_SIZE 448 211 #define CCP_ECC_DST_BUF_SIZE 192 212 #define CCP_ECC_OPERAND_SIZE 64 213 #define CCP_ECC_OUTPUT_SIZE 64 214 #define CCP_ECC_RESULT_OFFSET 60 215 #define CCP_ECC_RESULT_SUCCESS 0x0001 216 217 #define CCP_SB_BYTES 32 218 219 struct ccp_op; 220 struct ccp_device; 221 struct ccp_cmd; 222 struct ccp_fns; 223 224 struct ccp_dma_cmd { 225 struct list_head entry; 226 227 struct ccp_cmd ccp_cmd; 228 }; 229 230 struct ccp_dma_desc { 231 struct list_head entry; 232 233 struct ccp_device *ccp; 234 235 struct list_head pending; 236 struct list_head active; 237 238 enum dma_status status; 239 struct dma_async_tx_descriptor tx_desc; 240 size_t len; 241 }; 242 243 struct ccp_dma_chan { 244 struct ccp_device *ccp; 245 246 spinlock_t lock; 247 struct list_head created; 248 struct list_head pending; 249 struct list_head active; 250 struct list_head complete; 251 252 struct tasklet_struct cleanup_tasklet; 253 254 enum dma_status status; 255 struct dma_chan dma_chan; 256 }; 257 258 struct ccp_cmd_queue { 259 struct ccp_device *ccp; 260 261 /* Queue identifier */ 262 u32 id; 263 264 /* Queue dma pool */ 265 struct dma_pool *dma_pool; 266 267 /* Queue base address (not neccessarily aligned)*/ 268 struct ccp5_desc *qbase; 269 270 /* Aligned queue start address (per requirement) */ 271 struct mutex q_mutex ____cacheline_aligned; 272 unsigned int qidx; 273 274 /* Version 5 has different requirements for queue memory */ 275 unsigned int qsize; 276 dma_addr_t qbase_dma; 277 dma_addr_t qdma_tail; 278 279 /* Per-queue reserved storage block(s) */ 280 u32 sb_key; 281 u32 sb_ctx; 282 283 /* Bitmap of LSBs that can be accessed by this queue */ 284 DECLARE_BITMAP(lsbmask, MAX_LSB_CNT); 285 /* Private LSB that is assigned to this queue, or -1 if none. 286 * Bitmap for my private LSB, unused otherwise 287 */ 288 int lsb; 289 DECLARE_BITMAP(lsbmap, PLSB_MAP_SIZE); 290 291 /* Queue processing thread */ 292 struct task_struct *kthread; 293 unsigned int active; 294 unsigned int suspended; 295 296 /* Number of free command slots available */ 297 unsigned int free_slots; 298 299 /* Interrupt masks */ 300 u32 int_ok; 301 u32 int_err; 302 303 /* Register addresses for queue */ 304 void __iomem *reg_control; 305 void __iomem *reg_tail_lo; 306 void __iomem *reg_head_lo; 307 void __iomem *reg_int_enable; 308 void __iomem *reg_interrupt_status; 309 void __iomem *reg_status; 310 void __iomem *reg_int_status; 311 void __iomem *reg_dma_status; 312 void __iomem *reg_dma_read_status; 313 void __iomem *reg_dma_write_status; 314 u32 qcontrol; /* Cached control register */ 315 316 /* Status values from job */ 317 u32 int_status; 318 u32 q_status; 319 u32 q_int_status; 320 u32 cmd_error; 321 322 /* Interrupt wait queue */ 323 wait_queue_head_t int_queue; 324 unsigned int int_rcvd; 325 } ____cacheline_aligned; 326 327 struct ccp_device { 328 struct list_head entry; 329 330 struct ccp_vdata *vdata; 331 unsigned int ord; 332 char name[MAX_CCP_NAME_LEN]; 333 char rngname[MAX_CCP_NAME_LEN]; 334 335 struct device *dev; 336 337 /* Bus specific device information 338 */ 339 void *dev_specific; 340 int (*get_irq)(struct ccp_device *ccp); 341 void (*free_irq)(struct ccp_device *ccp); 342 unsigned int qim; 343 unsigned int irq; 344 bool use_tasklet; 345 struct tasklet_struct irq_tasklet; 346 347 /* I/O area used for device communication. The register mapping 348 * starts at an offset into the mapped bar. 349 * The CMD_REQx registers and the Delete_Cmd_Queue_Job register 350 * need to be protected while a command queue thread is accessing 351 * them. 352 */ 353 struct mutex req_mutex ____cacheline_aligned; 354 void __iomem *io_map; 355 void __iomem *io_regs; 356 357 /* Master lists that all cmds are queued on. Because there can be 358 * more than one CCP command queue that can process a cmd a separate 359 * backlog list is neeeded so that the backlog completion call 360 * completes before the cmd is available for execution. 361 */ 362 spinlock_t cmd_lock ____cacheline_aligned; 363 unsigned int cmd_count; 364 struct list_head cmd; 365 struct list_head backlog; 366 367 /* The command queues. These represent the queues available on the 368 * CCP that are available for processing cmds 369 */ 370 struct ccp_cmd_queue cmd_q[MAX_HW_QUEUES]; 371 unsigned int cmd_q_count; 372 373 /* Support for the CCP True RNG 374 */ 375 struct hwrng hwrng; 376 unsigned int hwrng_retries; 377 378 /* Support for the CCP DMA capabilities 379 */ 380 struct dma_device dma_dev; 381 struct ccp_dma_chan *ccp_dma_chan; 382 struct kmem_cache *dma_cmd_cache; 383 struct kmem_cache *dma_desc_cache; 384 385 /* A counter used to generate job-ids for cmds submitted to the CCP 386 */ 387 atomic_t current_id ____cacheline_aligned; 388 389 /* The v3 CCP uses key storage blocks (SB) to maintain context for 390 * certain operations. To prevent multiple cmds from using the same 391 * SB range a command queue reserves an SB range for the duration of 392 * the cmd. Each queue, will however, reserve 2 SB blocks for 393 * operations that only require single SB entries (eg. AES context/iv 394 * and key) in order to avoid allocation contention. This will reserve 395 * at most 10 SB entries, leaving 40 SB entries available for dynamic 396 * allocation. 397 * 398 * The v5 CCP Local Storage Block (LSB) is broken up into 8 399 * memrory ranges, each of which can be enabled for access by one 400 * or more queues. Device initialization takes this into account, 401 * and attempts to assign one region for exclusive use by each 402 * available queue; the rest are then aggregated as "public" use. 403 * If there are fewer regions than queues, all regions are shared 404 * amongst all queues. 405 */ 406 struct mutex sb_mutex ____cacheline_aligned; 407 DECLARE_BITMAP(sb, KSB_COUNT); 408 wait_queue_head_t sb_queue; 409 unsigned int sb_avail; 410 unsigned int sb_count; 411 u32 sb_start; 412 413 /* Bitmap of shared LSBs, if any */ 414 DECLARE_BITMAP(lsbmap, SLSB_MAP_SIZE); 415 416 /* Suspend support */ 417 unsigned int suspending; 418 wait_queue_head_t suspend_queue; 419 420 /* DMA caching attribute support */ 421 unsigned int axcache; 422 }; 423 424 enum ccp_memtype { 425 CCP_MEMTYPE_SYSTEM = 0, 426 CCP_MEMTYPE_SB, 427 CCP_MEMTYPE_LOCAL, 428 CCP_MEMTYPE__LAST, 429 }; 430 #define CCP_MEMTYPE_LSB CCP_MEMTYPE_KSB 431 432 433 struct ccp_dma_info { 434 dma_addr_t address; 435 unsigned int offset; 436 unsigned int length; 437 enum dma_data_direction dir; 438 } __packed __aligned(4); 439 440 struct ccp_dm_workarea { 441 struct device *dev; 442 struct dma_pool *dma_pool; 443 444 u8 *address; 445 struct ccp_dma_info dma; 446 unsigned int length; 447 }; 448 449 struct ccp_sg_workarea { 450 struct scatterlist *sg; 451 int nents; 452 unsigned int sg_used; 453 454 struct scatterlist *dma_sg; 455 struct device *dma_dev; 456 unsigned int dma_count; 457 enum dma_data_direction dma_dir; 458 459 u64 bytes_left; 460 }; 461 462 struct ccp_data { 463 struct ccp_sg_workarea sg_wa; 464 struct ccp_dm_workarea dm_wa; 465 }; 466 467 struct ccp_mem { 468 enum ccp_memtype type; 469 union { 470 struct ccp_dma_info dma; 471 u32 sb; 472 } u; 473 }; 474 475 struct ccp_aes_op { 476 enum ccp_aes_type type; 477 enum ccp_aes_mode mode; 478 enum ccp_aes_action action; 479 unsigned int size; 480 }; 481 482 struct ccp_xts_aes_op { 483 enum ccp_aes_action action; 484 enum ccp_xts_aes_unit_size unit_size; 485 }; 486 487 struct ccp_des3_op { 488 enum ccp_des3_type type; 489 enum ccp_des3_mode mode; 490 enum ccp_des3_action action; 491 }; 492 493 struct ccp_sha_op { 494 enum ccp_sha_type type; 495 u64 msg_bits; 496 }; 497 498 struct ccp_rsa_op { 499 u32 mod_size; 500 u32 input_len; 501 }; 502 503 struct ccp_passthru_op { 504 enum ccp_passthru_bitwise bit_mod; 505 enum ccp_passthru_byteswap byte_swap; 506 }; 507 508 struct ccp_ecc_op { 509 enum ccp_ecc_function function; 510 }; 511 512 struct ccp_op { 513 struct ccp_cmd_queue *cmd_q; 514 515 u32 jobid; 516 u32 ioc; 517 u32 soc; 518 u32 sb_key; 519 u32 sb_ctx; 520 u32 init; 521 u32 eom; 522 523 struct ccp_mem src; 524 struct ccp_mem dst; 525 struct ccp_mem exp; 526 527 union { 528 struct ccp_aes_op aes; 529 struct ccp_xts_aes_op xts; 530 struct ccp_des3_op des3; 531 struct ccp_sha_op sha; 532 struct ccp_rsa_op rsa; 533 struct ccp_passthru_op passthru; 534 struct ccp_ecc_op ecc; 535 } u; 536 }; 537 538 static inline u32 ccp_addr_lo(struct ccp_dma_info *info) 539 { 540 return lower_32_bits(info->address + info->offset); 541 } 542 543 static inline u32 ccp_addr_hi(struct ccp_dma_info *info) 544 { 545 return upper_32_bits(info->address + info->offset) & 0x0000ffff; 546 } 547 548 /** 549 * descriptor for version 5 CPP commands 550 * 8 32-bit words: 551 * word 0: function; engine; control bits 552 * word 1: length of source data 553 * word 2: low 32 bits of source pointer 554 * word 3: upper 16 bits of source pointer; source memory type 555 * word 4: low 32 bits of destination pointer 556 * word 5: upper 16 bits of destination pointer; destination memory type 557 * word 6: low 32 bits of key pointer 558 * word 7: upper 16 bits of key pointer; key memory type 559 */ 560 struct dword0 { 561 unsigned int soc:1; 562 unsigned int ioc:1; 563 unsigned int rsvd1:1; 564 unsigned int init:1; 565 unsigned int eom:1; /* AES/SHA only */ 566 unsigned int function:15; 567 unsigned int engine:4; 568 unsigned int prot:1; 569 unsigned int rsvd2:7; 570 }; 571 572 struct dword3 { 573 unsigned int src_hi:16; 574 unsigned int src_mem:2; 575 unsigned int lsb_cxt_id:8; 576 unsigned int rsvd1:5; 577 unsigned int fixed:1; 578 }; 579 580 union dword4 { 581 __le32 dst_lo; /* NON-SHA */ 582 __le32 sha_len_lo; /* SHA */ 583 }; 584 585 union dword5 { 586 struct { 587 unsigned int dst_hi:16; 588 unsigned int dst_mem:2; 589 unsigned int rsvd1:13; 590 unsigned int fixed:1; 591 } fields; 592 __le32 sha_len_hi; 593 }; 594 595 struct dword7 { 596 unsigned int key_hi:16; 597 unsigned int key_mem:2; 598 unsigned int rsvd1:14; 599 }; 600 601 struct ccp5_desc { 602 struct dword0 dw0; 603 __le32 length; 604 __le32 src_lo; 605 struct dword3 dw3; 606 union dword4 dw4; 607 union dword5 dw5; 608 __le32 key_lo; 609 struct dword7 dw7; 610 }; 611 612 int ccp_pci_init(void); 613 void ccp_pci_exit(void); 614 615 int ccp_platform_init(void); 616 void ccp_platform_exit(void); 617 618 void ccp_add_device(struct ccp_device *ccp); 619 void ccp_del_device(struct ccp_device *ccp); 620 621 extern void ccp_log_error(struct ccp_device *, int); 622 623 struct ccp_device *ccp_alloc_struct(struct device *dev); 624 bool ccp_queues_suspended(struct ccp_device *ccp); 625 int ccp_cmd_queue_thread(void *data); 626 int ccp_trng_read(struct hwrng *rng, void *data, size_t max, bool wait); 627 628 int ccp_run_cmd(struct ccp_cmd_queue *cmd_q, struct ccp_cmd *cmd); 629 630 int ccp_register_rng(struct ccp_device *ccp); 631 void ccp_unregister_rng(struct ccp_device *ccp); 632 int ccp_dmaengine_register(struct ccp_device *ccp); 633 void ccp_dmaengine_unregister(struct ccp_device *ccp); 634 635 /* Structure for computation functions that are device-specific */ 636 struct ccp_actions { 637 int (*aes)(struct ccp_op *); 638 int (*xts_aes)(struct ccp_op *); 639 int (*des3)(struct ccp_op *); 640 int (*sha)(struct ccp_op *); 641 int (*rsa)(struct ccp_op *); 642 int (*passthru)(struct ccp_op *); 643 int (*ecc)(struct ccp_op *); 644 u32 (*sballoc)(struct ccp_cmd_queue *, unsigned int); 645 void (*sbfree)(struct ccp_cmd_queue *, unsigned int, unsigned int); 646 unsigned int (*get_free_slots)(struct ccp_cmd_queue *); 647 int (*init)(struct ccp_device *); 648 void (*destroy)(struct ccp_device *); 649 irqreturn_t (*irqhandler)(int, void *); 650 }; 651 652 /* Structure to hold CCP version-specific values */ 653 struct ccp_vdata { 654 const unsigned int version; 655 const unsigned int dma_chan_attr; 656 void (*setup)(struct ccp_device *); 657 const struct ccp_actions *perform; 658 const unsigned int bar; 659 const unsigned int offset; 660 }; 661 662 extern const struct ccp_vdata ccpv3; 663 extern const struct ccp_vdata ccpv5a; 664 extern const struct ccp_vdata ccpv5b; 665 666 #endif 667