1 #ifndef __NITROX_DEV_H 2 #define __NITROX_DEV_H 3 4 #include <linux/dma-mapping.h> 5 #include <linux/interrupt.h> 6 #include <linux/pci.h> 7 8 #define VERSION_LEN 32 9 10 struct nitrox_cmdq { 11 /* command queue lock */ 12 spinlock_t cmdq_lock; 13 /* response list lock */ 14 spinlock_t response_lock; 15 /* backlog list lock */ 16 spinlock_t backlog_lock; 17 18 /* request submitted to chip, in progress */ 19 struct list_head response_head; 20 /* hw queue full, hold in backlog list */ 21 struct list_head backlog_head; 22 23 /* doorbell address */ 24 u8 __iomem *dbell_csr_addr; 25 /* base address of the queue */ 26 u8 *head; 27 28 struct nitrox_device *ndev; 29 /* flush pending backlog commands */ 30 struct work_struct backlog_qflush; 31 32 /* requests posted waiting for completion */ 33 atomic_t pending_count; 34 /* requests in backlog queues */ 35 atomic_t backlog_count; 36 37 /* command size 32B/64B */ 38 u8 instr_size; 39 u8 qno; 40 u32 qsize; 41 42 /* unaligned addresses */ 43 u8 *head_unaligned; 44 dma_addr_t dma_unaligned; 45 /* dma address of the base */ 46 dma_addr_t dma; 47 }; 48 49 struct nitrox_hw { 50 /* firmware version */ 51 char fw_name[VERSION_LEN]; 52 53 u16 vendor_id; 54 u16 device_id; 55 u8 revision_id; 56 57 /* CNN55XX cores */ 58 u8 se_cores; 59 u8 ae_cores; 60 u8 zip_cores; 61 }; 62 63 #define MAX_MSIX_VECTOR_NAME 20 64 /** 65 * vectors for queues (64 AE, 64 SE and 64 ZIP) and 66 * error condition/mailbox. 67 */ 68 #define MAX_MSIX_VECTORS 192 69 70 struct nitrox_msix { 71 struct msix_entry *entries; 72 char **names; 73 DECLARE_BITMAP(irqs, MAX_MSIX_VECTORS); 74 u32 nr_entries; 75 }; 76 77 struct bh_data { 78 /* slc port completion count address */ 79 u8 __iomem *completion_cnt_csr_addr; 80 81 struct nitrox_cmdq *cmdq; 82 struct tasklet_struct resp_handler; 83 }; 84 85 struct nitrox_bh { 86 struct bh_data *slc; 87 }; 88 89 /* NITROX-5 driver state */ 90 #define NITROX_UCODE_LOADED 0 91 #define NITROX_READY 1 92 93 /* command queue size */ 94 #define DEFAULT_CMD_QLEN 2048 95 /* command timeout in milliseconds */ 96 #define CMD_TIMEOUT 2000 97 98 #define DEV(ndev) ((struct device *)(&(ndev)->pdev->dev)) 99 #define PF_MODE 0 100 101 #define NITROX_CSR_ADDR(ndev, offset) \ 102 ((ndev)->bar_addr + (offset)) 103 104 /** 105 * struct nitrox_device - NITROX Device Information. 106 * @list: pointer to linked list of devices 107 * @bar_addr: iomap address 108 * @pdev: PCI device information 109 * @status: NITROX status 110 * @timeout: Request timeout in jiffies 111 * @refcnt: Device usage count 112 * @idx: device index (0..N) 113 * @node: NUMA node id attached 114 * @qlen: Command queue length 115 * @nr_queues: Number of command queues 116 * @ctx_pool: DMA pool for crypto context 117 * @pkt_cmdqs: SE Command queues 118 * @msix: MSI-X information 119 * @bh: post processing work 120 * @hw: hardware information 121 * @debugfs_dir: debugfs directory 122 */ 123 struct nitrox_device { 124 struct list_head list; 125 126 u8 __iomem *bar_addr; 127 struct pci_dev *pdev; 128 129 unsigned long status; 130 unsigned long timeout; 131 refcount_t refcnt; 132 133 u8 idx; 134 int node; 135 u16 qlen; 136 u16 nr_queues; 137 138 struct dma_pool *ctx_pool; 139 struct nitrox_cmdq *pkt_cmdqs; 140 141 struct nitrox_msix msix; 142 struct nitrox_bh bh; 143 144 struct nitrox_hw hw; 145 #if IS_ENABLED(CONFIG_DEBUG_FS) 146 struct dentry *debugfs_dir; 147 #endif 148 }; 149 150 /** 151 * nitrox_read_csr - Read from device register 152 * @ndev: NITROX device 153 * @offset: offset of the register to read 154 * 155 * Returns: value read 156 */ 157 static inline u64 nitrox_read_csr(struct nitrox_device *ndev, u64 offset) 158 { 159 return readq(ndev->bar_addr + offset); 160 } 161 162 /** 163 * nitrox_write_csr - Write to device register 164 * @ndev: NITROX device 165 * @offset: offset of the register to write 166 * @value: value to write 167 */ 168 static inline void nitrox_write_csr(struct nitrox_device *ndev, u64 offset, 169 u64 value) 170 { 171 writeq(value, (ndev->bar_addr + offset)); 172 } 173 174 static inline int nitrox_ready(struct nitrox_device *ndev) 175 { 176 return test_bit(NITROX_READY, &ndev->status); 177 } 178 179 #endif /* __NITROX_DEV_H */ 180