1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __NITROX_DEV_H 3 #define __NITROX_DEV_H 4 5 #include <linux/dma-mapping.h> 6 #include <linux/interrupt.h> 7 #include <linux/pci.h> 8 #include <linux/if.h> 9 10 #define VERSION_LEN 32 11 12 /** 13 * struct nitrox_cmdq - NITROX command queue 14 * @cmd_qlock: command queue lock 15 * @resp_qlock: response queue lock 16 * @backlog_qlock: backlog queue lock 17 * @ndev: NITROX device 18 * @response_head: submitted request list 19 * @backlog_head: backlog queue 20 * @dbell_csr_addr: doorbell register address for this queue 21 * @compl_cnt_csr_addr: completion count register address of the slc port 22 * @base: command queue base address 23 * @dma: dma address of the base 24 * @pending_count: request pending at device 25 * @backlog_count: backlog request count 26 * @write_idx: next write index for the command 27 * @instr_size: command size 28 * @qno: command queue number 29 * @qsize: command queue size 30 * @unalign_base: unaligned base address 31 * @unalign_dma: unaligned dma address 32 */ 33 struct nitrox_cmdq { 34 spinlock_t cmd_qlock; 35 spinlock_t resp_qlock; 36 spinlock_t backlog_qlock; 37 38 struct nitrox_device *ndev; 39 struct list_head response_head; 40 struct list_head backlog_head; 41 42 u8 __iomem *dbell_csr_addr; 43 u8 __iomem *compl_cnt_csr_addr; 44 u8 *base; 45 dma_addr_t dma; 46 47 struct work_struct backlog_qflush; 48 49 atomic_t pending_count; 50 atomic_t backlog_count; 51 52 int write_idx; 53 u8 instr_size; 54 u8 qno; 55 u32 qsize; 56 57 u8 *unalign_base; 58 dma_addr_t unalign_dma; 59 }; 60 61 /** 62 * struct nitrox_hw - NITROX hardware information 63 * @partname: partname ex: CNN55xxx-xxx 64 * @fw_name: firmware version 65 * @freq: NITROX frequency 66 * @vendor_id: vendor ID 67 * @device_id: device ID 68 * @revision_id: revision ID 69 * @se_cores: number of symmetric cores 70 * @ae_cores: number of asymmetric cores 71 * @zip_cores: number of zip cores 72 */ 73 struct nitrox_hw { 74 char partname[IFNAMSIZ * 2]; 75 char fw_name[VERSION_LEN]; 76 77 int freq; 78 u16 vendor_id; 79 u16 device_id; 80 u8 revision_id; 81 82 u8 se_cores; 83 u8 ae_cores; 84 u8 zip_cores; 85 }; 86 87 struct nitrox_stats { 88 atomic64_t posted; 89 atomic64_t completed; 90 atomic64_t dropped; 91 }; 92 93 #define IRQ_NAMESZ 32 94 95 struct nitrox_q_vector { 96 char name[IRQ_NAMESZ]; 97 bool valid; 98 int ring; 99 struct tasklet_struct resp_tasklet; 100 union { 101 struct nitrox_cmdq *cmdq; 102 struct nitrox_device *ndev; 103 }; 104 }; 105 106 /* 107 * NITROX Device states 108 */ 109 enum ndev_state { 110 __NDEV_NOT_READY, 111 __NDEV_READY, 112 __NDEV_IN_RESET, 113 }; 114 115 /* NITROX support modes for VF(s) */ 116 enum vf_mode { 117 __NDEV_MODE_PF, 118 __NDEV_MODE_VF16, 119 __NDEV_MODE_VF32, 120 __NDEV_MODE_VF64, 121 __NDEV_MODE_VF128, 122 }; 123 124 #define __NDEV_SRIOV_BIT 0 125 126 /* command queue size */ 127 #define DEFAULT_CMD_QLEN 2048 128 /* command timeout in milliseconds */ 129 #define CMD_TIMEOUT 2000 130 131 #define DEV(ndev) ((struct device *)(&(ndev)->pdev->dev)) 132 133 #define NITROX_CSR_ADDR(ndev, offset) \ 134 ((ndev)->bar_addr + (offset)) 135 136 /** 137 * struct nitrox_device - NITROX Device Information. 138 * @list: pointer to linked list of devices 139 * @bar_addr: iomap address 140 * @pdev: PCI device information 141 * @state: NITROX device state 142 * @flags: flags to indicate device the features 143 * @timeout: Request timeout in jiffies 144 * @refcnt: Device usage count 145 * @idx: device index (0..N) 146 * @node: NUMA node id attached 147 * @qlen: Command queue length 148 * @nr_queues: Number of command queues 149 * @mode: Device mode PF/VF 150 * @ctx_pool: DMA pool for crypto context 151 * @pkt_inq: Packet input rings 152 * @qvec: MSI-X queue vectors information 153 * @hw: hardware information 154 * @debugfs_dir: debugfs directory 155 */ 156 struct nitrox_device { 157 struct list_head list; 158 159 u8 __iomem *bar_addr; 160 struct pci_dev *pdev; 161 162 atomic_t state; 163 unsigned long flags; 164 unsigned long timeout; 165 refcount_t refcnt; 166 167 u8 idx; 168 int node; 169 u16 qlen; 170 u16 nr_queues; 171 int num_vfs; 172 enum vf_mode mode; 173 174 struct dma_pool *ctx_pool; 175 struct nitrox_cmdq *pkt_inq; 176 177 struct nitrox_q_vector *qvec; 178 int num_vecs; 179 180 struct nitrox_stats stats; 181 struct nitrox_hw hw; 182 #if IS_ENABLED(CONFIG_DEBUG_FS) 183 struct dentry *debugfs_dir; 184 #endif 185 }; 186 187 /** 188 * nitrox_read_csr - Read from device register 189 * @ndev: NITROX device 190 * @offset: offset of the register to read 191 * 192 * Returns: value read 193 */ 194 static inline u64 nitrox_read_csr(struct nitrox_device *ndev, u64 offset) 195 { 196 return readq(ndev->bar_addr + offset); 197 } 198 199 /** 200 * nitrox_write_csr - Write to device register 201 * @ndev: NITROX device 202 * @offset: offset of the register to write 203 * @value: value to write 204 */ 205 static inline void nitrox_write_csr(struct nitrox_device *ndev, u64 offset, 206 u64 value) 207 { 208 writeq(value, (ndev->bar_addr + offset)); 209 } 210 211 static inline bool nitrox_ready(struct nitrox_device *ndev) 212 { 213 return atomic_read(&ndev->state) == __NDEV_READY; 214 } 215 216 #ifdef CONFIG_DEBUG_FS 217 int nitrox_debugfs_init(struct nitrox_device *ndev); 218 void nitrox_debugfs_exit(struct nitrox_device *ndev); 219 #else 220 static inline int nitrox_debugfs_init(struct nitrox_device *ndev) 221 { 222 return 0; 223 } 224 225 static inline void nitrox_debugfs_exit(struct nitrox_device *ndev) 226 { } 227 #endif 228 229 #endif /* __NITROX_DEV_H */ 230