1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __NITROX_CSR_H 3 #define __NITROX_CSR_H 4 5 #include <asm/byteorder.h> 6 #include <linux/types.h> 7 8 /* EMU clusters */ 9 #define NR_CLUSTERS 4 10 /* Maximum cores per cluster, 11 * varies based on partname 12 */ 13 #define AE_CORES_PER_CLUSTER 20 14 #define SE_CORES_PER_CLUSTER 16 15 16 #define AE_MAX_CORES (AE_CORES_PER_CLUSTER * NR_CLUSTERS) 17 #define SE_MAX_CORES (SE_CORES_PER_CLUSTER * NR_CLUSTERS) 18 #define ZIP_MAX_CORES 5 19 20 /* BIST registers */ 21 #define EMU_BIST_STATUSX(_i) (0x1402700 + ((_i) * 0x40000)) 22 #define UCD_BIST_STATUS 0x12C0070 23 #define NPS_CORE_BIST_REG 0x10000E8 24 #define NPS_CORE_NPC_BIST_REG 0x1000128 25 #define NPS_PKT_SLC_BIST_REG 0x1040088 26 #define NPS_PKT_IN_BIST_REG 0x1040100 27 #define POM_BIST_REG 0x11C0100 28 #define BMI_BIST_REG 0x1140080 29 #define EFL_CORE_BIST_REGX(_i) (0x1240100 + ((_i) * 0x400)) 30 #define EFL_TOP_BIST_STAT 0x1241090 31 #define BMO_BIST_REG 0x1180080 32 #define LBC_BIST_STATUS 0x1200020 33 #define PEM_BIST_STATUSX(_i) (0x1080468 | ((_i) << 18)) 34 35 /* EMU registers */ 36 #define EMU_SE_ENABLEX(_i) (0x1400000 + ((_i) * 0x40000)) 37 #define EMU_AE_ENABLEX(_i) (0x1400008 + ((_i) * 0x40000)) 38 #define EMU_WD_INT_ENA_W1SX(_i) (0x1402318 + ((_i) * 0x40000)) 39 #define EMU_GE_INT_ENA_W1SX(_i) (0x1402518 + ((_i) * 0x40000)) 40 #define EMU_FUSE_MAPX(_i) (0x1402708 + ((_i) * 0x40000)) 41 42 /* UCD registers */ 43 #define UCD_UCODE_LOAD_BLOCK_NUM 0x12C0010 44 #define UCD_UCODE_LOAD_IDX_DATAX(_i) (0x12C0018 + ((_i) * 0x20)) 45 #define UCD_SE_EID_UCODE_BLOCK_NUMX(_i) (0x12C0000 + ((_i) * 0x1000)) 46 47 /* NPS core registers */ 48 #define NPS_CORE_GBL_VFCFG 0x1000000 49 #define NPS_CORE_CONTROL 0x1000008 50 #define NPS_CORE_INT_ACTIVE 0x1000080 51 #define NPS_CORE_INT 0x10000A0 52 #define NPS_CORE_INT_ENA_W1S 0x10000B8 53 #define NPS_STATS_PKT_DMA_RD_CNT 0x1000180 54 #define NPS_STATS_PKT_DMA_WR_CNT 0x1000190 55 56 /* NPS packet registers */ 57 #define NPS_PKT_INT 0x1040018 58 #define NPS_PKT_IN_RERR_HI 0x1040108 59 #define NPS_PKT_IN_RERR_HI_ENA_W1S 0x1040120 60 #define NPS_PKT_IN_RERR_LO 0x1040128 61 #define NPS_PKT_IN_RERR_LO_ENA_W1S 0x1040140 62 #define NPS_PKT_IN_ERR_TYPE 0x1040148 63 #define NPS_PKT_IN_ERR_TYPE_ENA_W1S 0x1040160 64 #define NPS_PKT_IN_INSTR_CTLX(_i) (0x10060 + ((_i) * 0x40000)) 65 #define NPS_PKT_IN_INSTR_BADDRX(_i) (0x10068 + ((_i) * 0x40000)) 66 #define NPS_PKT_IN_INSTR_RSIZEX(_i) (0x10070 + ((_i) * 0x40000)) 67 #define NPS_PKT_IN_DONE_CNTSX(_i) (0x10080 + ((_i) * 0x40000)) 68 #define NPS_PKT_IN_INSTR_BAOFF_DBELLX(_i) (0x10078 + ((_i) * 0x40000)) 69 #define NPS_PKT_IN_INT_LEVELSX(_i) (0x10088 + ((_i) * 0x40000)) 70 71 #define NPS_PKT_SLC_RERR_HI 0x1040208 72 #define NPS_PKT_SLC_RERR_HI_ENA_W1S 0x1040220 73 #define NPS_PKT_SLC_RERR_LO 0x1040228 74 #define NPS_PKT_SLC_RERR_LO_ENA_W1S 0x1040240 75 #define NPS_PKT_SLC_ERR_TYPE 0x1040248 76 #define NPS_PKT_SLC_ERR_TYPE_ENA_W1S 0x1040260 77 #define NPS_PKT_SLC_CTLX(_i) (0x10000 + ((_i) * 0x40000)) 78 #define NPS_PKT_SLC_CNTSX(_i) (0x10008 + ((_i) * 0x40000)) 79 #define NPS_PKT_SLC_INT_LEVELSX(_i) (0x10010 + ((_i) * 0x40000)) 80 81 /* POM registers */ 82 #define POM_INT_ENA_W1S 0x11C0018 83 #define POM_GRP_EXECMASKX(_i) (0x11C1100 | ((_i) * 8)) 84 #define POM_INT 0x11C0000 85 #define POM_PERF_CTL 0x11CC400 86 87 /* BMI registers */ 88 #define BMI_INT 0x1140000 89 #define BMI_CTL 0x1140020 90 #define BMI_INT_ENA_W1S 0x1140018 91 #define BMI_NPS_PKT_CNT 0x1140070 92 93 /* EFL registers */ 94 #define EFL_CORE_INT_ENA_W1SX(_i) (0x1240018 + ((_i) * 0x400)) 95 #define EFL_CORE_VF_ERR_INT0X(_i) (0x1240050 + ((_i) * 0x400)) 96 #define EFL_CORE_VF_ERR_INT0_ENA_W1SX(_i) (0x1240068 + ((_i) * 0x400)) 97 #define EFL_CORE_VF_ERR_INT1X(_i) (0x1240070 + ((_i) * 0x400)) 98 #define EFL_CORE_VF_ERR_INT1_ENA_W1SX(_i) (0x1240088 + ((_i) * 0x400)) 99 #define EFL_CORE_SE_ERR_INTX(_i) (0x12400A0 + ((_i) * 0x400)) 100 #define EFL_RNM_CTL_STATUS 0x1241800 101 #define EFL_CORE_INTX(_i) (0x1240000 + ((_i) * 0x400)) 102 103 /* BMO registers */ 104 #define BMO_CTL2 0x1180028 105 #define BMO_NPS_SLC_PKT_CNT 0x1180078 106 107 /* LBC registers */ 108 #define LBC_INT 0x1200000 109 #define LBC_INVAL_CTL 0x1201010 110 #define LBC_PLM_VF1_64_INT 0x1202008 111 #define LBC_INVAL_STATUS 0x1202010 112 #define LBC_INT_ENA_W1S 0x1203000 113 #define LBC_PLM_VF1_64_INT_ENA_W1S 0x1205008 114 #define LBC_PLM_VF65_128_INT 0x1206008 115 #define LBC_ELM_VF1_64_INT 0x1208000 116 #define LBC_PLM_VF65_128_INT_ENA_W1S 0x1209008 117 #define LBC_ELM_VF1_64_INT_ENA_W1S 0x120B000 118 #define LBC_ELM_VF65_128_INT 0x120C000 119 #define LBC_ELM_VF65_128_INT_ENA_W1S 0x120F000 120 121 #define RST_BOOT 0x10C1600 122 #define FUS_DAT1 0x10C1408 123 124 /* PEM registers */ 125 #define PEM0_INT 0x1080428 126 127 /** 128 * struct emu_fuse_map - EMU Fuse Map Registers 129 * @ae_fuse: Fuse settings for AE 19..0 130 * @se_fuse: Fuse settings for SE 15..0 131 * 132 * A set bit indicates the unit is fuse disabled. 133 */ 134 union emu_fuse_map { 135 u64 value; 136 struct { 137 #if (defined(__BIG_ENDIAN_BITFIELD)) 138 u64 valid : 1; 139 u64 raz_52_62 : 11; 140 u64 ae_fuse : 20; 141 u64 raz_16_31 : 16; 142 u64 se_fuse : 16; 143 #else 144 u64 se_fuse : 16; 145 u64 raz_16_31 : 16; 146 u64 ae_fuse : 20; 147 u64 raz_52_62 : 11; 148 u64 valid : 1; 149 #endif 150 } s; 151 }; 152 153 /** 154 * struct emu_se_enable - Symmetric Engine Enable Registers 155 * @enable: Individual enables for each of the clusters 156 * 16 symmetric engines. 157 */ 158 union emu_se_enable { 159 u64 value; 160 struct { 161 #if (defined(__BIG_ENDIAN_BITFIELD)) 162 u64 raz : 48; 163 u64 enable : 16; 164 #else 165 u64 enable : 16; 166 u64 raz : 48; 167 #endif 168 } s; 169 }; 170 171 /** 172 * struct emu_ae_enable - EMU Asymmetric engines. 173 * @enable: Individual enables for each of the cluster's 174 * 20 Asymmetric Engines. 175 */ 176 union emu_ae_enable { 177 u64 value; 178 struct { 179 #if (defined(__BIG_ENDIAN_BITFIELD)) 180 u64 raz : 44; 181 u64 enable : 20; 182 #else 183 u64 enable : 20; 184 u64 raz : 44; 185 #endif 186 } s; 187 }; 188 189 /** 190 * struct emu_wd_int_ena_w1s - EMU Interrupt Enable Registers 191 * @ae_wd: Reads or sets enable for EMU(0..3)_WD_INT[AE_WD] 192 * @se_wd: Reads or sets enable for EMU(0..3)_WD_INT[SE_WD] 193 */ 194 union emu_wd_int_ena_w1s { 195 u64 value; 196 struct { 197 #if (defined(__BIG_ENDIAN_BITFIELD)) 198 u64 raz2 : 12; 199 u64 ae_wd : 20; 200 u64 raz1 : 16; 201 u64 se_wd : 16; 202 #else 203 u64 se_wd : 16; 204 u64 raz1 : 16; 205 u64 ae_wd : 20; 206 u64 raz2 : 12; 207 #endif 208 } s; 209 }; 210 211 /** 212 * struct emu_ge_int_ena_w1s - EMU Interrupt Enable set registers 213 * @ae_ge: Reads or sets enable for EMU(0..3)_GE_INT[AE_GE] 214 * @se_ge: Reads or sets enable for EMU(0..3)_GE_INT[SE_GE] 215 */ 216 union emu_ge_int_ena_w1s { 217 u64 value; 218 struct { 219 #if (defined(__BIG_ENDIAN_BITFIELD)) 220 u64 raz_52_63 : 12; 221 u64 ae_ge : 20; 222 u64 raz_16_31: 16; 223 u64 se_ge : 16; 224 #else 225 u64 se_ge : 16; 226 u64 raz_16_31: 16; 227 u64 ae_ge : 20; 228 u64 raz_52_63 : 12; 229 #endif 230 } s; 231 }; 232 233 /** 234 * struct nps_pkt_slc_ctl - Solicited Packet Out Control Registers 235 * @rh: Indicates whether to remove or include the response header 236 * 1 = Include, 0 = Remove 237 * @z: If set, 8 trailing 0x00 bytes will be added to the end of the 238 * outgoing packet. 239 * @enb: Enable for this port. 240 */ 241 union nps_pkt_slc_ctl { 242 u64 value; 243 struct { 244 #if defined(__BIG_ENDIAN_BITFIELD) 245 u64 raz : 61; 246 u64 rh : 1; 247 u64 z : 1; 248 u64 enb : 1; 249 #else 250 u64 enb : 1; 251 u64 z : 1; 252 u64 rh : 1; 253 u64 raz : 61; 254 #endif 255 } s; 256 }; 257 258 /** 259 * struct nps_pkt_slc_cnts - Solicited Packet Out Count Registers 260 * @slc_int: Returns a 1 when: 261 * NPS_PKT_SLC(i)_CNTS[CNT] > NPS_PKT_SLC(i)_INT_LEVELS[CNT], or 262 * NPS_PKT_SLC(i)_CNTS[TIMER] > NPS_PKT_SLC(i)_INT_LEVELS[TIMET]. 263 * To clear the bit, the CNTS register must be written to clear. 264 * @in_int: Returns a 1 when: 265 * NPS_PKT_IN(i)_DONE_CNTS[CNT] > NPS_PKT_IN(i)_INT_LEVELS[CNT]. 266 * To clear the bit, the DONE_CNTS register must be written to clear. 267 * @mbox_int: Returns a 1 when: 268 * NPS_PKT_MBOX_PF_VF(i)_INT[INTR] is set. To clear the bit, 269 * write NPS_PKT_MBOX_PF_VF(i)_INT[INTR] with 1. 270 * @timer: Timer, incremented every 2048 coprocessor clock cycles 271 * when [CNT] is not zero. The hardware clears both [TIMER] and 272 * [INT] when [CNT] goes to 0. 273 * @cnt: Packet counter. Hardware adds to [CNT] as it sends packets out. 274 * On a write to this CSR, hardware subtracts the amount written to the 275 * [CNT] field from [CNT]. 276 */ 277 union nps_pkt_slc_cnts { 278 u64 value; 279 struct { 280 #if defined(__BIG_ENDIAN_BITFIELD) 281 u64 slc_int : 1; 282 u64 uns_int : 1; 283 u64 in_int : 1; 284 u64 mbox_int : 1; 285 u64 resend : 1; 286 u64 raz : 5; 287 u64 timer : 22; 288 u64 cnt : 32; 289 #else 290 u64 cnt : 32; 291 u64 timer : 22; 292 u64 raz : 5; 293 u64 resend : 1; 294 u64 mbox_int : 1; 295 u64 in_int : 1; 296 u64 uns_int : 1; 297 u64 slc_int : 1; 298 #endif 299 } s; 300 }; 301 302 /** 303 * struct nps_pkt_slc_int_levels - Solicited Packet Out Interrupt Levels 304 * Registers. 305 * @bmode: Determines whether NPS_PKT_SLC_CNTS[CNT] is a byte or 306 * packet counter. 307 * @timet: Output port counter time interrupt threshold. 308 * @cnt: Output port counter interrupt threshold. 309 */ 310 union nps_pkt_slc_int_levels { 311 u64 value; 312 struct { 313 #if defined(__BIG_ENDIAN_BITFIELD) 314 u64 bmode : 1; 315 u64 raz : 9; 316 u64 timet : 22; 317 u64 cnt : 32; 318 #else 319 u64 cnt : 32; 320 u64 timet : 22; 321 u64 raz : 9; 322 u64 bmode : 1; 323 #endif 324 } s; 325 }; 326 327 /** 328 * struct nps_pkt_inst - NPS Packet Interrupt Register 329 * @in_err: Set when any NPS_PKT_IN_RERR_HI/LO bit and 330 * corresponding NPS_PKT_IN_RERR_*_ENA_* bit are bot set. 331 * @uns_err: Set when any NSP_PKT_UNS_RERR_HI/LO bit and 332 * corresponding NPS_PKT_UNS_RERR_*_ENA_* bit are both set. 333 * @slc_er: Set when any NSP_PKT_SLC_RERR_HI/LO bit and 334 * corresponding NPS_PKT_SLC_RERR_*_ENA_* bit are both set. 335 */ 336 union nps_pkt_int { 337 u64 value; 338 struct { 339 #if defined(__BIG_ENDIAN_BITFIELD) 340 u64 raz : 54; 341 u64 uns_wto : 1; 342 u64 in_err : 1; 343 u64 uns_err : 1; 344 u64 slc_err : 1; 345 u64 in_dbe : 1; 346 u64 in_sbe : 1; 347 u64 uns_dbe : 1; 348 u64 uns_sbe : 1; 349 u64 slc_dbe : 1; 350 u64 slc_sbe : 1; 351 #else 352 u64 slc_sbe : 1; 353 u64 slc_dbe : 1; 354 u64 uns_sbe : 1; 355 u64 uns_dbe : 1; 356 u64 in_sbe : 1; 357 u64 in_dbe : 1; 358 u64 slc_err : 1; 359 u64 uns_err : 1; 360 u64 in_err : 1; 361 u64 uns_wto : 1; 362 u64 raz : 54; 363 #endif 364 } s; 365 }; 366 367 /** 368 * struct nps_pkt_in_done_cnts - Input instruction ring counts registers 369 * @slc_cnt: Returns a 1 when: 370 * NPS_PKT_SLC(i)_CNTS[CNT] > NPS_PKT_SLC(i)_INT_LEVELS[CNT], or 371 * NPS_PKT_SLC(i)_CNTS[TIMER] > NPS_PKT_SCL(i)_INT_LEVELS[TIMET] 372 * To clear the bit, the CNTS register must be 373 * written to clear the underlying condition 374 * @uns_int: Return a 1 when: 375 * NPS_PKT_UNS(i)_CNTS[CNT] > NPS_PKT_UNS(i)_INT_LEVELS[CNT], or 376 * NPS_PKT_UNS(i)_CNTS[TIMER] > NPS_PKT_UNS(i)_INT_LEVELS[TIMET] 377 * To clear the bit, the CNTS register must be 378 * written to clear the underlying condition 379 * @in_int: Returns a 1 when: 380 * NPS_PKT_IN(i)_DONE_CNTS[CNT] > NPS_PKT_IN(i)_INT_LEVELS[CNT] 381 * To clear the bit, the DONE_CNTS register 382 * must be written to clear the underlying condition 383 * @mbox_int: Returns a 1 when: 384 * NPS_PKT_MBOX_PF_VF(i)_INT[INTR] is set. 385 * To clear the bit, write NPS_PKT_MBOX_PF_VF(i)_INT[INTR] 386 * with 1. 387 * @resend: A write of 1 will resend an MSI-X interrupt message if any 388 * of the following conditions are true for this ring "i". 389 * NPS_PKT_SLC(i)_CNTS[CNT] > NPS_PKT_SLC(i)_INT_LEVELS[CNT] 390 * NPS_PKT_SLC(i)_CNTS[TIMER] > NPS_PKT_SLC(i)_INT_LEVELS[TIMET] 391 * NPS_PKT_UNS(i)_CNTS[CNT] > NPS_PKT_UNS(i)_INT_LEVELS[CNT] 392 * NPS_PKT_UNS(i)_CNTS[TIMER] > NPS_PKT_UNS(i)_INT_LEVELS[TIMET] 393 * NPS_PKT_IN(i)_DONE_CNTS[CNT] > NPS_PKT_IN(i)_INT_LEVELS[CNT] 394 * NPS_PKT_MBOX_PF_VF(i)_INT[INTR] is set 395 * @cnt: Packet counter. Hardware adds to [CNT] as it reads 396 * packets. On a write to this CSR, hardware substracts the 397 * amount written to the [CNT] field from [CNT], which will 398 * clear PKT_IN(i)_INT_STATUS[INTR] if [CNT] becomes <= 399 * NPS_PKT_IN(i)_INT_LEVELS[CNT]. This register should be 400 * cleared before enabling a ring by reading the current 401 * value and writing it back. 402 */ 403 union nps_pkt_in_done_cnts { 404 u64 value; 405 struct { 406 #if defined(__BIG_ENDIAN_BITFIELD) 407 u64 slc_int : 1; 408 u64 uns_int : 1; 409 u64 in_int : 1; 410 u64 mbox_int : 1; 411 u64 resend : 1; 412 u64 raz : 27; 413 u64 cnt : 32; 414 #else 415 u64 cnt : 32; 416 u64 raz : 27; 417 u64 resend : 1; 418 u64 mbox_int : 1; 419 u64 in_int : 1; 420 u64 uns_int : 1; 421 u64 slc_int : 1; 422 #endif 423 } s; 424 }; 425 426 /** 427 * struct nps_pkt_in_instr_ctl - Input Instruction Ring Control Registers. 428 * @is64b: If 1, the ring uses 64-byte instructions. If 0, the 429 * ring uses 32-byte instructions. 430 * @enb: Enable for the input ring. 431 */ 432 union nps_pkt_in_instr_ctl { 433 u64 value; 434 struct { 435 #if (defined(__BIG_ENDIAN_BITFIELD)) 436 u64 raz : 62; 437 u64 is64b : 1; 438 u64 enb : 1; 439 #else 440 u64 enb : 1; 441 u64 is64b : 1; 442 u64 raz : 62; 443 #endif 444 } s; 445 }; 446 447 /** 448 * struct nps_pkt_in_instr_rsize - Input instruction ring size registers 449 * @rsize: Ring size (number of instructions) 450 */ 451 union nps_pkt_in_instr_rsize { 452 u64 value; 453 struct { 454 #if (defined(__BIG_ENDIAN_BITFIELD)) 455 u64 raz : 32; 456 u64 rsize : 32; 457 #else 458 u64 rsize : 32; 459 u64 raz : 32; 460 #endif 461 } s; 462 }; 463 464 /** 465 * struct nps_pkt_in_instr_baoff_dbell - Input instruction ring 466 * base address offset and doorbell registers 467 * @aoff: Address offset. The offset from the NPS_PKT_IN_INSTR_BADDR 468 * where the next pointer is read. 469 * @dbell: Pointer list doorbell count. Write operations to this field 470 * increments the present value here. Read operations return the 471 * present value. 472 */ 473 union nps_pkt_in_instr_baoff_dbell { 474 u64 value; 475 struct { 476 #if (defined(__BIG_ENDIAN_BITFIELD)) 477 u64 aoff : 32; 478 u64 dbell : 32; 479 #else 480 u64 dbell : 32; 481 u64 aoff : 32; 482 #endif 483 } s; 484 }; 485 486 /** 487 * struct nps_core_int_ena_w1s - NPS core interrupt enable set register 488 * @host_nps_wr_err: Reads or sets enable for 489 * NPS_CORE_INT[HOST_NPS_WR_ERR]. 490 * @npco_dma_malform: Reads or sets enable for 491 * NPS_CORE_INT[NPCO_DMA_MALFORM]. 492 * @exec_wr_timeout: Reads or sets enable for 493 * NPS_CORE_INT[EXEC_WR_TIMEOUT]. 494 * @host_wr_timeout: Reads or sets enable for 495 * NPS_CORE_INT[HOST_WR_TIMEOUT]. 496 * @host_wr_err: Reads or sets enable for 497 * NPS_CORE_INT[HOST_WR_ERR] 498 */ 499 union nps_core_int_ena_w1s { 500 u64 value; 501 struct { 502 #if (defined(__BIG_ENDIAN_BITFIELD)) 503 u64 raz4 : 55; 504 u64 host_nps_wr_err : 1; 505 u64 npco_dma_malform : 1; 506 u64 exec_wr_timeout : 1; 507 u64 host_wr_timeout : 1; 508 u64 host_wr_err : 1; 509 u64 raz3 : 1; 510 u64 raz2 : 1; 511 u64 raz1 : 1; 512 u64 raz0 : 1; 513 #else 514 u64 raz0 : 1; 515 u64 raz1 : 1; 516 u64 raz2 : 1; 517 u64 raz3 : 1; 518 u64 host_wr_err : 1; 519 u64 host_wr_timeout : 1; 520 u64 exec_wr_timeout : 1; 521 u64 npco_dma_malform : 1; 522 u64 host_nps_wr_err : 1; 523 u64 raz4 : 55; 524 #endif 525 } s; 526 }; 527 528 /** 529 * struct nps_core_gbl_vfcfg - Global VF Configuration Register. 530 * @ilk_disable: When set, this bit indicates that the ILK interface has 531 * been disabled. 532 * @obaf: BMO allocation control 533 * 0 = allocate per queue 534 * 1 = allocate per VF 535 * @ibaf: BMI allocation control 536 * 0 = allocate per queue 537 * 1 = allocate per VF 538 * @zaf: ZIP allocation control 539 * 0 = allocate per queue 540 * 1 = allocate per VF 541 * @aeaf: AE allocation control 542 * 0 = allocate per queue 543 * 1 = allocate per VF 544 * @seaf: SE allocation control 545 * 0 = allocation per queue 546 * 1 = allocate per VF 547 * @cfg: VF/PF mode. 548 */ 549 union nps_core_gbl_vfcfg { 550 u64 value; 551 struct { 552 #if (defined(__BIG_ENDIAN_BITFIELD)) 553 u64 raz :55; 554 u64 ilk_disable :1; 555 u64 obaf :1; 556 u64 ibaf :1; 557 u64 zaf :1; 558 u64 aeaf :1; 559 u64 seaf :1; 560 u64 cfg :3; 561 #else 562 u64 cfg :3; 563 u64 seaf :1; 564 u64 aeaf :1; 565 u64 zaf :1; 566 u64 ibaf :1; 567 u64 obaf :1; 568 u64 ilk_disable :1; 569 u64 raz :55; 570 #endif 571 } s; 572 }; 573 574 /** 575 * struct nps_core_int_active - NPS Core Interrupt Active Register 576 * @resend: Resend MSI-X interrupt if needs to handle interrupts 577 * Sofware can set this bit and then exit the ISR. 578 * @ocla: Set when any OCLA(0)_INT and corresponding OCLA(0_INT_ENA_W1C 579 * bit are set 580 * @mbox: Set when any NPS_PKT_MBOX_INT_LO/HI and corresponding 581 * NPS_PKT_MBOX_INT_LO_ENA_W1C/HI_ENA_W1C bits are set 582 * @emu: bit i is set in [EMU] when any EMU(i)_INT bit is set 583 * @bmo: Set when any BMO_INT bit is set 584 * @bmi: Set when any BMI_INT bit is set or when any non-RO 585 * BMI_INT and corresponding BMI_INT_ENA_W1C bits are both set 586 * @aqm: Set when any AQM_INT bit is set 587 * @zqm: Set when any ZQM_INT bit is set 588 * @efl: Set when any EFL_INT RO bit is set or when any non-RO EFL_INT 589 * and corresponding EFL_INT_ENA_W1C bits are both set 590 * @ilk: Set when any ILK_INT bit is set 591 * @lbc: Set when any LBC_INT RO bit is set or when any non-RO LBC_INT 592 * and corresponding LBC_INT_ENA_W1C bits are bot set 593 * @pem: Set when any PEM(0)_INT RO bit is set or when any non-RO 594 * PEM(0)_INT and corresponding PEM(0)_INT_ENA_W1C bit are both set 595 * @ucd: Set when any UCD_INT bit is set 596 * @zctl: Set when any ZIP_INT RO bit is set or when any non-RO ZIP_INT 597 * and corresponding ZIP_INT_ENA_W1C bits are both set 598 * @lbm: Set when any LBM_INT bit is set 599 * @nps_pkt: Set when any NPS_PKT_INT bit is set 600 * @nps_core: Set when any NPS_CORE_INT RO bit is set or when non-RO 601 * NPS_CORE_INT and corresponding NSP_CORE_INT_ENA_W1C bits are both set 602 */ 603 union nps_core_int_active { 604 u64 value; 605 struct { 606 #if (defined(__BIG_ENDIAN_BITFIELD)) 607 u64 resend : 1; 608 u64 raz : 43; 609 u64 ocla : 1; 610 u64 mbox : 1; 611 u64 emu : 4; 612 u64 bmo : 1; 613 u64 bmi : 1; 614 u64 aqm : 1; 615 u64 zqm : 1; 616 u64 efl : 1; 617 u64 ilk : 1; 618 u64 lbc : 1; 619 u64 pem : 1; 620 u64 pom : 1; 621 u64 ucd : 1; 622 u64 zctl : 1; 623 u64 lbm : 1; 624 u64 nps_pkt : 1; 625 u64 nps_core : 1; 626 #else 627 u64 nps_core : 1; 628 u64 nps_pkt : 1; 629 u64 lbm : 1; 630 u64 zctl: 1; 631 u64 ucd : 1; 632 u64 pom : 1; 633 u64 pem : 1; 634 u64 lbc : 1; 635 u64 ilk : 1; 636 u64 efl : 1; 637 u64 zqm : 1; 638 u64 aqm : 1; 639 u64 bmi : 1; 640 u64 bmo : 1; 641 u64 emu : 4; 642 u64 mbox : 1; 643 u64 ocla : 1; 644 u64 raz : 43; 645 u64 resend : 1; 646 #endif 647 } s; 648 }; 649 650 /** 651 * struct efl_core_int - EFL Interrupt Registers 652 * @epci_decode_err: EPCI decoded a transacation that was unknown 653 * This error should only occurred when there is a micrcode/SE error 654 * and should be considered fatal 655 * @ae_err: An AE uncorrectable error occurred. 656 * See EFL_CORE(0..3)_AE_ERR_INT 657 * @se_err: An SE uncorrectable error occurred. 658 * See EFL_CORE(0..3)_SE_ERR_INT 659 * @dbe: Double-bit error occurred in EFL 660 * @sbe: Single-bit error occurred in EFL 661 * @d_left: Asserted when new POM-Header-BMI-data is 662 * being sent to an Exec, and that Exec has Not read all BMI 663 * data associated with the previous POM header 664 * @len_ovr: Asserted when an Exec-Read is issued that is more than 665 * 14 greater in length that the BMI data left to be read 666 */ 667 union efl_core_int { 668 u64 value; 669 struct { 670 #if (defined(__BIG_ENDIAN_BITFIELD)) 671 u64 raz : 57; 672 u64 epci_decode_err : 1; 673 u64 ae_err : 1; 674 u64 se_err : 1; 675 u64 dbe : 1; 676 u64 sbe : 1; 677 u64 d_left : 1; 678 u64 len_ovr : 1; 679 #else 680 u64 len_ovr : 1; 681 u64 d_left : 1; 682 u64 sbe : 1; 683 u64 dbe : 1; 684 u64 se_err : 1; 685 u64 ae_err : 1; 686 u64 epci_decode_err : 1; 687 u64 raz : 57; 688 #endif 689 } s; 690 }; 691 692 /** 693 * struct efl_core_int_ena_w1s - EFL core interrupt enable set register 694 * @epci_decode_err: Reads or sets enable for 695 * EFL_CORE(0..3)_INT[EPCI_DECODE_ERR]. 696 * @d_left: Reads or sets enable for 697 * EFL_CORE(0..3)_INT[D_LEFT]. 698 * @len_ovr: Reads or sets enable for 699 * EFL_CORE(0..3)_INT[LEN_OVR]. 700 */ 701 union efl_core_int_ena_w1s { 702 u64 value; 703 struct { 704 #if (defined(__BIG_ENDIAN_BITFIELD)) 705 u64 raz_7_63 : 57; 706 u64 epci_decode_err : 1; 707 u64 raz_2_5 : 4; 708 u64 d_left : 1; 709 u64 len_ovr : 1; 710 #else 711 u64 len_ovr : 1; 712 u64 d_left : 1; 713 u64 raz_2_5 : 4; 714 u64 epci_decode_err : 1; 715 u64 raz_7_63 : 57; 716 #endif 717 } s; 718 }; 719 720 /** 721 * struct efl_rnm_ctl_status - RNM Control and Status Register 722 * @ent_sel: Select input to RNM FIFO 723 * @exp_ent: Exported entropy enable for random number generator 724 * @rng_rst: Reset to RNG. Setting this bit to 1 cancels the generation 725 * of the current random number. 726 * @rnm_rst: Reset the RNM. Setting this bit to 1 clears all sorted numbers 727 * in the random number memory. 728 * @rng_en: Enabled the output of the RNG. 729 * @ent_en: Entropy enable for random number generator. 730 */ 731 union efl_rnm_ctl_status { 732 u64 value; 733 struct { 734 #if (defined(__BIG_ENDIAN_BITFIELD)) 735 u64 raz_9_63 : 55; 736 u64 ent_sel : 4; 737 u64 exp_ent : 1; 738 u64 rng_rst : 1; 739 u64 rnm_rst : 1; 740 u64 rng_en : 1; 741 u64 ent_en : 1; 742 #else 743 u64 ent_en : 1; 744 u64 rng_en : 1; 745 u64 rnm_rst : 1; 746 u64 rng_rst : 1; 747 u64 exp_ent : 1; 748 u64 ent_sel : 4; 749 u64 raz_9_63 : 55; 750 #endif 751 } s; 752 }; 753 754 /** 755 * struct bmi_ctl - BMI control register 756 * @ilk_hdrq_thrsh: Maximum number of header queue locations 757 * that ILK packets may consume. When the threshold is 758 * exceeded ILK_XOFF is sent to the BMI_X2P_ARB. 759 * @nps_hdrq_thrsh: Maximum number of header queue locations 760 * that NPS packets may consume. When the threshold is 761 * exceeded NPS_XOFF is sent to the BMI_X2P_ARB. 762 * @totl_hdrq_thrsh: Maximum number of header queue locations 763 * that the sum of ILK and NPS packets may consume. 764 * @ilk_free_thrsh: Maximum number of buffers that ILK packet 765 * flows may consume before ILK_XOFF is sent to the BMI_X2P_ARB. 766 * @nps_free_thrsh: Maximum number of buffers that NPS packet 767 * flows may consume before NPS XOFF is sent to the BMI_X2p_ARB. 768 * @totl_free_thrsh: Maximum number of buffers that bot ILK and NPS 769 * packet flows may consume before both NPS_XOFF and ILK_XOFF 770 * are asserted to the BMI_X2P_ARB. 771 * @max_pkt_len: Maximum packet length, integral number of 256B 772 * buffers. 773 */ 774 union bmi_ctl { 775 u64 value; 776 struct { 777 #if (defined(__BIG_ENDIAN_BITFIELD)) 778 u64 raz_56_63 : 8; 779 u64 ilk_hdrq_thrsh : 8; 780 u64 nps_hdrq_thrsh : 8; 781 u64 totl_hdrq_thrsh : 8; 782 u64 ilk_free_thrsh : 8; 783 u64 nps_free_thrsh : 8; 784 u64 totl_free_thrsh : 8; 785 u64 max_pkt_len : 8; 786 #else 787 u64 max_pkt_len : 8; 788 u64 totl_free_thrsh : 8; 789 u64 nps_free_thrsh : 8; 790 u64 ilk_free_thrsh : 8; 791 u64 totl_hdrq_thrsh : 8; 792 u64 nps_hdrq_thrsh : 8; 793 u64 ilk_hdrq_thrsh : 8; 794 u64 raz_56_63 : 8; 795 #endif 796 } s; 797 }; 798 799 /** 800 * struct bmi_int_ena_w1s - BMI interrupt enable set register 801 * @ilk_req_oflw: Reads or sets enable for 802 * BMI_INT[ILK_REQ_OFLW]. 803 * @nps_req_oflw: Reads or sets enable for 804 * BMI_INT[NPS_REQ_OFLW]. 805 * @fpf_undrrn: Reads or sets enable for 806 * BMI_INT[FPF_UNDRRN]. 807 * @eop_err_ilk: Reads or sets enable for 808 * BMI_INT[EOP_ERR_ILK]. 809 * @eop_err_nps: Reads or sets enable for 810 * BMI_INT[EOP_ERR_NPS]. 811 * @sop_err_ilk: Reads or sets enable for 812 * BMI_INT[SOP_ERR_ILK]. 813 * @sop_err_nps: Reads or sets enable for 814 * BMI_INT[SOP_ERR_NPS]. 815 * @pkt_rcv_err_ilk: Reads or sets enable for 816 * BMI_INT[PKT_RCV_ERR_ILK]. 817 * @pkt_rcv_err_nps: Reads or sets enable for 818 * BMI_INT[PKT_RCV_ERR_NPS]. 819 * @max_len_err_ilk: Reads or sets enable for 820 * BMI_INT[MAX_LEN_ERR_ILK]. 821 * @max_len_err_nps: Reads or sets enable for 822 * BMI_INT[MAX_LEN_ERR_NPS]. 823 */ 824 union bmi_int_ena_w1s { 825 u64 value; 826 struct { 827 #if (defined(__BIG_ENDIAN_BITFIELD)) 828 u64 raz_13_63 : 51; 829 u64 ilk_req_oflw : 1; 830 u64 nps_req_oflw : 1; 831 u64 raz_10 : 1; 832 u64 raz_9 : 1; 833 u64 fpf_undrrn : 1; 834 u64 eop_err_ilk : 1; 835 u64 eop_err_nps : 1; 836 u64 sop_err_ilk : 1; 837 u64 sop_err_nps : 1; 838 u64 pkt_rcv_err_ilk : 1; 839 u64 pkt_rcv_err_nps : 1; 840 u64 max_len_err_ilk : 1; 841 u64 max_len_err_nps : 1; 842 #else 843 u64 max_len_err_nps : 1; 844 u64 max_len_err_ilk : 1; 845 u64 pkt_rcv_err_nps : 1; 846 u64 pkt_rcv_err_ilk : 1; 847 u64 sop_err_nps : 1; 848 u64 sop_err_ilk : 1; 849 u64 eop_err_nps : 1; 850 u64 eop_err_ilk : 1; 851 u64 fpf_undrrn : 1; 852 u64 raz_9 : 1; 853 u64 raz_10 : 1; 854 u64 nps_req_oflw : 1; 855 u64 ilk_req_oflw : 1; 856 u64 raz_13_63 : 51; 857 #endif 858 } s; 859 }; 860 861 /** 862 * struct bmo_ctl2 - BMO Control2 Register 863 * @arb_sel: Determines P2X Arbitration 864 * @ilk_buf_thrsh: Maximum number of buffers that the 865 * ILK packet flows may consume before ILK XOFF is 866 * asserted to the POM. 867 * @nps_slc_buf_thrsh: Maximum number of buffers that the 868 * NPS_SLC packet flow may consume before NPS_SLC XOFF is 869 * asserted to the POM. 870 * @nps_uns_buf_thrsh: Maximum number of buffers that the 871 * NPS_UNS packet flow may consume before NPS_UNS XOFF is 872 * asserted to the POM. 873 * @totl_buf_thrsh: Maximum number of buffers that ILK, NPS_UNS and 874 * NPS_SLC packet flows may consume before NPS_UNS XOFF, NSP_SLC and 875 * ILK_XOFF are all asserted POM. 876 */ 877 union bmo_ctl2 { 878 u64 value; 879 struct { 880 #if (defined(__BIG_ENDIAN_BITFIELD)) 881 u64 arb_sel : 1; 882 u64 raz_32_62 : 31; 883 u64 ilk_buf_thrsh : 8; 884 u64 nps_slc_buf_thrsh : 8; 885 u64 nps_uns_buf_thrsh : 8; 886 u64 totl_buf_thrsh : 8; 887 #else 888 u64 totl_buf_thrsh : 8; 889 u64 nps_uns_buf_thrsh : 8; 890 u64 nps_slc_buf_thrsh : 8; 891 u64 ilk_buf_thrsh : 8; 892 u64 raz_32_62 : 31; 893 u64 arb_sel : 1; 894 #endif 895 } s; 896 }; 897 898 /** 899 * struct pom_int_ena_w1s - POM interrupt enable set register 900 * @illegal_intf: Reads or sets enable for POM_INT[ILLEGAL_INTF]. 901 * @illegal_dport: Reads or sets enable for POM_INT[ILLEGAL_DPORT]. 902 */ 903 union pom_int_ena_w1s { 904 u64 value; 905 struct { 906 #if (defined(__BIG_ENDIAN_BITFIELD)) 907 u64 raz2 : 60; 908 u64 illegal_intf : 1; 909 u64 illegal_dport : 1; 910 u64 raz1 : 1; 911 u64 raz0 : 1; 912 #else 913 u64 raz0 : 1; 914 u64 raz1 : 1; 915 u64 illegal_dport : 1; 916 u64 illegal_intf : 1; 917 u64 raz2 : 60; 918 #endif 919 } s; 920 }; 921 922 /** 923 * struct lbc_inval_ctl - LBC invalidation control register 924 * @wait_timer: Wait timer for wait state. [WAIT_TIMER] must 925 * always be written with its reset value. 926 * @cam_inval_start: Software should write [CAM_INVAL_START]=1 927 * to initiate an LBC cache invalidation. After this, software 928 * should read LBC_INVAL_STATUS until LBC_INVAL_STATUS[DONE] is set. 929 * LBC hardware clears [CAVM_INVAL_START] before software can 930 * observed LBC_INVAL_STATUS[DONE] to be set 931 */ 932 union lbc_inval_ctl { 933 u64 value; 934 struct { 935 #if (defined(__BIG_ENDIAN_BITFIELD)) 936 u64 raz2 : 48; 937 u64 wait_timer : 8; 938 u64 raz1 : 6; 939 u64 cam_inval_start : 1; 940 u64 raz0 : 1; 941 #else 942 u64 raz0 : 1; 943 u64 cam_inval_start : 1; 944 u64 raz1 : 6; 945 u64 wait_timer : 8; 946 u64 raz2 : 48; 947 #endif 948 } s; 949 }; 950 951 /** 952 * struct lbc_int_ena_w1s - LBC interrupt enable set register 953 * @cam_hard_err: Reads or sets enable for LBC_INT[CAM_HARD_ERR]. 954 * @cam_inval_abort: Reads or sets enable for LBC_INT[CAM_INVAL_ABORT]. 955 * @over_fetch_err: Reads or sets enable for LBC_INT[OVER_FETCH_ERR]. 956 * @cache_line_to_err: Reads or sets enable for 957 * LBC_INT[CACHE_LINE_TO_ERR]. 958 * @cam_soft_err: Reads or sets enable for 959 * LBC_INT[CAM_SOFT_ERR]. 960 * @dma_rd_err: Reads or sets enable for 961 * LBC_INT[DMA_RD_ERR]. 962 */ 963 union lbc_int_ena_w1s { 964 u64 value; 965 struct { 966 #if (defined(__BIG_ENDIAN_BITFIELD)) 967 u64 raz_10_63 : 54; 968 u64 cam_hard_err : 1; 969 u64 cam_inval_abort : 1; 970 u64 over_fetch_err : 1; 971 u64 cache_line_to_err : 1; 972 u64 raz_2_5 : 4; 973 u64 cam_soft_err : 1; 974 u64 dma_rd_err : 1; 975 #else 976 u64 dma_rd_err : 1; 977 u64 cam_soft_err : 1; 978 u64 raz_2_5 : 4; 979 u64 cache_line_to_err : 1; 980 u64 over_fetch_err : 1; 981 u64 cam_inval_abort : 1; 982 u64 cam_hard_err : 1; 983 u64 raz_10_63 : 54; 984 #endif 985 } s; 986 }; 987 988 /** 989 * struct lbc_int - LBC interrupt summary register 990 * @cam_hard_err: indicates a fatal hardware error. 991 * It requires system reset. 992 * When [CAM_HARD_ERR] is set, LBC stops logging any new information in 993 * LBC_POM_MISS_INFO_LOG, 994 * LBC_POM_MISS_ADDR_LOG, 995 * LBC_EFL_MISS_INFO_LOG, and 996 * LBC_EFL_MISS_ADDR_LOG. 997 * Software should sample them. 998 * @cam_inval_abort: indicates a fatal hardware error. 999 * System reset is required. 1000 * @over_fetch_err: indicates a fatal hardware error 1001 * System reset is required 1002 * @cache_line_to_err: is a debug feature. 1003 * This timeout interrupt bit tells the software that 1004 * a cacheline in LBC has non-zero usage and the context 1005 * has not been used for greater than the 1006 * LBC_TO_CNT[TO_CNT] time interval. 1007 * @sbe: Memory SBE error. This is recoverable via ECC. 1008 * See LBC_ECC_INT for more details. 1009 * @dbe: Memory DBE error. This is a fatal and requires a 1010 * system reset. 1011 * @pref_dat_len_mismatch_err: Summary bit for context length 1012 * mismatch errors. 1013 * @rd_dat_len_mismatch_err: Summary bit for SE read data length 1014 * greater than data prefect length errors. 1015 * @cam_soft_err: is recoverable. Software must complete a 1016 * LBC_INVAL_CTL[CAM_INVAL_START] invalidation sequence and 1017 * then clear [CAM_SOFT_ERR]. 1018 * @dma_rd_err: A context prefect read of host memory returned with 1019 * a read error. 1020 */ 1021 union lbc_int { 1022 u64 value; 1023 struct { 1024 #if (defined(__BIG_ENDIAN_BITFIELD)) 1025 u64 raz_10_63 : 54; 1026 u64 cam_hard_err : 1; 1027 u64 cam_inval_abort : 1; 1028 u64 over_fetch_err : 1; 1029 u64 cache_line_to_err : 1; 1030 u64 sbe : 1; 1031 u64 dbe : 1; 1032 u64 pref_dat_len_mismatch_err : 1; 1033 u64 rd_dat_len_mismatch_err : 1; 1034 u64 cam_soft_err : 1; 1035 u64 dma_rd_err : 1; 1036 #else 1037 u64 dma_rd_err : 1; 1038 u64 cam_soft_err : 1; 1039 u64 rd_dat_len_mismatch_err : 1; 1040 u64 pref_dat_len_mismatch_err : 1; 1041 u64 dbe : 1; 1042 u64 sbe : 1; 1043 u64 cache_line_to_err : 1; 1044 u64 over_fetch_err : 1; 1045 u64 cam_inval_abort : 1; 1046 u64 cam_hard_err : 1; 1047 u64 raz_10_63 : 54; 1048 #endif 1049 } s; 1050 }; 1051 1052 /** 1053 * struct lbc_inval_status: LBC Invalidation status register 1054 * @cam_clean_entry_complete_cnt: The number of entries that are 1055 * cleaned up successfully. 1056 * @cam_clean_entry_cnt: The number of entries that have the CAM 1057 * inval command issued. 1058 * @cam_inval_state: cam invalidation FSM state 1059 * @cam_inval_abort: cam invalidation abort 1060 * @cam_rst_rdy: lbc_cam reset ready 1061 * @done: LBC clears [DONE] when 1062 * LBC_INVAL_CTL[CAM_INVAL_START] is written with a one, 1063 * and sets [DONE] when it completes the invalidation 1064 * sequence. 1065 */ 1066 union lbc_inval_status { 1067 u64 value; 1068 struct { 1069 #if (defined(__BIG_ENDIAN_BITFIELD)) 1070 u64 raz3 : 23; 1071 u64 cam_clean_entry_complete_cnt : 9; 1072 u64 raz2 : 7; 1073 u64 cam_clean_entry_cnt : 9; 1074 u64 raz1 : 5; 1075 u64 cam_inval_state : 3; 1076 u64 raz0 : 5; 1077 u64 cam_inval_abort : 1; 1078 u64 cam_rst_rdy : 1; 1079 u64 done : 1; 1080 #else 1081 u64 done : 1; 1082 u64 cam_rst_rdy : 1; 1083 u64 cam_inval_abort : 1; 1084 u64 raz0 : 5; 1085 u64 cam_inval_state : 3; 1086 u64 raz1 : 5; 1087 u64 cam_clean_entry_cnt : 9; 1088 u64 raz2 : 7; 1089 u64 cam_clean_entry_complete_cnt : 9; 1090 u64 raz3 : 23; 1091 #endif 1092 } s; 1093 }; 1094 1095 /** 1096 * struct rst_boot: RST Boot Register 1097 * @jtcsrdis: when set, internal CSR access via JTAG TAP controller 1098 * is disabled 1099 * @jt_tst_mode: JTAG test mode 1100 * @io_supply: I/O power supply setting based on IO_VDD_SELECT pin: 1101 * 0x1 = 1.8V 1102 * 0x2 = 2.5V 1103 * 0x4 = 3.3V 1104 * All other values are reserved 1105 * @pnr_mul: clock multiplier 1106 * @lboot: last boot cause mask, resets only with PLL_DC_OK 1107 * @rboot: determines whether core 0 remains in reset after 1108 * chip cold or warm or soft reset 1109 * @rboot_pin: read only access to REMOTE_BOOT pin 1110 */ 1111 union rst_boot { 1112 u64 value; 1113 struct { 1114 #if (defined(__BIG_ENDIAN_BITFIELD)) 1115 u64 raz_63 : 1; 1116 u64 jtcsrdis : 1; 1117 u64 raz_59_61 : 3; 1118 u64 jt_tst_mode : 1; 1119 u64 raz_40_57 : 18; 1120 u64 io_supply : 3; 1121 u64 raz_30_36 : 7; 1122 u64 pnr_mul : 6; 1123 u64 raz_12_23 : 12; 1124 u64 lboot : 10; 1125 u64 rboot : 1; 1126 u64 rboot_pin : 1; 1127 #else 1128 u64 rboot_pin : 1; 1129 u64 rboot : 1; 1130 u64 lboot : 10; 1131 u64 raz_12_23 : 12; 1132 u64 pnr_mul : 6; 1133 u64 raz_30_36 : 7; 1134 u64 io_supply : 3; 1135 u64 raz_40_57 : 18; 1136 u64 jt_tst_mode : 1; 1137 u64 raz_59_61 : 3; 1138 u64 jtcsrdis : 1; 1139 u64 raz_63 : 1; 1140 #endif 1141 }; 1142 }; 1143 1144 /** 1145 * struct fus_dat1: Fuse Data 1 Register 1146 * @pll_mul: main clock PLL multiplier hardware limit 1147 * @pll_half_dis: main clock PLL control 1148 * @efus_lck: efuse lockdown 1149 * @zip_info: ZIP information 1150 * @bar2_sz_conf: when zero, BAR2 size conforms to 1151 * PCIe specification 1152 * @efus_ign: efuse ignore 1153 * @nozip: ZIP disable 1154 * @pll_alt_matrix: select alternate PLL matrix 1155 * @pll_bwadj_denom: select CLKF denominator for 1156 * BWADJ value 1157 * @chip_id: chip ID 1158 */ 1159 union fus_dat1 { 1160 u64 value; 1161 struct { 1162 #if (defined(__BIG_ENDIAN_BITFIELD)) 1163 u64 raz_57_63 : 7; 1164 u64 pll_mul : 3; 1165 u64 pll_half_dis : 1; 1166 u64 raz_43_52 : 10; 1167 u64 efus_lck : 3; 1168 u64 raz_26_39 : 14; 1169 u64 zip_info : 5; 1170 u64 bar2_sz_conf : 1; 1171 u64 efus_ign : 1; 1172 u64 nozip : 1; 1173 u64 raz_11_17 : 7; 1174 u64 pll_alt_matrix : 1; 1175 u64 pll_bwadj_denom : 2; 1176 u64 chip_id : 8; 1177 #else 1178 u64 chip_id : 8; 1179 u64 pll_bwadj_denom : 2; 1180 u64 pll_alt_matrix : 1; 1181 u64 raz_11_17 : 7; 1182 u64 nozip : 1; 1183 u64 efus_ign : 1; 1184 u64 bar2_sz_conf : 1; 1185 u64 zip_info : 5; 1186 u64 raz_26_39 : 14; 1187 u64 efus_lck : 3; 1188 u64 raz_43_52 : 10; 1189 u64 pll_half_dis : 1; 1190 u64 pll_mul : 3; 1191 u64 raz_57_63 : 7; 1192 #endif 1193 }; 1194 }; 1195 1196 #endif /* __NITROX_CSR_H */ 1197