1 /* 2 * Copyright (C) 2016 Cavium, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of version 2 of the GNU General Public License 6 * as published by the Free Software Foundation. 7 */ 8 9 #ifndef __CPT_HW_TYPES_H 10 #define __CPT_HW_TYPES_H 11 12 #include "cpt_common.h" 13 14 /** 15 * Enumeration cpt_comp_e 16 * 17 * CPT Completion Enumeration 18 * Enumerates the values of CPT_RES_S[COMPCODE]. 19 */ 20 enum cpt_comp_e { 21 CPT_COMP_E_NOTDONE = 0x00, 22 CPT_COMP_E_GOOD = 0x01, 23 CPT_COMP_E_FAULT = 0x02, 24 CPT_COMP_E_SWERR = 0x03, 25 CPT_COMP_E_LAST_ENTRY = 0xFF 26 }; 27 28 /** 29 * Structure cpt_inst_s 30 * 31 * CPT Instruction Structure 32 * This structure specifies the instruction layout. Instructions are 33 * stored in memory as little-endian unless CPT()_PF_Q()_CTL[INST_BE] is set. 34 * cpt_inst_s_s 35 * Word 0 36 * doneint:1 Done interrupt. 37 * 0 = No interrupts related to this instruction. 38 * 1 = When the instruction completes, CPT()_VQ()_DONE[DONE] will be 39 * incremented,and based on the rules described there an interrupt may 40 * occur. 41 * Word 1 42 * res_addr [127: 64] Result IOVA. 43 * If nonzero, specifies where to write CPT_RES_S. 44 * If zero, no result structure will be written. 45 * Address must be 16-byte aligned. 46 * Bits <63:49> are ignored by hardware; software should use a 47 * sign-extended bit <48> for forward compatibility. 48 * Word 2 49 * grp:10 [171:162] If [WQ_PTR] is nonzero, the SSO guest-group to use when 50 * CPT submits work SSO. 51 * For the SSO to not discard the add-work request, FPA_PF_MAP() must map 52 * [GRP] and CPT()_PF_Q()_GMCTL[GMID] as valid. 53 * tt:2 [161:160] If [WQ_PTR] is nonzero, the SSO tag type to use when CPT 54 * submits work to SSO 55 * tag:32 [159:128] If [WQ_PTR] is nonzero, the SSO tag to use when CPT 56 * submits work to SSO. 57 * Word 3 58 * wq_ptr [255:192] If [WQ_PTR] is nonzero, it is a pointer to a 59 * work-queue entry that CPT submits work to SSO after all context, 60 * output data, and result write operations are visible to other 61 * CNXXXX units and the cores. Bits <2:0> must be zero. 62 * Bits <63:49> are ignored by hardware; software should 63 * use a sign-extended bit <48> for forward compatibility. 64 * Internal: 65 * Bits <63:49>, <2:0> are ignored by hardware, treated as always 0x0. 66 * Word 4 67 * ei0; [319:256] Engine instruction word 0. Passed to the AE/SE. 68 * Word 5 69 * ei1; [383:320] Engine instruction word 1. Passed to the AE/SE. 70 * Word 6 71 * ei2; [447:384] Engine instruction word 1. Passed to the AE/SE. 72 * Word 7 73 * ei3; [511:448] Engine instruction word 1. Passed to the AE/SE. 74 * 75 */ 76 union cpt_inst_s { 77 u64 u[8]; 78 struct cpt_inst_s_s { 79 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */ 80 u64 reserved_17_63:47; 81 u64 doneint:1; 82 u64 reserved_0_1:16; 83 #else /* Word 0 - Little Endian */ 84 u64 reserved_0_15:16; 85 u64 doneint:1; 86 u64 reserved_17_63:47; 87 #endif /* Word 0 - End */ 88 u64 res_addr; 89 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 2 - Big Endian */ 90 u64 reserved_172_19:20; 91 u64 grp:10; 92 u64 tt:2; 93 u64 tag:32; 94 #else /* Word 2 - Little Endian */ 95 u64 tag:32; 96 u64 tt:2; 97 u64 grp:10; 98 u64 reserved_172_191:20; 99 #endif /* Word 2 - End */ 100 u64 wq_ptr; 101 u64 ei0; 102 u64 ei1; 103 u64 ei2; 104 u64 ei3; 105 } s; 106 }; 107 108 /** 109 * Structure cpt_res_s 110 * 111 * CPT Result Structure 112 * The CPT coprocessor writes the result structure after it completes a 113 * CPT_INST_S instruction. The result structure is exactly 16 bytes, and 114 * each instruction completion produces exactly one result structure. 115 * 116 * This structure is stored in memory as little-endian unless 117 * CPT()_PF_Q()_CTL[INST_BE] is set. 118 * cpt_res_s_s 119 * Word 0 120 * doneint:1 [16:16] Done interrupt. This bit is copied from the 121 * corresponding instruction's CPT_INST_S[DONEINT]. 122 * compcode:8 [7:0] Indicates completion/error status of the CPT coprocessor 123 * for the associated instruction, as enumerated by CPT_COMP_E. 124 * Core software may write the memory location containing [COMPCODE] to 125 * 0x0 before ringing the doorbell, and then poll for completion by 126 * checking for a nonzero value. 127 * Once the core observes a nonzero [COMPCODE] value in this case,the CPT 128 * coprocessor will have also completed L2/DRAM write operations. 129 * Word 1 130 * reserved 131 * 132 */ 133 union cpt_res_s { 134 u64 u[2]; 135 struct cpt_res_s_s { 136 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */ 137 u64 reserved_17_63:47; 138 u64 doneint:1; 139 u64 reserved_8_15:8; 140 u64 compcode:8; 141 #else /* Word 0 - Little Endian */ 142 u64 compcode:8; 143 u64 reserved_8_15:8; 144 u64 doneint:1; 145 u64 reserved_17_63:47; 146 #endif /* Word 0 - End */ 147 u64 reserved_64_127; 148 } s; 149 }; 150 151 /** 152 * Register (NCB) cpt#_pf_bist_status 153 * 154 * CPT PF Control Bist Status Register 155 * This register has the BIST status of memories. Each bit is the BIST result 156 * of an individual memory (per bit, 0 = pass and 1 = fail). 157 * cptx_pf_bist_status_s 158 * Word0 159 * bstatus [29:0](RO/H) BIST status. One bit per memory, enumerated by 160 * CPT_RAMS_E. 161 */ 162 union cptx_pf_bist_status { 163 u64 u; 164 struct cptx_pf_bist_status_s { 165 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */ 166 u64 reserved_30_63:34; 167 u64 bstatus:30; 168 #else /* Word 0 - Little Endian */ 169 u64 bstatus:30; 170 u64 reserved_30_63:34; 171 #endif /* Word 0 - End */ 172 } s; 173 }; 174 175 /** 176 * Register (NCB) cpt#_pf_constants 177 * 178 * CPT PF Constants Register 179 * This register contains implementation-related parameters of CPT in CNXXXX. 180 * cptx_pf_constants_s 181 * Word 0 182 * reserved_40_63:24 [63:40] Reserved. 183 * epcis:8 [39:32](RO) Number of EPCI busses. 184 * grps:8 [31:24](RO) Number of engine groups implemented. 185 * ae:8 [23:16](RO/H) Number of AEs. In CNXXXX, for CPT0 returns 0x0, 186 * for CPT1 returns 0x18, or less if there are fuse-disables. 187 * se:8 [15:8](RO/H) Number of SEs. In CNXXXX, for CPT0 returns 0x30, 188 * or less if there are fuse-disables, for CPT1 returns 0x0. 189 * vq:8 [7:0](RO) Number of VQs. 190 */ 191 union cptx_pf_constants { 192 u64 u; 193 struct cptx_pf_constants_s { 194 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */ 195 u64 reserved_40_63:24; 196 u64 epcis:8; 197 u64 grps:8; 198 u64 ae:8; 199 u64 se:8; 200 u64 vq:8; 201 #else /* Word 0 - Little Endian */ 202 u64 vq:8; 203 u64 se:8; 204 u64 ae:8; 205 u64 grps:8; 206 u64 epcis:8; 207 u64 reserved_40_63:24; 208 #endif /* Word 0 - End */ 209 } s; 210 }; 211 212 /** 213 * Register (NCB) cpt#_pf_exe_bist_status 214 * 215 * CPT PF Engine Bist Status Register 216 * This register has the BIST status of each engine. Each bit is the 217 * BIST result of an individual engine (per bit, 0 = pass and 1 = fail). 218 * cptx_pf_exe_bist_status_s 219 * Word0 220 * reserved_48_63:16 [63:48] reserved 221 * bstatus:48 [47:0](RO/H) BIST status. One bit per engine. 222 * 223 */ 224 union cptx_pf_exe_bist_status { 225 u64 u; 226 struct cptx_pf_exe_bist_status_s { 227 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */ 228 u64 reserved_48_63:16; 229 u64 bstatus:48; 230 #else /* Word 0 - Little Endian */ 231 u64 bstatus:48; 232 u64 reserved_48_63:16; 233 #endif /* Word 0 - End */ 234 } s; 235 }; 236 237 /** 238 * Register (NCB) cpt#_pf_q#_ctl 239 * 240 * CPT Queue Control Register 241 * This register configures queues. This register should be changed only 242 * when quiescent (see CPT()_VQ()_INPROG[INFLIGHT]). 243 * cptx_pf_qx_ctl_s 244 * Word0 245 * reserved_60_63:4 [63:60] reserved. 246 * aura:12; [59:48](R/W) Guest-aura for returning this queue's 247 * instruction-chunk buffers to FPA. Only used when [INST_FREE] is set. 248 * For the FPA to not discard the request, FPA_PF_MAP() must map 249 * [AURA] and CPT()_PF_Q()_GMCTL[GMID] as valid. 250 * reserved_45_47:3 [47:45] reserved. 251 * size:13 [44:32](R/W) Command-buffer size, in number of 64-bit words per 252 * command buffer segment. Must be 8*n + 1, where n is the number of 253 * instructions per buffer segment. 254 * reserved_11_31:21 [31:11] Reserved. 255 * cont_err:1 [10:10](R/W) Continue on error. 256 * 0 = When CPT()_VQ()_MISC_INT[NWRP], CPT()_VQ()_MISC_INT[IRDE] or 257 * CPT()_VQ()_MISC_INT[DOVF] are set by hardware or software via 258 * CPT()_VQ()_MISC_INT_W1S, then CPT()_VQ()_CTL[ENA] is cleared. Due to 259 * pipelining, additional instructions may have been processed between the 260 * instruction causing the error and the next instruction in the disabled 261 * queue (the instruction at CPT()_VQ()_SADDR). 262 * 1 = Ignore errors and continue processing instructions. 263 * For diagnostic use only. 264 * inst_free:1 [9:9](R/W) Instruction FPA free. When set, when CPT reaches the 265 * end of an instruction chunk, that chunk will be freed to the FPA. 266 * inst_be:1 [8:8](R/W) Instruction big-endian control. When set, instructions, 267 * instruction next chunk pointers, and result structures are stored in 268 * big-endian format in memory. 269 * iqb_ldwb:1 [7:7](R/W) Instruction load don't write back. 270 * 0 = The hardware issues NCB transient load (LDT) towards the cache, 271 * which if the line hits and is is dirty will cause the line to be 272 * written back before being replaced. 273 * 1 = The hardware issues NCB LDWB read-and-invalidate command towards 274 * the cache when fetching the last word of instructions; as a result the 275 * line will not be written back when replaced. This improves 276 * performance, but software must not read the instructions after they are 277 * posted to the hardware. Reads that do not consume the last word of a 278 * cache line always use LDI. 279 * reserved_4_6:3 [6:4] Reserved. 280 * grp:3; [3:1](R/W) Engine group. 281 * pri:1; [0:0](R/W) Queue priority. 282 * 1 = This queue has higher priority. Round-robin between higher 283 * priority queues. 284 * 0 = This queue has lower priority. Round-robin between lower 285 * priority queues. 286 */ 287 union cptx_pf_qx_ctl { 288 u64 u; 289 struct cptx_pf_qx_ctl_s { 290 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */ 291 u64 reserved_60_63:4; 292 u64 aura:12; 293 u64 reserved_45_47:3; 294 u64 size:13; 295 u64 reserved_11_31:21; 296 u64 cont_err:1; 297 u64 inst_free:1; 298 u64 inst_be:1; 299 u64 iqb_ldwb:1; 300 u64 reserved_4_6:3; 301 u64 grp:3; 302 u64 pri:1; 303 #else /* Word 0 - Little Endian */ 304 u64 pri:1; 305 u64 grp:3; 306 u64 reserved_4_6:3; 307 u64 iqb_ldwb:1; 308 u64 inst_be:1; 309 u64 inst_free:1; 310 u64 cont_err:1; 311 u64 reserved_11_31:21; 312 u64 size:13; 313 u64 reserved_45_47:3; 314 u64 aura:12; 315 u64 reserved_60_63:4; 316 #endif /* Word 0 - End */ 317 } s; 318 }; 319 320 /** 321 * Register (NCB) cpt#_vq#_saddr 322 * 323 * CPT Queue Starting Buffer Address Registers 324 * These registers set the instruction buffer starting address. 325 * cptx_vqx_saddr_s 326 * Word0 327 * reserved_49_63:15 [63:49] Reserved. 328 * ptr:43 [48:6](R/W/H) Instruction buffer IOVA <48:6> (64-byte aligned). 329 * When written, it is the initial buffer starting address; when read, 330 * it is the next read pointer to be requested from L2C. The PTR field 331 * is overwritten with the next pointer each time that the command buffer 332 * segment is exhausted. New commands will then be read from the newly 333 * specified command buffer pointer. 334 * reserved_0_5:6 [5:0] Reserved. 335 * 336 */ 337 union cptx_vqx_saddr { 338 u64 u; 339 struct cptx_vqx_saddr_s { 340 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */ 341 u64 reserved_49_63:15; 342 u64 ptr:43; 343 u64 reserved_0_5:6; 344 #else /* Word 0 - Little Endian */ 345 u64 reserved_0_5:6; 346 u64 ptr:43; 347 u64 reserved_49_63:15; 348 #endif /* Word 0 - End */ 349 } s; 350 }; 351 352 /** 353 * Register (NCB) cpt#_vq#_misc_ena_w1s 354 * 355 * CPT Queue Misc Interrupt Enable Set Register 356 * This register sets interrupt enable bits. 357 * cptx_vqx_misc_ena_w1s_s 358 * Word0 359 * reserved_5_63:59 [63:5] Reserved. 360 * swerr:1 [4:4](R/W1S/H) Reads or sets enable for 361 * CPT(0..1)_VQ(0..63)_MISC_INT[SWERR]. 362 * nwrp:1 [3:3](R/W1S/H) Reads or sets enable for 363 * CPT(0..1)_VQ(0..63)_MISC_INT[NWRP]. 364 * irde:1 [2:2](R/W1S/H) Reads or sets enable for 365 * CPT(0..1)_VQ(0..63)_MISC_INT[IRDE]. 366 * dovf:1 [1:1](R/W1S/H) Reads or sets enable for 367 * CPT(0..1)_VQ(0..63)_MISC_INT[DOVF]. 368 * mbox:1 [0:0](R/W1S/H) Reads or sets enable for 369 * CPT(0..1)_VQ(0..63)_MISC_INT[MBOX]. 370 * 371 */ 372 union cptx_vqx_misc_ena_w1s { 373 u64 u; 374 struct cptx_vqx_misc_ena_w1s_s { 375 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */ 376 u64 reserved_5_63:59; 377 u64 swerr:1; 378 u64 nwrp:1; 379 u64 irde:1; 380 u64 dovf:1; 381 u64 mbox:1; 382 #else /* Word 0 - Little Endian */ 383 u64 mbox:1; 384 u64 dovf:1; 385 u64 irde:1; 386 u64 nwrp:1; 387 u64 swerr:1; 388 u64 reserved_5_63:59; 389 #endif /* Word 0 - End */ 390 } s; 391 }; 392 393 /** 394 * Register (NCB) cpt#_vq#_doorbell 395 * 396 * CPT Queue Doorbell Registers 397 * Doorbells for the CPT instruction queues. 398 * cptx_vqx_doorbell_s 399 * Word0 400 * reserved_20_63:44 [63:20] Reserved. 401 * dbell_cnt:20 [19:0](R/W/H) Number of instruction queue 64-bit words to add 402 * to the CPT instruction doorbell count. Readback value is the the 403 * current number of pending doorbell requests. If counter overflows 404 * CPT()_VQ()_MISC_INT[DBELL_DOVF] is set. To reset the count back to 405 * zero, write one to clear CPT()_VQ()_MISC_INT_ENA_W1C[DBELL_DOVF], 406 * then write a value of 2^20 minus the read [DBELL_CNT], then write one 407 * to CPT()_VQ()_MISC_INT_W1C[DBELL_DOVF] and 408 * CPT()_VQ()_MISC_INT_ENA_W1S[DBELL_DOVF]. Must be a multiple of 8. 409 * All CPT instructions are 8 words and require a doorbell count of 410 * multiple of 8. 411 */ 412 union cptx_vqx_doorbell { 413 u64 u; 414 struct cptx_vqx_doorbell_s { 415 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */ 416 u64 reserved_20_63:44; 417 u64 dbell_cnt:20; 418 #else /* Word 0 - Little Endian */ 419 u64 dbell_cnt:20; 420 u64 reserved_20_63:44; 421 #endif /* Word 0 - End */ 422 } s; 423 }; 424 425 /** 426 * Register (NCB) cpt#_vq#_inprog 427 * 428 * CPT Queue In Progress Count Registers 429 * These registers contain the per-queue instruction in flight registers. 430 * cptx_vqx_inprog_s 431 * Word0 432 * reserved_8_63:56 [63:8] Reserved. 433 * inflight:8 [7:0](RO/H) Inflight count. Counts the number of instructions 434 * for the VF for which CPT is fetching, executing or responding to 435 * instructions. However this does not include any interrupts that are 436 * awaiting software handling (CPT()_VQ()_DONE[DONE] != 0x0). 437 * A queue may not be reconfigured until: 438 * 1. CPT()_VQ()_CTL[ENA] is cleared by software. 439 * 2. [INFLIGHT] is polled until equals to zero. 440 */ 441 union cptx_vqx_inprog { 442 u64 u; 443 struct cptx_vqx_inprog_s { 444 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */ 445 u64 reserved_8_63:56; 446 u64 inflight:8; 447 #else /* Word 0 - Little Endian */ 448 u64 inflight:8; 449 u64 reserved_8_63:56; 450 #endif /* Word 0 - End */ 451 } s; 452 }; 453 454 /** 455 * Register (NCB) cpt#_vq#_misc_int 456 * 457 * CPT Queue Misc Interrupt Register 458 * These registers contain the per-queue miscellaneous interrupts. 459 * cptx_vqx_misc_int_s 460 * Word 0 461 * reserved_5_63:59 [63:5] Reserved. 462 * swerr:1 [4:4](R/W1C/H) Software error from engines. 463 * nwrp:1 [3:3](R/W1C/H) NCB result write response error. 464 * irde:1 [2:2](R/W1C/H) Instruction NCB read response error. 465 * dovf:1 [1:1](R/W1C/H) Doorbell overflow. 466 * mbox:1 [0:0](R/W1C/H) PF to VF mailbox interrupt. Set when 467 * CPT()_VF()_PF_MBOX(0) is written. 468 * 469 */ 470 union cptx_vqx_misc_int { 471 u64 u; 472 struct cptx_vqx_misc_int_s { 473 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */ 474 u64 reserved_5_63:59; 475 u64 swerr:1; 476 u64 nwrp:1; 477 u64 irde:1; 478 u64 dovf:1; 479 u64 mbox:1; 480 #else /* Word 0 - Little Endian */ 481 u64 mbox:1; 482 u64 dovf:1; 483 u64 irde:1; 484 u64 nwrp:1; 485 u64 swerr:1; 486 u64 reserved_5_63:59; 487 #endif /* Word 0 - End */ 488 } s; 489 }; 490 491 /** 492 * Register (NCB) cpt#_vq#_done_ack 493 * 494 * CPT Queue Done Count Ack Registers 495 * This register is written by software to acknowledge interrupts. 496 * cptx_vqx_done_ack_s 497 * Word0 498 * reserved_20_63:44 [63:20] Reserved. 499 * done_ack:20 [19:0](R/W/H) Number of decrements to CPT()_VQ()_DONE[DONE]. 500 * Reads CPT()_VQ()_DONE[DONE]. Written by software to acknowledge 501 * interrupts. If CPT()_VQ()_DONE[DONE] is still nonzero the interrupt 502 * will be re-sent if the conditions described in CPT()_VQ()_DONE[DONE] 503 * are satisfied. 504 * 505 */ 506 union cptx_vqx_done_ack { 507 u64 u; 508 struct cptx_vqx_done_ack_s { 509 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */ 510 u64 reserved_20_63:44; 511 u64 done_ack:20; 512 #else /* Word 0 - Little Endian */ 513 u64 done_ack:20; 514 u64 reserved_20_63:44; 515 #endif /* Word 0 - End */ 516 } s; 517 }; 518 519 /** 520 * Register (NCB) cpt#_vq#_done 521 * 522 * CPT Queue Done Count Registers 523 * These registers contain the per-queue instruction done count. 524 * cptx_vqx_done_s 525 * Word0 526 * reserved_20_63:44 [63:20] Reserved. 527 * done:20 [19:0](R/W/H) Done count. When CPT_INST_S[DONEINT] set and that 528 * instruction completes, CPT()_VQ()_DONE[DONE] is incremented when the 529 * instruction finishes. Write to this field are for diagnostic use only; 530 * instead software writes CPT()_VQ()_DONE_ACK with the number of 531 * decrements for this field. 532 * Interrupts are sent as follows: 533 * * When CPT()_VQ()_DONE[DONE] = 0, then no results are pending, the 534 * interrupt coalescing timer is held to zero, and an interrupt is not 535 * sent. 536 * * When CPT()_VQ()_DONE[DONE] != 0, then the interrupt coalescing timer 537 * counts. If the counter is >= CPT()_VQ()_DONE_WAIT[TIME_WAIT]*1024, or 538 * CPT()_VQ()_DONE[DONE] >= CPT()_VQ()_DONE_WAIT[NUM_WAIT], i.e. enough 539 * time has passed or enough results have arrived, then the interrupt is 540 * sent. 541 * * When CPT()_VQ()_DONE_ACK is written (or CPT()_VQ()_DONE is written 542 * but this is not typical), the interrupt coalescing timer restarts. 543 * Note after decrementing this interrupt equation is recomputed, 544 * for example if CPT()_VQ()_DONE[DONE] >= CPT()_VQ()_DONE_WAIT[NUM_WAIT] 545 * and because the timer is zero, the interrupt will be resent immediately. 546 * (This covers the race case between software acknowledging an interrupt 547 * and a result returning.) 548 * * When CPT()_VQ()_DONE_ENA_W1S[DONE] = 0, interrupts are not sent, 549 * but the counting described above still occurs. 550 * Since CPT instructions complete out-of-order, if software is using 551 * completion interrupts the suggested scheme is to request a DONEINT on 552 * each request, and when an interrupt arrives perform a "greedy" scan for 553 * completions; even if a later command is acknowledged first this will 554 * not result in missing a completion. 555 * Software is responsible for making sure [DONE] does not overflow; 556 * for example by insuring there are not more than 2^20-1 instructions in 557 * flight that may request interrupts. 558 * 559 */ 560 union cptx_vqx_done { 561 u64 u; 562 struct cptx_vqx_done_s { 563 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */ 564 u64 reserved_20_63:44; 565 u64 done:20; 566 #else /* Word 0 - Little Endian */ 567 u64 done:20; 568 u64 reserved_20_63:44; 569 #endif /* Word 0 - End */ 570 } s; 571 }; 572 573 /** 574 * Register (NCB) cpt#_vq#_done_wait 575 * 576 * CPT Queue Done Interrupt Coalescing Wait Registers 577 * Specifies the per queue interrupt coalescing settings. 578 * cptx_vqx_done_wait_s 579 * Word0 580 * reserved_48_63:16 [63:48] Reserved. 581 * time_wait:16; [47:32](R/W) Time hold-off. When CPT()_VQ()_DONE[DONE] = 0 582 * or CPT()_VQ()_DONE_ACK is written a timer is cleared. When the timer 583 * reaches [TIME_WAIT]*1024 then interrupt coalescing ends. 584 * see CPT()_VQ()_DONE[DONE]. If 0x0, time coalescing is disabled. 585 * reserved_20_31:12 [31:20] Reserved. 586 * num_wait:20 [19:0](R/W) Number of messages hold-off. 587 * When CPT()_VQ()_DONE[DONE] >= [NUM_WAIT] then interrupt coalescing ends 588 * see CPT()_VQ()_DONE[DONE]. If 0x0, same behavior as 0x1. 589 * 590 */ 591 union cptx_vqx_done_wait { 592 u64 u; 593 struct cptx_vqx_done_wait_s { 594 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */ 595 u64 reserved_48_63:16; 596 u64 time_wait:16; 597 u64 reserved_20_31:12; 598 u64 num_wait:20; 599 #else /* Word 0 - Little Endian */ 600 u64 num_wait:20; 601 u64 reserved_20_31:12; 602 u64 time_wait:16; 603 u64 reserved_48_63:16; 604 #endif /* Word 0 - End */ 605 } s; 606 }; 607 608 /** 609 * Register (NCB) cpt#_vq#_done_ena_w1s 610 * 611 * CPT Queue Done Interrupt Enable Set Registers 612 * Write 1 to these registers will enable the DONEINT interrupt for the queue. 613 * cptx_vqx_done_ena_w1s_s 614 * Word0 615 * reserved_1_63:63 [63:1] Reserved. 616 * done:1 [0:0](R/W1S/H) Write 1 will enable DONEINT for this queue. 617 * Write 0 has no effect. Read will return the enable bit. 618 */ 619 union cptx_vqx_done_ena_w1s { 620 u64 u; 621 struct cptx_vqx_done_ena_w1s_s { 622 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */ 623 u64 reserved_1_63:63; 624 u64 done:1; 625 #else /* Word 0 - Little Endian */ 626 u64 done:1; 627 u64 reserved_1_63:63; 628 #endif /* Word 0 - End */ 629 } s; 630 }; 631 632 /** 633 * Register (NCB) cpt#_vq#_ctl 634 * 635 * CPT VF Queue Control Registers 636 * This register configures queues. This register should be changed (other than 637 * clearing [ENA]) only when quiescent (see CPT()_VQ()_INPROG[INFLIGHT]). 638 * cptx_vqx_ctl_s 639 * Word0 640 * reserved_1_63:63 [63:1] Reserved. 641 * ena:1 [0:0](R/W/H) Enables the logical instruction queue. 642 * See also CPT()_PF_Q()_CTL[CONT_ERR] and CPT()_VQ()_INPROG[INFLIGHT]. 643 * 1 = Queue is enabled. 644 * 0 = Queue is disabled. 645 */ 646 union cptx_vqx_ctl { 647 u64 u; 648 struct cptx_vqx_ctl_s { 649 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */ 650 u64 reserved_1_63:63; 651 u64 ena:1; 652 #else /* Word 0 - Little Endian */ 653 u64 ena:1; 654 u64 reserved_1_63:63; 655 #endif /* Word 0 - End */ 656 } s; 657 }; 658 #endif /*__CPT_HW_TYPES_H*/ 659