1 /* 2 * Copyright (C) 2016 Cavium, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of version 2 of the GNU General Public License 6 * as published by the Free Software Foundation. 7 */ 8 9 #ifndef __CPT_COMMON_H 10 #define __CPT_COMMON_H 11 12 #include <asm/byteorder.h> 13 #include <linux/delay.h> 14 #include <linux/pci.h> 15 16 #include "cpt_hw_types.h" 17 18 /* Device ID */ 19 #define CPT_81XX_PCI_PF_DEVICE_ID 0xa040 20 #define CPT_81XX_PCI_VF_DEVICE_ID 0xa041 21 22 /* flags to indicate the features supported */ 23 #define CPT_FLAG_SRIOV_ENABLED BIT(1) 24 #define CPT_FLAG_VF_DRIVER BIT(2) 25 #define CPT_FLAG_DEVICE_READY BIT(3) 26 27 #define cpt_sriov_enabled(cpt) ((cpt)->flags & CPT_FLAG_SRIOV_ENABLED) 28 #define cpt_vf_driver(cpt) ((cpt)->flags & CPT_FLAG_VF_DRIVER) 29 #define cpt_device_ready(cpt) ((cpt)->flags & CPT_FLAG_DEVICE_READY) 30 31 #define CPT_MBOX_MSG_TYPE_ACK 1 32 #define CPT_MBOX_MSG_TYPE_NACK 2 33 #define CPT_MBOX_MSG_TIMEOUT 2000 34 #define VF_STATE_DOWN 0 35 #define VF_STATE_UP 1 36 37 /* 38 * CPT Registers map for 81xx 39 */ 40 41 /* PF registers */ 42 #define CPTX_PF_CONSTANTS(a) (0x0ll + ((u64)(a) << 36)) 43 #define CPTX_PF_RESET(a) (0x100ll + ((u64)(a) << 36)) 44 #define CPTX_PF_DIAG(a) (0x120ll + ((u64)(a) << 36)) 45 #define CPTX_PF_BIST_STATUS(a) (0x160ll + ((u64)(a) << 36)) 46 #define CPTX_PF_ECC0_CTL(a) (0x200ll + ((u64)(a) << 36)) 47 #define CPTX_PF_ECC0_FLIP(a) (0x210ll + ((u64)(a) << 36)) 48 #define CPTX_PF_ECC0_INT(a) (0x220ll + ((u64)(a) << 36)) 49 #define CPTX_PF_ECC0_INT_W1S(a) (0x230ll + ((u64)(a) << 36)) 50 #define CPTX_PF_ECC0_ENA_W1S(a) (0x240ll + ((u64)(a) << 36)) 51 #define CPTX_PF_ECC0_ENA_W1C(a) (0x250ll + ((u64)(a) << 36)) 52 #define CPTX_PF_MBOX_INTX(a, b) \ 53 (0x400ll + ((u64)(a) << 36) + ((b) << 3)) 54 #define CPTX_PF_MBOX_INT_W1SX(a, b) \ 55 (0x420ll + ((u64)(a) << 36) + ((b) << 3)) 56 #define CPTX_PF_MBOX_ENA_W1CX(a, b) \ 57 (0x440ll + ((u64)(a) << 36) + ((b) << 3)) 58 #define CPTX_PF_MBOX_ENA_W1SX(a, b) \ 59 (0x460ll + ((u64)(a) << 36) + ((b) << 3)) 60 #define CPTX_PF_EXEC_INT(a) (0x500ll + 0x1000000000ll * ((a) & 0x1)) 61 #define CPTX_PF_EXEC_INT_W1S(a) (0x520ll + ((u64)(a) << 36)) 62 #define CPTX_PF_EXEC_ENA_W1C(a) (0x540ll + ((u64)(a) << 36)) 63 #define CPTX_PF_EXEC_ENA_W1S(a) (0x560ll + ((u64)(a) << 36)) 64 #define CPTX_PF_GX_EN(a, b) \ 65 (0x600ll + ((u64)(a) << 36) + ((b) << 3)) 66 #define CPTX_PF_EXEC_INFO(a) (0x700ll + ((u64)(a) << 36)) 67 #define CPTX_PF_EXEC_BUSY(a) (0x800ll + ((u64)(a) << 36)) 68 #define CPTX_PF_EXEC_INFO0(a) (0x900ll + ((u64)(a) << 36)) 69 #define CPTX_PF_EXEC_INFO1(a) (0x910ll + ((u64)(a) << 36)) 70 #define CPTX_PF_INST_REQ_PC(a) (0x10000ll + ((u64)(a) << 36)) 71 #define CPTX_PF_INST_LATENCY_PC(a) \ 72 (0x10020ll + ((u64)(a) << 36)) 73 #define CPTX_PF_RD_REQ_PC(a) (0x10040ll + ((u64)(a) << 36)) 74 #define CPTX_PF_RD_LATENCY_PC(a) (0x10060ll + ((u64)(a) << 36)) 75 #define CPTX_PF_RD_UC_PC(a) (0x10080ll + ((u64)(a) << 36)) 76 #define CPTX_PF_ACTIVE_CYCLES_PC(a) (0x10100ll + ((u64)(a) << 36)) 77 #define CPTX_PF_EXE_CTL(a) (0x4000000ll + ((u64)(a) << 36)) 78 #define CPTX_PF_EXE_STATUS(a) (0x4000008ll + ((u64)(a) << 36)) 79 #define CPTX_PF_EXE_CLK(a) (0x4000010ll + ((u64)(a) << 36)) 80 #define CPTX_PF_EXE_DBG_CTL(a) (0x4000018ll + ((u64)(a) << 36)) 81 #define CPTX_PF_EXE_DBG_DATA(a) (0x4000020ll + ((u64)(a) << 36)) 82 #define CPTX_PF_EXE_BIST_STATUS(a) (0x4000028ll + ((u64)(a) << 36)) 83 #define CPTX_PF_EXE_REQ_TIMER(a) (0x4000030ll + ((u64)(a) << 36)) 84 #define CPTX_PF_EXE_MEM_CTL(a) (0x4000038ll + ((u64)(a) << 36)) 85 #define CPTX_PF_EXE_PERF_CTL(a) (0x4001000ll + ((u64)(a) << 36)) 86 #define CPTX_PF_EXE_DBG_CNTX(a, b) \ 87 (0x4001100ll + ((u64)(a) << 36) + ((b) << 3)) 88 #define CPTX_PF_EXE_PERF_EVENT_CNT(a) (0x4001180ll + ((u64)(a) << 36)) 89 #define CPTX_PF_EXE_EPCI_INBX_CNT(a, b) \ 90 (0x4001200ll + ((u64)(a) << 36) + ((b) << 3)) 91 #define CPTX_PF_EXE_EPCI_OUTBX_CNT(a, b) \ 92 (0x4001240ll + ((u64)(a) << 36) + ((b) << 3)) 93 #define CPTX_PF_ENGX_UCODE_BASE(a, b) \ 94 (0x4002000ll + ((u64)(a) << 36) + ((b) << 3)) 95 #define CPTX_PF_QX_CTL(a, b) \ 96 (0x8000000ll + ((u64)(a) << 36) + ((b) << 20)) 97 #define CPTX_PF_QX_GMCTL(a, b) \ 98 (0x8000020ll + ((u64)(a) << 36) + ((b) << 20)) 99 #define CPTX_PF_QX_CTL2(a, b) \ 100 (0x8000100ll + ((u64)(a) << 36) + ((b) << 20)) 101 #define CPTX_PF_VFX_MBOXX(a, b, c) \ 102 (0x8001000ll + ((u64)(a) << 36) + ((b) << 20) + ((c) << 8)) 103 104 /* VF registers */ 105 #define CPTX_VQX_CTL(a, b) (0x100ll + ((u64)(a) << 36) + ((b) << 20)) 106 #define CPTX_VQX_SADDR(a, b) (0x200ll + ((u64)(a) << 36) + ((b) << 20)) 107 #define CPTX_VQX_DONE_WAIT(a, b) (0x400ll + ((u64)(a) << 36) + ((b) << 20)) 108 #define CPTX_VQX_INPROG(a, b) (0x410ll + ((u64)(a) << 36) + ((b) << 20)) 109 #define CPTX_VQX_DONE(a, b) (0x420ll + ((u64)(a) << 36) + ((b) << 20)) 110 #define CPTX_VQX_DONE_ACK(a, b) (0x440ll + ((u64)(a) << 36) + ((b) << 20)) 111 #define CPTX_VQX_DONE_INT_W1S(a, b) (0x460ll + ((u64)(a) << 36) + ((b) << 20)) 112 #define CPTX_VQX_DONE_INT_W1C(a, b) (0x468ll + ((u64)(a) << 36) + ((b) << 20)) 113 #define CPTX_VQX_DONE_ENA_W1S(a, b) (0x470ll + ((u64)(a) << 36) + ((b) << 20)) 114 #define CPTX_VQX_DONE_ENA_W1C(a, b) (0x478ll + ((u64)(a) << 36) + ((b) << 20)) 115 #define CPTX_VQX_MISC_INT(a, b) (0x500ll + ((u64)(a) << 36) + ((b) << 20)) 116 #define CPTX_VQX_MISC_INT_W1S(a, b) (0x508ll + ((u64)(a) << 36) + ((b) << 20)) 117 #define CPTX_VQX_MISC_ENA_W1S(a, b) (0x510ll + ((u64)(a) << 36) + ((b) << 20)) 118 #define CPTX_VQX_MISC_ENA_W1C(a, b) (0x518ll + ((u64)(a) << 36) + ((b) << 20)) 119 #define CPTX_VQX_DOORBELL(a, b) (0x600ll + ((u64)(a) << 36) + ((b) << 20)) 120 #define CPTX_VFX_PF_MBOXX(a, b, c) \ 121 (0x1000ll + ((u64)(a) << 36) + ((b) << 20) + ((c) << 3)) 122 123 enum vftype { 124 AE_TYPES = 1, 125 SE_TYPES = 2, 126 BAD_CPT_TYPES, 127 }; 128 129 /* Max CPT devices supported */ 130 enum cpt_mbox_opcode { 131 CPT_MSG_VF_UP = 1, 132 CPT_MSG_VF_DOWN, 133 CPT_MSG_READY, 134 CPT_MSG_QLEN, 135 CPT_MSG_QBIND_GRP, 136 CPT_MSG_VQ_PRIORITY, 137 }; 138 139 /* CPT mailbox structure */ 140 struct cpt_mbox { 141 u64 msg; /* Message type MBOX[0] */ 142 u64 data;/* Data MBOX[1] */ 143 }; 144 145 /* Register read/write APIs */ 146 static inline void cpt_write_csr64(u8 __iomem *hw_addr, u64 offset, 147 u64 val) 148 { 149 writeq(val, hw_addr + offset); 150 } 151 152 static inline u64 cpt_read_csr64(u8 __iomem *hw_addr, u64 offset) 153 { 154 return readq(hw_addr + offset); 155 } 156 #endif /* __CPT_COMMON_H */ 157