1 /* 2 * CAAM hardware register-level view 3 * 4 * Copyright 2008-2011 Freescale Semiconductor, Inc. 5 */ 6 7 #ifndef REGS_H 8 #define REGS_H 9 10 #include <linux/types.h> 11 #include <linux/bitops.h> 12 #include <linux/io.h> 13 14 /* 15 * Architecture-specific register access methods 16 * 17 * CAAM's bus-addressable registers are 64 bits internally. 18 * They have been wired to be safely accessible on 32-bit 19 * architectures, however. Registers were organized such 20 * that (a) they can be contained in 32 bits, (b) if not, then they 21 * can be treated as two 32-bit entities, or finally (c) if they 22 * must be treated as a single 64-bit value, then this can safely 23 * be done with two 32-bit cycles. 24 * 25 * For 32-bit operations on 64-bit values, CAAM follows the same 26 * 64-bit register access conventions as it's predecessors, in that 27 * writes are "triggered" by a write to the register at the numerically 28 * higher address, thus, a full 64-bit write cycle requires a write 29 * to the lower address, followed by a write to the higher address, 30 * which will latch/execute the write cycle. 31 * 32 * For example, let's assume a SW reset of CAAM through the master 33 * configuration register. 34 * - SWRST is in bit 31 of MCFG. 35 * - MCFG begins at base+0x0000. 36 * - Bits 63-32 are a 32-bit word at base+0x0000 (numerically-lower) 37 * - Bits 31-0 are a 32-bit word at base+0x0004 (numerically-higher) 38 * 39 * (and on Power, the convention is 0-31, 32-63, I know...) 40 * 41 * Assuming a 64-bit write to this MCFG to perform a software reset 42 * would then require a write of 0 to base+0x0000, followed by a 43 * write of 0x80000000 to base+0x0004, which would "execute" the 44 * reset. 45 * 46 * Of course, since MCFG 63-32 is all zero, we could cheat and simply 47 * write 0x8000000 to base+0x0004, and the reset would work fine. 48 * However, since CAAM does contain some write-and-read-intended 49 * 64-bit registers, this code defines 64-bit access methods for 50 * the sake of internal consistency and simplicity, and so that a 51 * clean transition to 64-bit is possible when it becomes necessary. 52 * 53 * There are limitations to this that the developer must recognize. 54 * 32-bit architectures cannot enforce an atomic-64 operation, 55 * Therefore: 56 * 57 * - On writes, since the HW is assumed to latch the cycle on the 58 * write of the higher-numeric-address word, then ordered 59 * writes work OK. 60 * 61 * - For reads, where a register contains a relevant value of more 62 * that 32 bits, the hardware employs logic to latch the other 63 * "half" of the data until read, ensuring an accurate value. 64 * This is of particular relevance when dealing with CAAM's 65 * performance counters. 66 * 67 */ 68 69 extern bool caam_little_end; 70 extern bool caam_imx; 71 72 #define caam_to_cpu(len) \ 73 static inline u##len caam##len ## _to_cpu(u##len val) \ 74 { \ 75 if (caam_little_end) \ 76 return le##len ## _to_cpu(val); \ 77 else \ 78 return be##len ## _to_cpu(val); \ 79 } 80 81 #define cpu_to_caam(len) \ 82 static inline u##len cpu_to_caam##len(u##len val) \ 83 { \ 84 if (caam_little_end) \ 85 return cpu_to_le##len(val); \ 86 else \ 87 return cpu_to_be##len(val); \ 88 } 89 90 caam_to_cpu(16) 91 caam_to_cpu(32) 92 caam_to_cpu(64) 93 cpu_to_caam(16) 94 cpu_to_caam(32) 95 cpu_to_caam(64) 96 97 static inline void wr_reg32(void __iomem *reg, u32 data) 98 { 99 if (caam_little_end) 100 iowrite32(data, reg); 101 else 102 iowrite32be(data, reg); 103 } 104 105 static inline u32 rd_reg32(void __iomem *reg) 106 { 107 if (caam_little_end) 108 return ioread32(reg); 109 110 return ioread32be(reg); 111 } 112 113 static inline void clrsetbits_32(void __iomem *reg, u32 clear, u32 set) 114 { 115 if (caam_little_end) 116 iowrite32((ioread32(reg) & ~clear) | set, reg); 117 else 118 iowrite32be((ioread32be(reg) & ~clear) | set, reg); 119 } 120 121 /* 122 * The only users of these wr/rd_reg64 functions is the Job Ring (JR). 123 * The DMA address registers in the JR are handled differently depending on 124 * platform: 125 * 126 * 1. All BE CAAM platforms and i.MX platforms (LE CAAM): 127 * 128 * base + 0x0000 : most-significant 32 bits 129 * base + 0x0004 : least-significant 32 bits 130 * 131 * The 32-bit version of this core therefore has to write to base + 0x0004 132 * to set the 32-bit wide DMA address. 133 * 134 * 2. All other LE CAAM platforms (LS1021A etc.) 135 * base + 0x0000 : least-significant 32 bits 136 * base + 0x0004 : most-significant 32 bits 137 */ 138 #ifdef CONFIG_64BIT 139 static inline void wr_reg64(void __iomem *reg, u64 data) 140 { 141 if (caam_little_end) 142 iowrite64(data, reg); 143 else 144 iowrite64be(data, reg); 145 } 146 147 static inline u64 rd_reg64(void __iomem *reg) 148 { 149 if (caam_little_end) 150 return ioread64(reg); 151 else 152 return ioread64be(reg); 153 } 154 155 #else /* CONFIG_64BIT */ 156 static inline void wr_reg64(void __iomem *reg, u64 data) 157 { 158 if (!caam_imx && caam_little_end) { 159 wr_reg32((u32 __iomem *)(reg) + 1, data >> 32); 160 wr_reg32((u32 __iomem *)(reg), data); 161 } else { 162 wr_reg32((u32 __iomem *)(reg), data >> 32); 163 wr_reg32((u32 __iomem *)(reg) + 1, data); 164 } 165 } 166 167 static inline u64 rd_reg64(void __iomem *reg) 168 { 169 if (!caam_imx && caam_little_end) 170 return ((u64)rd_reg32((u32 __iomem *)(reg) + 1) << 32 | 171 (u64)rd_reg32((u32 __iomem *)(reg))); 172 173 return ((u64)rd_reg32((u32 __iomem *)(reg)) << 32 | 174 (u64)rd_reg32((u32 __iomem *)(reg) + 1)); 175 } 176 #endif /* CONFIG_64BIT */ 177 178 static inline u64 cpu_to_caam_dma64(dma_addr_t value) 179 { 180 if (caam_imx) 181 return (((u64)cpu_to_caam32(lower_32_bits(value)) << 32) | 182 (u64)cpu_to_caam32(upper_32_bits(value))); 183 184 return cpu_to_caam64(value); 185 } 186 187 static inline u64 caam_dma64_to_cpu(u64 value) 188 { 189 if (caam_imx) 190 return (((u64)caam32_to_cpu(lower_32_bits(value)) << 32) | 191 (u64)caam32_to_cpu(upper_32_bits(value))); 192 193 return caam64_to_cpu(value); 194 } 195 196 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 197 #define cpu_to_caam_dma(value) cpu_to_caam_dma64(value) 198 #define caam_dma_to_cpu(value) caam_dma64_to_cpu(value) 199 #else 200 #define cpu_to_caam_dma(value) cpu_to_caam32(value) 201 #define caam_dma_to_cpu(value) caam32_to_cpu(value) 202 #endif /* CONFIG_ARCH_DMA_ADDR_T_64BIT */ 203 204 /* 205 * jr_outentry 206 * Represents each entry in a JobR output ring 207 */ 208 struct jr_outentry { 209 dma_addr_t desc;/* Pointer to completed descriptor */ 210 u32 jrstatus; /* Status for completed descriptor */ 211 } __packed; 212 213 /* 214 * caam_perfmon - Performance Monitor/Secure Memory Status/ 215 * CAAM Global Status/Component Version IDs 216 * 217 * Spans f00-fff wherever instantiated 218 */ 219 220 /* Number of DECOs */ 221 #define CHA_NUM_MS_DECONUM_SHIFT 24 222 #define CHA_NUM_MS_DECONUM_MASK (0xfull << CHA_NUM_MS_DECONUM_SHIFT) 223 224 /* 225 * CHA version IDs / instantiation bitfields 226 * Defined for use with the cha_id fields in perfmon, but the same shift/mask 227 * selectors can be used to pull out the number of instantiated blocks within 228 * cha_num fields in perfmon because the locations are the same. 229 */ 230 #define CHA_ID_LS_AES_SHIFT 0 231 #define CHA_ID_LS_AES_MASK (0xfull << CHA_ID_LS_AES_SHIFT) 232 #define CHA_ID_LS_AES_LP (0x3ull << CHA_ID_LS_AES_SHIFT) 233 #define CHA_ID_LS_AES_HP (0x4ull << CHA_ID_LS_AES_SHIFT) 234 235 #define CHA_ID_LS_DES_SHIFT 4 236 #define CHA_ID_LS_DES_MASK (0xfull << CHA_ID_LS_DES_SHIFT) 237 238 #define CHA_ID_LS_ARC4_SHIFT 8 239 #define CHA_ID_LS_ARC4_MASK (0xfull << CHA_ID_LS_ARC4_SHIFT) 240 241 #define CHA_ID_LS_MD_SHIFT 12 242 #define CHA_ID_LS_MD_MASK (0xfull << CHA_ID_LS_MD_SHIFT) 243 #define CHA_ID_LS_MD_LP256 (0x0ull << CHA_ID_LS_MD_SHIFT) 244 #define CHA_ID_LS_MD_LP512 (0x1ull << CHA_ID_LS_MD_SHIFT) 245 #define CHA_ID_LS_MD_HP (0x2ull << CHA_ID_LS_MD_SHIFT) 246 247 #define CHA_ID_LS_RNG_SHIFT 16 248 #define CHA_ID_LS_RNG_MASK (0xfull << CHA_ID_LS_RNG_SHIFT) 249 250 #define CHA_ID_LS_SNW8_SHIFT 20 251 #define CHA_ID_LS_SNW8_MASK (0xfull << CHA_ID_LS_SNW8_SHIFT) 252 253 #define CHA_ID_LS_KAS_SHIFT 24 254 #define CHA_ID_LS_KAS_MASK (0xfull << CHA_ID_LS_KAS_SHIFT) 255 256 #define CHA_ID_LS_PK_SHIFT 28 257 #define CHA_ID_LS_PK_MASK (0xfull << CHA_ID_LS_PK_SHIFT) 258 259 #define CHA_ID_MS_CRC_SHIFT 0 260 #define CHA_ID_MS_CRC_MASK (0xfull << CHA_ID_MS_CRC_SHIFT) 261 262 #define CHA_ID_MS_SNW9_SHIFT 4 263 #define CHA_ID_MS_SNW9_MASK (0xfull << CHA_ID_MS_SNW9_SHIFT) 264 265 #define CHA_ID_MS_DECO_SHIFT 24 266 #define CHA_ID_MS_DECO_MASK (0xfull << CHA_ID_MS_DECO_SHIFT) 267 268 #define CHA_ID_MS_JR_SHIFT 28 269 #define CHA_ID_MS_JR_MASK (0xfull << CHA_ID_MS_JR_SHIFT) 270 271 struct sec_vid { 272 u16 ip_id; 273 u8 maj_rev; 274 u8 min_rev; 275 }; 276 277 struct caam_perfmon { 278 /* Performance Monitor Registers f00-f9f */ 279 u64 req_dequeued; /* PC_REQ_DEQ - Dequeued Requests */ 280 u64 ob_enc_req; /* PC_OB_ENC_REQ - Outbound Encrypt Requests */ 281 u64 ib_dec_req; /* PC_IB_DEC_REQ - Inbound Decrypt Requests */ 282 u64 ob_enc_bytes; /* PC_OB_ENCRYPT - Outbound Bytes Encrypted */ 283 u64 ob_prot_bytes; /* PC_OB_PROTECT - Outbound Bytes Protected */ 284 u64 ib_dec_bytes; /* PC_IB_DECRYPT - Inbound Bytes Decrypted */ 285 u64 ib_valid_bytes; /* PC_IB_VALIDATED Inbound Bytes Validated */ 286 u64 rsvd[13]; 287 288 /* CAAM Hardware Instantiation Parameters fa0-fbf */ 289 u32 cha_rev_ms; /* CRNR - CHA Rev No. Most significant half*/ 290 u32 cha_rev_ls; /* CRNR - CHA Rev No. Least significant half*/ 291 #define CTPR_MS_QI_SHIFT 25 292 #define CTPR_MS_QI_MASK (0x1ull << CTPR_MS_QI_SHIFT) 293 #define CTPR_MS_DPAA2 BIT(13) 294 #define CTPR_MS_VIRT_EN_INCL 0x00000001 295 #define CTPR_MS_VIRT_EN_POR 0x00000002 296 #define CTPR_MS_PG_SZ_MASK 0x10 297 #define CTPR_MS_PG_SZ_SHIFT 4 298 u32 comp_parms_ms; /* CTPR - Compile Parameters Register */ 299 u32 comp_parms_ls; /* CTPR - Compile Parameters Register */ 300 u64 rsvd1[2]; 301 302 /* CAAM Global Status fc0-fdf */ 303 u64 faultaddr; /* FAR - Fault Address */ 304 u32 faultliodn; /* FALR - Fault Address LIODN */ 305 u32 faultdetail; /* FADR - Fault Addr Detail */ 306 u32 rsvd2; 307 #define CSTA_PLEND BIT(10) 308 #define CSTA_ALT_PLEND BIT(18) 309 u32 status; /* CSTA - CAAM Status */ 310 u64 rsvd3; 311 312 /* Component Instantiation Parameters fe0-fff */ 313 u32 rtic_id; /* RVID - RTIC Version ID */ 314 u32 ccb_id; /* CCBVID - CCB Version ID */ 315 u32 cha_id_ms; /* CHAVID - CHA Version ID Most Significant*/ 316 u32 cha_id_ls; /* CHAVID - CHA Version ID Least Significant*/ 317 u32 cha_num_ms; /* CHANUM - CHA Number Most Significant */ 318 u32 cha_num_ls; /* CHANUM - CHA Number Least Significant*/ 319 u32 caam_id_ms; /* CAAMVID - CAAM Version ID MS */ 320 u32 caam_id_ls; /* CAAMVID - CAAM Version ID LS */ 321 }; 322 323 /* LIODN programming for DMA configuration */ 324 #define MSTRID_LOCK_LIODN 0x80000000 325 #define MSTRID_LOCK_MAKETRUSTED 0x00010000 /* only for JR masterid */ 326 327 #define MSTRID_LIODN_MASK 0x0fff 328 struct masterid { 329 u32 liodn_ms; /* lock and make-trusted control bits */ 330 u32 liodn_ls; /* LIODN for non-sequence and seq access */ 331 }; 332 333 /* Partition ID for DMA configuration */ 334 struct partid { 335 u32 rsvd1; 336 u32 pidr; /* partition ID, DECO */ 337 }; 338 339 /* RNGB test mode (replicated twice in some configurations) */ 340 /* Padded out to 0x100 */ 341 struct rngtst { 342 u32 mode; /* RTSTMODEx - Test mode */ 343 u32 rsvd1[3]; 344 u32 reset; /* RTSTRESETx - Test reset control */ 345 u32 rsvd2[3]; 346 u32 status; /* RTSTSSTATUSx - Test status */ 347 u32 rsvd3; 348 u32 errstat; /* RTSTERRSTATx - Test error status */ 349 u32 rsvd4; 350 u32 errctl; /* RTSTERRCTLx - Test error control */ 351 u32 rsvd5; 352 u32 entropy; /* RTSTENTROPYx - Test entropy */ 353 u32 rsvd6[15]; 354 u32 verifctl; /* RTSTVERIFCTLx - Test verification control */ 355 u32 rsvd7; 356 u32 verifstat; /* RTSTVERIFSTATx - Test verification status */ 357 u32 rsvd8; 358 u32 verifdata; /* RTSTVERIFDx - Test verification data */ 359 u32 rsvd9; 360 u32 xkey; /* RTSTXKEYx - Test XKEY */ 361 u32 rsvd10; 362 u32 oscctctl; /* RTSTOSCCTCTLx - Test osc. counter control */ 363 u32 rsvd11; 364 u32 oscct; /* RTSTOSCCTx - Test oscillator counter */ 365 u32 rsvd12; 366 u32 oscctstat; /* RTSTODCCTSTATx - Test osc counter status */ 367 u32 rsvd13[2]; 368 u32 ofifo[4]; /* RTSTOFIFOx - Test output FIFO */ 369 u32 rsvd14[15]; 370 }; 371 372 /* RNG4 TRNG test registers */ 373 struct rng4tst { 374 #define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */ 375 #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC 0 /* use von Neumann data in 376 both entropy shifter and 377 statistical checker */ 378 #define RTMCTL_SAMP_MODE_RAW_ES_SC 1 /* use raw data in both 379 entropy shifter and 380 statistical checker */ 381 #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC 2 /* use von Neumann data in 382 entropy shifter, raw data 383 in statistical checker */ 384 #define RTMCTL_SAMP_MODE_INVALID 3 /* invalid combination */ 385 u32 rtmctl; /* misc. control register */ 386 u32 rtscmisc; /* statistical check misc. register */ 387 u32 rtpkrrng; /* poker range register */ 388 union { 389 u32 rtpkrmax; /* PRGM=1: poker max. limit register */ 390 u32 rtpkrsq; /* PRGM=0: poker square calc. result register */ 391 }; 392 #define RTSDCTL_ENT_DLY_SHIFT 16 393 #define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT) 394 #define RTSDCTL_ENT_DLY_MIN 3200 395 #define RTSDCTL_ENT_DLY_MAX 12800 396 u32 rtsdctl; /* seed control register */ 397 union { 398 u32 rtsblim; /* PRGM=1: sparse bit limit register */ 399 u32 rttotsam; /* PRGM=0: total samples register */ 400 }; 401 u32 rtfrqmin; /* frequency count min. limit register */ 402 #define RTFRQMAX_DISABLE (1 << 20) 403 union { 404 u32 rtfrqmax; /* PRGM=1: freq. count max. limit register */ 405 u32 rtfrqcnt; /* PRGM=0: freq. count register */ 406 }; 407 u32 rsvd1[40]; 408 #define RDSTA_SKVT 0x80000000 409 #define RDSTA_SKVN 0x40000000 410 #define RDSTA_IF0 0x00000001 411 #define RDSTA_IF1 0x00000002 412 #define RDSTA_IFMASK (RDSTA_IF1 | RDSTA_IF0) 413 u32 rdsta; 414 u32 rsvd2[15]; 415 }; 416 417 /* 418 * caam_ctrl - basic core configuration 419 * starts base + 0x0000 padded out to 0x1000 420 */ 421 422 #define KEK_KEY_SIZE 8 423 #define TKEK_KEY_SIZE 8 424 #define TDSK_KEY_SIZE 8 425 426 #define DECO_RESET 1 /* Use with DECO reset/availability regs */ 427 #define DECO_RESET_0 (DECO_RESET << 0) 428 #define DECO_RESET_1 (DECO_RESET << 1) 429 #define DECO_RESET_2 (DECO_RESET << 2) 430 #define DECO_RESET_3 (DECO_RESET << 3) 431 #define DECO_RESET_4 (DECO_RESET << 4) 432 433 struct caam_ctrl { 434 /* Basic Configuration Section 000-01f */ 435 /* Read/Writable */ 436 u32 rsvd1; 437 u32 mcr; /* MCFG Master Config Register */ 438 u32 rsvd2; 439 u32 scfgr; /* SCFGR, Security Config Register */ 440 441 /* Bus Access Configuration Section 010-11f */ 442 /* Read/Writable */ 443 struct masterid jr_mid[4]; /* JRxLIODNR - JobR LIODN setup */ 444 u32 rsvd3[11]; 445 u32 jrstart; /* JRSTART - Job Ring Start Register */ 446 struct masterid rtic_mid[4]; /* RTICxLIODNR - RTIC LIODN setup */ 447 u32 rsvd4[5]; 448 u32 deco_rsr; /* DECORSR - Deco Request Source */ 449 u32 rsvd11; 450 u32 deco_rq; /* DECORR - DECO Request */ 451 struct partid deco_mid[5]; /* DECOxLIODNR - 1 per DECO */ 452 u32 rsvd5[22]; 453 454 /* DECO Availability/Reset Section 120-3ff */ 455 u32 deco_avail; /* DAR - DECO availability */ 456 u32 deco_reset; /* DRR - DECO reset */ 457 u32 rsvd6[182]; 458 459 /* Key Encryption/Decryption Configuration 400-5ff */ 460 /* Read/Writable only while in Non-secure mode */ 461 u32 kek[KEK_KEY_SIZE]; /* JDKEKR - Key Encryption Key */ 462 u32 tkek[TKEK_KEY_SIZE]; /* TDKEKR - Trusted Desc KEK */ 463 u32 tdsk[TDSK_KEY_SIZE]; /* TDSKR - Trusted Desc Signing Key */ 464 u32 rsvd7[32]; 465 u64 sknonce; /* SKNR - Secure Key Nonce */ 466 u32 rsvd8[70]; 467 468 /* RNG Test/Verification/Debug Access 600-7ff */ 469 /* (Useful in Test/Debug modes only...) */ 470 union { 471 struct rngtst rtst[2]; 472 struct rng4tst r4tst[2]; 473 }; 474 475 u32 rsvd9[448]; 476 477 /* Performance Monitor f00-fff */ 478 struct caam_perfmon perfmon; 479 }; 480 481 /* 482 * Controller master config register defs 483 */ 484 #define MCFGR_SWRESET 0x80000000 /* software reset */ 485 #define MCFGR_WDENABLE 0x40000000 /* DECO watchdog enable */ 486 #define MCFGR_WDFAIL 0x20000000 /* DECO watchdog force-fail */ 487 #define MCFGR_DMA_RESET 0x10000000 488 #define MCFGR_LONG_PTR 0x00010000 /* Use >32-bit desc addressing */ 489 #define SCFGR_RDBENABLE 0x00000400 490 #define SCFGR_VIRT_EN 0x00008000 491 #define DECORR_RQD0ENABLE 0x00000001 /* Enable DECO0 for direct access */ 492 #define DECORSR_JR0 0x00000001 /* JR to supply TZ, SDID, ICID */ 493 #define DECORSR_VALID 0x80000000 494 #define DECORR_DEN0 0x00010000 /* DECO0 available for access*/ 495 496 /* AXI read cache control */ 497 #define MCFGR_ARCACHE_SHIFT 12 498 #define MCFGR_ARCACHE_MASK (0xf << MCFGR_ARCACHE_SHIFT) 499 #define MCFGR_ARCACHE_BUFF (0x1 << MCFGR_ARCACHE_SHIFT) 500 #define MCFGR_ARCACHE_CACH (0x2 << MCFGR_ARCACHE_SHIFT) 501 #define MCFGR_ARCACHE_RALL (0x4 << MCFGR_ARCACHE_SHIFT) 502 503 /* AXI write cache control */ 504 #define MCFGR_AWCACHE_SHIFT 8 505 #define MCFGR_AWCACHE_MASK (0xf << MCFGR_AWCACHE_SHIFT) 506 #define MCFGR_AWCACHE_BUFF (0x1 << MCFGR_AWCACHE_SHIFT) 507 #define MCFGR_AWCACHE_CACH (0x2 << MCFGR_AWCACHE_SHIFT) 508 #define MCFGR_AWCACHE_WALL (0x8 << MCFGR_AWCACHE_SHIFT) 509 510 /* AXI pipeline depth */ 511 #define MCFGR_AXIPIPE_SHIFT 4 512 #define MCFGR_AXIPIPE_MASK (0xf << MCFGR_AXIPIPE_SHIFT) 513 514 #define MCFGR_AXIPRI 0x00000008 /* Assert AXI priority sideband */ 515 #define MCFGR_LARGE_BURST 0x00000004 /* 128/256-byte burst size */ 516 #define MCFGR_BURST_64 0x00000001 /* 64-byte burst size */ 517 518 /* JRSTART register offsets */ 519 #define JRSTART_JR0_START 0x00000001 /* Start Job ring 0 */ 520 #define JRSTART_JR1_START 0x00000002 /* Start Job ring 1 */ 521 #define JRSTART_JR2_START 0x00000004 /* Start Job ring 2 */ 522 #define JRSTART_JR3_START 0x00000008 /* Start Job ring 3 */ 523 524 /* 525 * caam_job_ring - direct job ring setup 526 * 1-4 possible per instantiation, base + 1000/2000/3000/4000 527 * Padded out to 0x1000 528 */ 529 struct caam_job_ring { 530 /* Input ring */ 531 u64 inpring_base; /* IRBAx - Input desc ring baseaddr */ 532 u32 rsvd1; 533 u32 inpring_size; /* IRSx - Input ring size */ 534 u32 rsvd2; 535 u32 inpring_avail; /* IRSAx - Input ring room remaining */ 536 u32 rsvd3; 537 u32 inpring_jobadd; /* IRJAx - Input ring jobs added */ 538 539 /* Output Ring */ 540 u64 outring_base; /* ORBAx - Output status ring base addr */ 541 u32 rsvd4; 542 u32 outring_size; /* ORSx - Output ring size */ 543 u32 rsvd5; 544 u32 outring_rmvd; /* ORJRx - Output ring jobs removed */ 545 u32 rsvd6; 546 u32 outring_used; /* ORSFx - Output ring slots full */ 547 548 /* Status/Configuration */ 549 u32 rsvd7; 550 u32 jroutstatus; /* JRSTAx - JobR output status */ 551 u32 rsvd8; 552 u32 jrintstatus; /* JRINTx - JobR interrupt status */ 553 u32 rconfig_hi; /* JRxCFG - Ring configuration */ 554 u32 rconfig_lo; 555 556 /* Indices. CAAM maintains as "heads" of each queue */ 557 u32 rsvd9; 558 u32 inp_rdidx; /* IRRIx - Input ring read index */ 559 u32 rsvd10; 560 u32 out_wtidx; /* ORWIx - Output ring write index */ 561 562 /* Command/control */ 563 u32 rsvd11; 564 u32 jrcommand; /* JRCRx - JobR command */ 565 566 u32 rsvd12[932]; 567 568 /* Performance Monitor f00-fff */ 569 struct caam_perfmon perfmon; 570 }; 571 572 #define JR_RINGSIZE_MASK 0x03ff 573 /* 574 * jrstatus - Job Ring Output Status 575 * All values in lo word 576 * Also note, same values written out as status through QI 577 * in the command/status field of a frame descriptor 578 */ 579 #define JRSTA_SSRC_SHIFT 28 580 #define JRSTA_SSRC_MASK 0xf0000000 581 582 #define JRSTA_SSRC_NONE 0x00000000 583 #define JRSTA_SSRC_CCB_ERROR 0x20000000 584 #define JRSTA_SSRC_JUMP_HALT_USER 0x30000000 585 #define JRSTA_SSRC_DECO 0x40000000 586 #define JRSTA_SSRC_JRERROR 0x60000000 587 #define JRSTA_SSRC_JUMP_HALT_CC 0x70000000 588 589 #define JRSTA_DECOERR_JUMP 0x08000000 590 #define JRSTA_DECOERR_INDEX_SHIFT 8 591 #define JRSTA_DECOERR_INDEX_MASK 0xff00 592 #define JRSTA_DECOERR_ERROR_MASK 0x00ff 593 594 #define JRSTA_DECOERR_NONE 0x00 595 #define JRSTA_DECOERR_LINKLEN 0x01 596 #define JRSTA_DECOERR_LINKPTR 0x02 597 #define JRSTA_DECOERR_JRCTRL 0x03 598 #define JRSTA_DECOERR_DESCCMD 0x04 599 #define JRSTA_DECOERR_ORDER 0x05 600 #define JRSTA_DECOERR_KEYCMD 0x06 601 #define JRSTA_DECOERR_LOADCMD 0x07 602 #define JRSTA_DECOERR_STORECMD 0x08 603 #define JRSTA_DECOERR_OPCMD 0x09 604 #define JRSTA_DECOERR_FIFOLDCMD 0x0a 605 #define JRSTA_DECOERR_FIFOSTCMD 0x0b 606 #define JRSTA_DECOERR_MOVECMD 0x0c 607 #define JRSTA_DECOERR_JUMPCMD 0x0d 608 #define JRSTA_DECOERR_MATHCMD 0x0e 609 #define JRSTA_DECOERR_SHASHCMD 0x0f 610 #define JRSTA_DECOERR_SEQCMD 0x10 611 #define JRSTA_DECOERR_DECOINTERNAL 0x11 612 #define JRSTA_DECOERR_SHDESCHDR 0x12 613 #define JRSTA_DECOERR_HDRLEN 0x13 614 #define JRSTA_DECOERR_BURSTER 0x14 615 #define JRSTA_DECOERR_DESCSIGNATURE 0x15 616 #define JRSTA_DECOERR_DMA 0x16 617 #define JRSTA_DECOERR_BURSTFIFO 0x17 618 #define JRSTA_DECOERR_JRRESET 0x1a 619 #define JRSTA_DECOERR_JOBFAIL 0x1b 620 #define JRSTA_DECOERR_DNRERR 0x80 621 #define JRSTA_DECOERR_UNDEFPCL 0x81 622 #define JRSTA_DECOERR_PDBERR 0x82 623 #define JRSTA_DECOERR_ANRPLY_LATE 0x83 624 #define JRSTA_DECOERR_ANRPLY_REPLAY 0x84 625 #define JRSTA_DECOERR_SEQOVF 0x85 626 #define JRSTA_DECOERR_INVSIGN 0x86 627 #define JRSTA_DECOERR_DSASIGN 0x87 628 629 #define JRSTA_CCBERR_JUMP 0x08000000 630 #define JRSTA_CCBERR_INDEX_MASK 0xff00 631 #define JRSTA_CCBERR_INDEX_SHIFT 8 632 #define JRSTA_CCBERR_CHAID_MASK 0x00f0 633 #define JRSTA_CCBERR_CHAID_SHIFT 4 634 #define JRSTA_CCBERR_ERRID_MASK 0x000f 635 636 #define JRSTA_CCBERR_CHAID_AES (0x01 << JRSTA_CCBERR_CHAID_SHIFT) 637 #define JRSTA_CCBERR_CHAID_DES (0x02 << JRSTA_CCBERR_CHAID_SHIFT) 638 #define JRSTA_CCBERR_CHAID_ARC4 (0x03 << JRSTA_CCBERR_CHAID_SHIFT) 639 #define JRSTA_CCBERR_CHAID_MD (0x04 << JRSTA_CCBERR_CHAID_SHIFT) 640 #define JRSTA_CCBERR_CHAID_RNG (0x05 << JRSTA_CCBERR_CHAID_SHIFT) 641 #define JRSTA_CCBERR_CHAID_SNOW (0x06 << JRSTA_CCBERR_CHAID_SHIFT) 642 #define JRSTA_CCBERR_CHAID_KASUMI (0x07 << JRSTA_CCBERR_CHAID_SHIFT) 643 #define JRSTA_CCBERR_CHAID_PK (0x08 << JRSTA_CCBERR_CHAID_SHIFT) 644 #define JRSTA_CCBERR_CHAID_CRC (0x09 << JRSTA_CCBERR_CHAID_SHIFT) 645 646 #define JRSTA_CCBERR_ERRID_NONE 0x00 647 #define JRSTA_CCBERR_ERRID_MODE 0x01 648 #define JRSTA_CCBERR_ERRID_DATASIZ 0x02 649 #define JRSTA_CCBERR_ERRID_KEYSIZ 0x03 650 #define JRSTA_CCBERR_ERRID_PKAMEMSZ 0x04 651 #define JRSTA_CCBERR_ERRID_PKBMEMSZ 0x05 652 #define JRSTA_CCBERR_ERRID_SEQUENCE 0x06 653 #define JRSTA_CCBERR_ERRID_PKDIVZRO 0x07 654 #define JRSTA_CCBERR_ERRID_PKMODEVN 0x08 655 #define JRSTA_CCBERR_ERRID_KEYPARIT 0x09 656 #define JRSTA_CCBERR_ERRID_ICVCHK 0x0a 657 #define JRSTA_CCBERR_ERRID_HARDWARE 0x0b 658 #define JRSTA_CCBERR_ERRID_CCMAAD 0x0c 659 #define JRSTA_CCBERR_ERRID_INVCHA 0x0f 660 661 #define JRINT_ERR_INDEX_MASK 0x3fff0000 662 #define JRINT_ERR_INDEX_SHIFT 16 663 #define JRINT_ERR_TYPE_MASK 0xf00 664 #define JRINT_ERR_TYPE_SHIFT 8 665 #define JRINT_ERR_HALT_MASK 0xc 666 #define JRINT_ERR_HALT_SHIFT 2 667 #define JRINT_ERR_HALT_INPROGRESS 0x4 668 #define JRINT_ERR_HALT_COMPLETE 0x8 669 #define JRINT_JR_ERROR 0x02 670 #define JRINT_JR_INT 0x01 671 672 #define JRINT_ERR_TYPE_WRITE 1 673 #define JRINT_ERR_TYPE_BAD_INPADDR 3 674 #define JRINT_ERR_TYPE_BAD_OUTADDR 4 675 #define JRINT_ERR_TYPE_INV_INPWRT 5 676 #define JRINT_ERR_TYPE_INV_OUTWRT 6 677 #define JRINT_ERR_TYPE_RESET 7 678 #define JRINT_ERR_TYPE_REMOVE_OFL 8 679 #define JRINT_ERR_TYPE_ADD_OFL 9 680 681 #define JRCFG_SOE 0x04 682 #define JRCFG_ICEN 0x02 683 #define JRCFG_IMSK 0x01 684 #define JRCFG_ICDCT_SHIFT 8 685 #define JRCFG_ICTT_SHIFT 16 686 687 #define JRCR_RESET 0x01 688 689 /* 690 * caam_assurance - Assurance Controller View 691 * base + 0x6000 padded out to 0x1000 692 */ 693 694 struct rtic_element { 695 u64 address; 696 u32 rsvd; 697 u32 length; 698 }; 699 700 struct rtic_block { 701 struct rtic_element element[2]; 702 }; 703 704 struct rtic_memhash { 705 u32 memhash_be[32]; 706 u32 memhash_le[32]; 707 }; 708 709 struct caam_assurance { 710 /* Status/Command/Watchdog */ 711 u32 rsvd1; 712 u32 status; /* RSTA - Status */ 713 u32 rsvd2; 714 u32 cmd; /* RCMD - Command */ 715 u32 rsvd3; 716 u32 ctrl; /* RCTL - Control */ 717 u32 rsvd4; 718 u32 throttle; /* RTHR - Throttle */ 719 u32 rsvd5[2]; 720 u64 watchdog; /* RWDOG - Watchdog Timer */ 721 u32 rsvd6; 722 u32 rend; /* REND - Endian corrections */ 723 u32 rsvd7[50]; 724 725 /* Block access/configuration @ 100/110/120/130 */ 726 struct rtic_block memblk[4]; /* Memory Blocks A-D */ 727 u32 rsvd8[32]; 728 729 /* Block hashes @ 200/300/400/500 */ 730 struct rtic_memhash hash[4]; /* Block hash values A-D */ 731 u32 rsvd_3[640]; 732 }; 733 734 /* 735 * caam_queue_if - QI configuration and control 736 * starts base + 0x7000, padded out to 0x1000 long 737 */ 738 739 struct caam_queue_if { 740 u32 qi_control_hi; /* QICTL - QI Control */ 741 u32 qi_control_lo; 742 u32 rsvd1; 743 u32 qi_status; /* QISTA - QI Status */ 744 u32 qi_deq_cfg_hi; /* QIDQC - QI Dequeue Configuration */ 745 u32 qi_deq_cfg_lo; 746 u32 qi_enq_cfg_hi; /* QISEQC - QI Enqueue Command */ 747 u32 qi_enq_cfg_lo; 748 u32 rsvd2[1016]; 749 }; 750 751 /* QI control bits - low word */ 752 #define QICTL_DQEN 0x01 /* Enable frame pop */ 753 #define QICTL_STOP 0x02 /* Stop dequeue/enqueue */ 754 #define QICTL_SOE 0x04 /* Stop on error */ 755 756 /* QI control bits - high word */ 757 #define QICTL_MBSI 0x01 758 #define QICTL_MHWSI 0x02 759 #define QICTL_MWSI 0x04 760 #define QICTL_MDWSI 0x08 761 #define QICTL_CBSI 0x10 /* CtrlDataByteSwapInput */ 762 #define QICTL_CHWSI 0x20 /* CtrlDataHalfSwapInput */ 763 #define QICTL_CWSI 0x40 /* CtrlDataWordSwapInput */ 764 #define QICTL_CDWSI 0x80 /* CtrlDataDWordSwapInput */ 765 #define QICTL_MBSO 0x0100 766 #define QICTL_MHWSO 0x0200 767 #define QICTL_MWSO 0x0400 768 #define QICTL_MDWSO 0x0800 769 #define QICTL_CBSO 0x1000 /* CtrlDataByteSwapOutput */ 770 #define QICTL_CHWSO 0x2000 /* CtrlDataHalfSwapOutput */ 771 #define QICTL_CWSO 0x4000 /* CtrlDataWordSwapOutput */ 772 #define QICTL_CDWSO 0x8000 /* CtrlDataDWordSwapOutput */ 773 #define QICTL_DMBS 0x010000 774 #define QICTL_EPO 0x020000 775 776 /* QI status bits */ 777 #define QISTA_PHRDERR 0x01 /* PreHeader Read Error */ 778 #define QISTA_CFRDERR 0x02 /* Compound Frame Read Error */ 779 #define QISTA_OFWRERR 0x04 /* Output Frame Read Error */ 780 #define QISTA_BPDERR 0x08 /* Buffer Pool Depleted */ 781 #define QISTA_BTSERR 0x10 /* Buffer Undersize */ 782 #define QISTA_CFWRERR 0x20 /* Compound Frame Write Err */ 783 #define QISTA_STOPD 0x80000000 /* QI Stopped (see QICTL) */ 784 785 /* deco_sg_table - DECO view of scatter/gather table */ 786 struct deco_sg_table { 787 u64 addr; /* Segment Address */ 788 u32 elen; /* E, F bits + 30-bit length */ 789 u32 bpid_offset; /* Buffer Pool ID + 16-bit length */ 790 }; 791 792 /* 793 * caam_deco - descriptor controller - CHA cluster block 794 * 795 * Only accessible when direct DECO access is turned on 796 * (done in DECORR, via MID programmed in DECOxMID 797 * 798 * 5 typical, base + 0x8000/9000/a000/b000 799 * Padded out to 0x1000 long 800 */ 801 struct caam_deco { 802 u32 rsvd1; 803 u32 cls1_mode; /* CxC1MR - Class 1 Mode */ 804 u32 rsvd2; 805 u32 cls1_keysize; /* CxC1KSR - Class 1 Key Size */ 806 u32 cls1_datasize_hi; /* CxC1DSR - Class 1 Data Size */ 807 u32 cls1_datasize_lo; 808 u32 rsvd3; 809 u32 cls1_icvsize; /* CxC1ICVSR - Class 1 ICV size */ 810 u32 rsvd4[5]; 811 u32 cha_ctrl; /* CCTLR - CHA control */ 812 u32 rsvd5; 813 u32 irq_crtl; /* CxCIRQ - CCB interrupt done/error/clear */ 814 u32 rsvd6; 815 u32 clr_written; /* CxCWR - Clear-Written */ 816 u32 ccb_status_hi; /* CxCSTA - CCB Status/Error */ 817 u32 ccb_status_lo; 818 u32 rsvd7[3]; 819 u32 aad_size; /* CxAADSZR - Current AAD Size */ 820 u32 rsvd8; 821 u32 cls1_iv_size; /* CxC1IVSZR - Current Class 1 IV Size */ 822 u32 rsvd9[7]; 823 u32 pkha_a_size; /* PKASZRx - Size of PKHA A */ 824 u32 rsvd10; 825 u32 pkha_b_size; /* PKBSZRx - Size of PKHA B */ 826 u32 rsvd11; 827 u32 pkha_n_size; /* PKNSZRx - Size of PKHA N */ 828 u32 rsvd12; 829 u32 pkha_e_size; /* PKESZRx - Size of PKHA E */ 830 u32 rsvd13[24]; 831 u32 cls1_ctx[16]; /* CxC1CTXR - Class 1 Context @100 */ 832 u32 rsvd14[48]; 833 u32 cls1_key[8]; /* CxC1KEYR - Class 1 Key @200 */ 834 u32 rsvd15[121]; 835 u32 cls2_mode; /* CxC2MR - Class 2 Mode */ 836 u32 rsvd16; 837 u32 cls2_keysize; /* CxX2KSR - Class 2 Key Size */ 838 u32 cls2_datasize_hi; /* CxC2DSR - Class 2 Data Size */ 839 u32 cls2_datasize_lo; 840 u32 rsvd17; 841 u32 cls2_icvsize; /* CxC2ICVSZR - Class 2 ICV Size */ 842 u32 rsvd18[56]; 843 u32 cls2_ctx[18]; /* CxC2CTXR - Class 2 Context @500 */ 844 u32 rsvd19[46]; 845 u32 cls2_key[32]; /* CxC2KEYR - Class2 Key @600 */ 846 u32 rsvd20[84]; 847 u32 inp_infofifo_hi; /* CxIFIFO - Input Info FIFO @7d0 */ 848 u32 inp_infofifo_lo; 849 u32 rsvd21[2]; 850 u64 inp_datafifo; /* CxDFIFO - Input Data FIFO */ 851 u32 rsvd22[2]; 852 u64 out_datafifo; /* CxOFIFO - Output Data FIFO */ 853 u32 rsvd23[2]; 854 u32 jr_ctl_hi; /* CxJRR - JobR Control Register @800 */ 855 u32 jr_ctl_lo; 856 u64 jr_descaddr; /* CxDADR - JobR Descriptor Address */ 857 #define DECO_OP_STATUS_HI_ERR_MASK 0xF00000FF 858 u32 op_status_hi; /* DxOPSTA - DECO Operation Status */ 859 u32 op_status_lo; 860 u32 rsvd24[2]; 861 u32 liodn; /* DxLSR - DECO LIODN Status - non-seq */ 862 u32 td_liodn; /* DxLSR - DECO LIODN Status - trustdesc */ 863 u32 rsvd26[6]; 864 u64 math[4]; /* DxMTH - Math register */ 865 u32 rsvd27[8]; 866 struct deco_sg_table gthr_tbl[4]; /* DxGTR - Gather Tables */ 867 u32 rsvd28[16]; 868 struct deco_sg_table sctr_tbl[4]; /* DxSTR - Scatter Tables */ 869 u32 rsvd29[48]; 870 u32 descbuf[64]; /* DxDESB - Descriptor buffer */ 871 u32 rscvd30[193]; 872 #define DESC_DBG_DECO_STAT_HOST_ERR 0x00D00000 873 #define DESC_DBG_DECO_STAT_VALID 0x80000000 874 #define DESC_DBG_DECO_STAT_MASK 0x00F00000 875 u32 desc_dbg; /* DxDDR - DECO Debug Register */ 876 u32 rsvd31[126]; 877 }; 878 879 #define DECO_JQCR_WHL 0x20000000 880 #define DECO_JQCR_FOUR 0x10000000 881 882 #define JR_BLOCK_NUMBER 1 883 #define ASSURE_BLOCK_NUMBER 6 884 #define QI_BLOCK_NUMBER 7 885 #define DECO_BLOCK_NUMBER 8 886 #define PG_SIZE_4K 0x1000 887 #define PG_SIZE_64K 0x10000 888 #endif /* REGS_H */ 889