1 /* 2 * CAAM hardware register-level view 3 * 4 * Copyright 2008-2011 Freescale Semiconductor, Inc. 5 */ 6 7 #ifndef REGS_H 8 #define REGS_H 9 10 #include <linux/types.h> 11 #include <linux/io.h> 12 13 /* 14 * Architecture-specific register access methods 15 * 16 * CAAM's bus-addressable registers are 64 bits internally. 17 * They have been wired to be safely accessible on 32-bit 18 * architectures, however. Registers were organized such 19 * that (a) they can be contained in 32 bits, (b) if not, then they 20 * can be treated as two 32-bit entities, or finally (c) if they 21 * must be treated as a single 64-bit value, then this can safely 22 * be done with two 32-bit cycles. 23 * 24 * For 32-bit operations on 64-bit values, CAAM follows the same 25 * 64-bit register access conventions as it's predecessors, in that 26 * writes are "triggered" by a write to the register at the numerically 27 * higher address, thus, a full 64-bit write cycle requires a write 28 * to the lower address, followed by a write to the higher address, 29 * which will latch/execute the write cycle. 30 * 31 * For example, let's assume a SW reset of CAAM through the master 32 * configuration register. 33 * - SWRST is in bit 31 of MCFG. 34 * - MCFG begins at base+0x0000. 35 * - Bits 63-32 are a 32-bit word at base+0x0000 (numerically-lower) 36 * - Bits 31-0 are a 32-bit word at base+0x0004 (numerically-higher) 37 * 38 * (and on Power, the convention is 0-31, 32-63, I know...) 39 * 40 * Assuming a 64-bit write to this MCFG to perform a software reset 41 * would then require a write of 0 to base+0x0000, followed by a 42 * write of 0x80000000 to base+0x0004, which would "execute" the 43 * reset. 44 * 45 * Of course, since MCFG 63-32 is all zero, we could cheat and simply 46 * write 0x8000000 to base+0x0004, and the reset would work fine. 47 * However, since CAAM does contain some write-and-read-intended 48 * 64-bit registers, this code defines 64-bit access methods for 49 * the sake of internal consistency and simplicity, and so that a 50 * clean transition to 64-bit is possible when it becomes necessary. 51 * 52 * There are limitations to this that the developer must recognize. 53 * 32-bit architectures cannot enforce an atomic-64 operation, 54 * Therefore: 55 * 56 * - On writes, since the HW is assumed to latch the cycle on the 57 * write of the higher-numeric-address word, then ordered 58 * writes work OK. 59 * 60 * - For reads, where a register contains a relevant value of more 61 * that 32 bits, the hardware employs logic to latch the other 62 * "half" of the data until read, ensuring an accurate value. 63 * This is of particular relevance when dealing with CAAM's 64 * performance counters. 65 * 66 */ 67 68 #ifdef __BIG_ENDIAN 69 #define wr_reg32(reg, data) out_be32(reg, data) 70 #define rd_reg32(reg) in_be32(reg) 71 #ifdef CONFIG_64BIT 72 #define wr_reg64(reg, data) out_be64(reg, data) 73 #define rd_reg64(reg) in_be64(reg) 74 #endif 75 #else 76 #ifdef __LITTLE_ENDIAN 77 #define wr_reg32(reg, data) __raw_writel(data, reg) 78 #define rd_reg32(reg) __raw_readl(reg) 79 #ifdef CONFIG_64BIT 80 #define wr_reg64(reg, data) __raw_writeq(data, reg) 81 #define rd_reg64(reg) __raw_readq(reg) 82 #endif 83 #endif 84 #endif 85 86 #ifndef CONFIG_64BIT 87 static inline void wr_reg64(u64 __iomem *reg, u64 data) 88 { 89 wr_reg32((u32 __iomem *)reg, (data & 0xffffffff00000000ull) >> 32); 90 wr_reg32((u32 __iomem *)reg + 1, data & 0x00000000ffffffffull); 91 } 92 93 static inline u64 rd_reg64(u64 __iomem *reg) 94 { 95 return (((u64)rd_reg32((u32 __iomem *)reg)) << 32) | 96 ((u64)rd_reg32((u32 __iomem *)reg + 1)); 97 } 98 #endif 99 100 /* 101 * jr_outentry 102 * Represents each entry in a JobR output ring 103 */ 104 struct jr_outentry { 105 dma_addr_t desc;/* Pointer to completed descriptor */ 106 u32 jrstatus; /* Status for completed descriptor */ 107 } __packed; 108 109 /* 110 * caam_perfmon - Performance Monitor/Secure Memory Status/ 111 * CAAM Global Status/Component Version IDs 112 * 113 * Spans f00-fff wherever instantiated 114 */ 115 116 /* Number of DECOs */ 117 #define CHA_NUM_DECONUM_SHIFT 56 118 #define CHA_NUM_DECONUM_MASK (0xfull << CHA_NUM_DECONUM_SHIFT) 119 120 /* CHA Version IDs */ 121 #define CHA_ID_AES_SHIFT 0 122 #define CHA_ID_AES_MASK (0xfull << CHA_ID_AES_SHIFT) 123 124 #define CHA_ID_DES_SHIFT 4 125 #define CHA_ID_DES_MASK (0xfull << CHA_ID_DES_SHIFT) 126 127 #define CHA_ID_ARC4_SHIFT 8 128 #define CHA_ID_ARC4_MASK (0xfull << CHA_ID_ARC4_SHIFT) 129 130 #define CHA_ID_MD_SHIFT 12 131 #define CHA_ID_MD_MASK (0xfull << CHA_ID_MD_SHIFT) 132 133 #define CHA_ID_RNG_SHIFT 16 134 #define CHA_ID_RNG_MASK (0xfull << CHA_ID_RNG_SHIFT) 135 136 #define CHA_ID_SNW8_SHIFT 20 137 #define CHA_ID_SNW8_MASK (0xfull << CHA_ID_SNW8_SHIFT) 138 139 #define CHA_ID_KAS_SHIFT 24 140 #define CHA_ID_KAS_MASK (0xfull << CHA_ID_KAS_SHIFT) 141 142 #define CHA_ID_PK_SHIFT 28 143 #define CHA_ID_PK_MASK (0xfull << CHA_ID_PK_SHIFT) 144 145 #define CHA_ID_CRC_SHIFT 32 146 #define CHA_ID_CRC_MASK (0xfull << CHA_ID_CRC_SHIFT) 147 148 #define CHA_ID_SNW9_SHIFT 36 149 #define CHA_ID_SNW9_MASK (0xfull << CHA_ID_SNW9_SHIFT) 150 151 #define CHA_ID_DECO_SHIFT 56 152 #define CHA_ID_DECO_MASK (0xfull << CHA_ID_DECO_SHIFT) 153 154 #define CHA_ID_JR_SHIFT 60 155 #define CHA_ID_JR_MASK (0xfull << CHA_ID_JR_SHIFT) 156 157 struct sec_vid { 158 u16 ip_id; 159 u8 maj_rev; 160 u8 min_rev; 161 }; 162 163 struct caam_perfmon { 164 /* Performance Monitor Registers f00-f9f */ 165 u64 req_dequeued; /* PC_REQ_DEQ - Dequeued Requests */ 166 u64 ob_enc_req; /* PC_OB_ENC_REQ - Outbound Encrypt Requests */ 167 u64 ib_dec_req; /* PC_IB_DEC_REQ - Inbound Decrypt Requests */ 168 u64 ob_enc_bytes; /* PC_OB_ENCRYPT - Outbound Bytes Encrypted */ 169 u64 ob_prot_bytes; /* PC_OB_PROTECT - Outbound Bytes Protected */ 170 u64 ib_dec_bytes; /* PC_IB_DECRYPT - Inbound Bytes Decrypted */ 171 u64 ib_valid_bytes; /* PC_IB_VALIDATED Inbound Bytes Validated */ 172 u64 rsvd[13]; 173 174 /* CAAM Hardware Instantiation Parameters fa0-fbf */ 175 u64 cha_rev; /* CRNR - CHA Revision Number */ 176 #define CTPR_QI_SHIFT 57 177 #define CTPR_QI_MASK (0x1ull << CTPR_QI_SHIFT) 178 u64 comp_parms; /* CTPR - Compile Parameters Register */ 179 u64 rsvd1[2]; 180 181 /* CAAM Global Status fc0-fdf */ 182 u64 faultaddr; /* FAR - Fault Address */ 183 u32 faultliodn; /* FALR - Fault Address LIODN */ 184 u32 faultdetail; /* FADR - Fault Addr Detail */ 185 u32 rsvd2; 186 u32 status; /* CSTA - CAAM Status */ 187 u64 rsvd3; 188 189 /* Component Instantiation Parameters fe0-fff */ 190 u32 rtic_id; /* RVID - RTIC Version ID */ 191 u32 ccb_id; /* CCBVID - CCB Version ID */ 192 u64 cha_id; /* CHAVID - CHA Version ID */ 193 u64 cha_num; /* CHANUM - CHA Number */ 194 u64 caam_id; /* CAAMVID - CAAM Version ID */ 195 }; 196 197 /* LIODN programming for DMA configuration */ 198 #define MSTRID_LOCK_LIODN 0x80000000 199 #define MSTRID_LOCK_MAKETRUSTED 0x00010000 /* only for JR masterid */ 200 201 #define MSTRID_LIODN_MASK 0x0fff 202 struct masterid { 203 u32 liodn_ms; /* lock and make-trusted control bits */ 204 u32 liodn_ls; /* LIODN for non-sequence and seq access */ 205 }; 206 207 /* Partition ID for DMA configuration */ 208 struct partid { 209 u32 rsvd1; 210 u32 pidr; /* partition ID, DECO */ 211 }; 212 213 /* RNGB test mode (replicated twice in some configurations) */ 214 /* Padded out to 0x100 */ 215 struct rngtst { 216 u32 mode; /* RTSTMODEx - Test mode */ 217 u32 rsvd1[3]; 218 u32 reset; /* RTSTRESETx - Test reset control */ 219 u32 rsvd2[3]; 220 u32 status; /* RTSTSSTATUSx - Test status */ 221 u32 rsvd3; 222 u32 errstat; /* RTSTERRSTATx - Test error status */ 223 u32 rsvd4; 224 u32 errctl; /* RTSTERRCTLx - Test error control */ 225 u32 rsvd5; 226 u32 entropy; /* RTSTENTROPYx - Test entropy */ 227 u32 rsvd6[15]; 228 u32 verifctl; /* RTSTVERIFCTLx - Test verification control */ 229 u32 rsvd7; 230 u32 verifstat; /* RTSTVERIFSTATx - Test verification status */ 231 u32 rsvd8; 232 u32 verifdata; /* RTSTVERIFDx - Test verification data */ 233 u32 rsvd9; 234 u32 xkey; /* RTSTXKEYx - Test XKEY */ 235 u32 rsvd10; 236 u32 oscctctl; /* RTSTOSCCTCTLx - Test osc. counter control */ 237 u32 rsvd11; 238 u32 oscct; /* RTSTOSCCTx - Test oscillator counter */ 239 u32 rsvd12; 240 u32 oscctstat; /* RTSTODCCTSTATx - Test osc counter status */ 241 u32 rsvd13[2]; 242 u32 ofifo[4]; /* RTSTOFIFOx - Test output FIFO */ 243 u32 rsvd14[15]; 244 }; 245 246 /* RNG4 TRNG test registers */ 247 struct rng4tst { 248 #define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */ 249 u32 rtmctl; /* misc. control register */ 250 u32 rtscmisc; /* statistical check misc. register */ 251 u32 rtpkrrng; /* poker range register */ 252 union { 253 u32 rtpkrmax; /* PRGM=1: poker max. limit register */ 254 u32 rtpkrsq; /* PRGM=0: poker square calc. result register */ 255 }; 256 #define RTSDCTL_ENT_DLY_SHIFT 16 257 #define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT) 258 #define RTSDCTL_ENT_DLY_MIN 1200 259 #define RTSDCTL_ENT_DLY_MAX 12800 260 u32 rtsdctl; /* seed control register */ 261 union { 262 u32 rtsblim; /* PRGM=1: sparse bit limit register */ 263 u32 rttotsam; /* PRGM=0: total samples register */ 264 }; 265 u32 rtfrqmin; /* frequency count min. limit register */ 266 union { 267 u32 rtfrqmax; /* PRGM=1: freq. count max. limit register */ 268 u32 rtfrqcnt; /* PRGM=0: freq. count register */ 269 }; 270 u32 rsvd1[40]; 271 #define RDSTA_SKVT 0x80000000 272 #define RDSTA_SKVN 0x40000000 273 #define RDSTA_IF0 0x00000001 274 #define RDSTA_IF1 0x00000002 275 #define RDSTA_IFMASK (RDSTA_IF1 | RDSTA_IF0) 276 u32 rdsta; 277 u32 rsvd2[15]; 278 }; 279 280 /* 281 * caam_ctrl - basic core configuration 282 * starts base + 0x0000 padded out to 0x1000 283 */ 284 285 #define KEK_KEY_SIZE 8 286 #define TKEK_KEY_SIZE 8 287 #define TDSK_KEY_SIZE 8 288 289 #define DECO_RESET 1 /* Use with DECO reset/availability regs */ 290 #define DECO_RESET_0 (DECO_RESET << 0) 291 #define DECO_RESET_1 (DECO_RESET << 1) 292 #define DECO_RESET_2 (DECO_RESET << 2) 293 #define DECO_RESET_3 (DECO_RESET << 3) 294 #define DECO_RESET_4 (DECO_RESET << 4) 295 296 struct caam_ctrl { 297 /* Basic Configuration Section 000-01f */ 298 /* Read/Writable */ 299 u32 rsvd1; 300 u32 mcr; /* MCFG Master Config Register */ 301 u32 rsvd2; 302 u32 scfgr; /* SCFGR, Security Config Register */ 303 304 /* Bus Access Configuration Section 010-11f */ 305 /* Read/Writable */ 306 struct masterid jr_mid[4]; /* JRxLIODNR - JobR LIODN setup */ 307 u32 rsvd3[12]; 308 struct masterid rtic_mid[4]; /* RTICxLIODNR - RTIC LIODN setup */ 309 u32 rsvd4[7]; 310 u32 deco_rq; /* DECORR - DECO Request */ 311 struct partid deco_mid[5]; /* DECOxLIODNR - 1 per DECO */ 312 u32 rsvd5[22]; 313 314 /* DECO Availability/Reset Section 120-3ff */ 315 u32 deco_avail; /* DAR - DECO availability */ 316 u32 deco_reset; /* DRR - DECO reset */ 317 u32 rsvd6[182]; 318 319 /* Key Encryption/Decryption Configuration 400-5ff */ 320 /* Read/Writable only while in Non-secure mode */ 321 u32 kek[KEK_KEY_SIZE]; /* JDKEKR - Key Encryption Key */ 322 u32 tkek[TKEK_KEY_SIZE]; /* TDKEKR - Trusted Desc KEK */ 323 u32 tdsk[TDSK_KEY_SIZE]; /* TDSKR - Trusted Desc Signing Key */ 324 u32 rsvd7[32]; 325 u64 sknonce; /* SKNR - Secure Key Nonce */ 326 u32 rsvd8[70]; 327 328 /* RNG Test/Verification/Debug Access 600-7ff */ 329 /* (Useful in Test/Debug modes only...) */ 330 union { 331 struct rngtst rtst[2]; 332 struct rng4tst r4tst[2]; 333 }; 334 335 u32 rsvd9[448]; 336 337 /* Performance Monitor f00-fff */ 338 struct caam_perfmon perfmon; 339 }; 340 341 /* 342 * Controller master config register defs 343 */ 344 #define MCFGR_SWRESET 0x80000000 /* software reset */ 345 #define MCFGR_WDENABLE 0x40000000 /* DECO watchdog enable */ 346 #define MCFGR_WDFAIL 0x20000000 /* DECO watchdog force-fail */ 347 #define MCFGR_DMA_RESET 0x10000000 348 #define MCFGR_LONG_PTR 0x00010000 /* Use >32-bit desc addressing */ 349 #define SCFGR_RDBENABLE 0x00000400 350 #define DECORR_RQD0ENABLE 0x00000001 /* Enable DECO0 for direct access */ 351 #define DECORR_DEN0 0x00010000 /* DECO0 available for access*/ 352 353 /* AXI read cache control */ 354 #define MCFGR_ARCACHE_SHIFT 12 355 #define MCFGR_ARCACHE_MASK (0xf << MCFGR_ARCACHE_SHIFT) 356 357 /* AXI write cache control */ 358 #define MCFGR_AWCACHE_SHIFT 8 359 #define MCFGR_AWCACHE_MASK (0xf << MCFGR_AWCACHE_SHIFT) 360 361 /* AXI pipeline depth */ 362 #define MCFGR_AXIPIPE_SHIFT 4 363 #define MCFGR_AXIPIPE_MASK (0xf << MCFGR_AXIPIPE_SHIFT) 364 365 #define MCFGR_AXIPRI 0x00000008 /* Assert AXI priority sideband */ 366 #define MCFGR_BURST_64 0x00000001 /* Max burst size */ 367 368 /* 369 * caam_job_ring - direct job ring setup 370 * 1-4 possible per instantiation, base + 1000/2000/3000/4000 371 * Padded out to 0x1000 372 */ 373 struct caam_job_ring { 374 /* Input ring */ 375 u64 inpring_base; /* IRBAx - Input desc ring baseaddr */ 376 u32 rsvd1; 377 u32 inpring_size; /* IRSx - Input ring size */ 378 u32 rsvd2; 379 u32 inpring_avail; /* IRSAx - Input ring room remaining */ 380 u32 rsvd3; 381 u32 inpring_jobadd; /* IRJAx - Input ring jobs added */ 382 383 /* Output Ring */ 384 u64 outring_base; /* ORBAx - Output status ring base addr */ 385 u32 rsvd4; 386 u32 outring_size; /* ORSx - Output ring size */ 387 u32 rsvd5; 388 u32 outring_rmvd; /* ORJRx - Output ring jobs removed */ 389 u32 rsvd6; 390 u32 outring_used; /* ORSFx - Output ring slots full */ 391 392 /* Status/Configuration */ 393 u32 rsvd7; 394 u32 jroutstatus; /* JRSTAx - JobR output status */ 395 u32 rsvd8; 396 u32 jrintstatus; /* JRINTx - JobR interrupt status */ 397 u32 rconfig_hi; /* JRxCFG - Ring configuration */ 398 u32 rconfig_lo; 399 400 /* Indices. CAAM maintains as "heads" of each queue */ 401 u32 rsvd9; 402 u32 inp_rdidx; /* IRRIx - Input ring read index */ 403 u32 rsvd10; 404 u32 out_wtidx; /* ORWIx - Output ring write index */ 405 406 /* Command/control */ 407 u32 rsvd11; 408 u32 jrcommand; /* JRCRx - JobR command */ 409 410 u32 rsvd12[932]; 411 412 /* Performance Monitor f00-fff */ 413 struct caam_perfmon perfmon; 414 }; 415 416 #define JR_RINGSIZE_MASK 0x03ff 417 /* 418 * jrstatus - Job Ring Output Status 419 * All values in lo word 420 * Also note, same values written out as status through QI 421 * in the command/status field of a frame descriptor 422 */ 423 #define JRSTA_SSRC_SHIFT 28 424 #define JRSTA_SSRC_MASK 0xf0000000 425 426 #define JRSTA_SSRC_NONE 0x00000000 427 #define JRSTA_SSRC_CCB_ERROR 0x20000000 428 #define JRSTA_SSRC_JUMP_HALT_USER 0x30000000 429 #define JRSTA_SSRC_DECO 0x40000000 430 #define JRSTA_SSRC_JRERROR 0x60000000 431 #define JRSTA_SSRC_JUMP_HALT_CC 0x70000000 432 433 #define JRSTA_DECOERR_JUMP 0x08000000 434 #define JRSTA_DECOERR_INDEX_SHIFT 8 435 #define JRSTA_DECOERR_INDEX_MASK 0xff00 436 #define JRSTA_DECOERR_ERROR_MASK 0x00ff 437 438 #define JRSTA_DECOERR_NONE 0x00 439 #define JRSTA_DECOERR_LINKLEN 0x01 440 #define JRSTA_DECOERR_LINKPTR 0x02 441 #define JRSTA_DECOERR_JRCTRL 0x03 442 #define JRSTA_DECOERR_DESCCMD 0x04 443 #define JRSTA_DECOERR_ORDER 0x05 444 #define JRSTA_DECOERR_KEYCMD 0x06 445 #define JRSTA_DECOERR_LOADCMD 0x07 446 #define JRSTA_DECOERR_STORECMD 0x08 447 #define JRSTA_DECOERR_OPCMD 0x09 448 #define JRSTA_DECOERR_FIFOLDCMD 0x0a 449 #define JRSTA_DECOERR_FIFOSTCMD 0x0b 450 #define JRSTA_DECOERR_MOVECMD 0x0c 451 #define JRSTA_DECOERR_JUMPCMD 0x0d 452 #define JRSTA_DECOERR_MATHCMD 0x0e 453 #define JRSTA_DECOERR_SHASHCMD 0x0f 454 #define JRSTA_DECOERR_SEQCMD 0x10 455 #define JRSTA_DECOERR_DECOINTERNAL 0x11 456 #define JRSTA_DECOERR_SHDESCHDR 0x12 457 #define JRSTA_DECOERR_HDRLEN 0x13 458 #define JRSTA_DECOERR_BURSTER 0x14 459 #define JRSTA_DECOERR_DESCSIGNATURE 0x15 460 #define JRSTA_DECOERR_DMA 0x16 461 #define JRSTA_DECOERR_BURSTFIFO 0x17 462 #define JRSTA_DECOERR_JRRESET 0x1a 463 #define JRSTA_DECOERR_JOBFAIL 0x1b 464 #define JRSTA_DECOERR_DNRERR 0x80 465 #define JRSTA_DECOERR_UNDEFPCL 0x81 466 #define JRSTA_DECOERR_PDBERR 0x82 467 #define JRSTA_DECOERR_ANRPLY_LATE 0x83 468 #define JRSTA_DECOERR_ANRPLY_REPLAY 0x84 469 #define JRSTA_DECOERR_SEQOVF 0x85 470 #define JRSTA_DECOERR_INVSIGN 0x86 471 #define JRSTA_DECOERR_DSASIGN 0x87 472 473 #define JRSTA_CCBERR_JUMP 0x08000000 474 #define JRSTA_CCBERR_INDEX_MASK 0xff00 475 #define JRSTA_CCBERR_INDEX_SHIFT 8 476 #define JRSTA_CCBERR_CHAID_MASK 0x00f0 477 #define JRSTA_CCBERR_CHAID_SHIFT 4 478 #define JRSTA_CCBERR_ERRID_MASK 0x000f 479 480 #define JRSTA_CCBERR_CHAID_AES (0x01 << JRSTA_CCBERR_CHAID_SHIFT) 481 #define JRSTA_CCBERR_CHAID_DES (0x02 << JRSTA_CCBERR_CHAID_SHIFT) 482 #define JRSTA_CCBERR_CHAID_ARC4 (0x03 << JRSTA_CCBERR_CHAID_SHIFT) 483 #define JRSTA_CCBERR_CHAID_MD (0x04 << JRSTA_CCBERR_CHAID_SHIFT) 484 #define JRSTA_CCBERR_CHAID_RNG (0x05 << JRSTA_CCBERR_CHAID_SHIFT) 485 #define JRSTA_CCBERR_CHAID_SNOW (0x06 << JRSTA_CCBERR_CHAID_SHIFT) 486 #define JRSTA_CCBERR_CHAID_KASUMI (0x07 << JRSTA_CCBERR_CHAID_SHIFT) 487 #define JRSTA_CCBERR_CHAID_PK (0x08 << JRSTA_CCBERR_CHAID_SHIFT) 488 #define JRSTA_CCBERR_CHAID_CRC (0x09 << JRSTA_CCBERR_CHAID_SHIFT) 489 490 #define JRSTA_CCBERR_ERRID_NONE 0x00 491 #define JRSTA_CCBERR_ERRID_MODE 0x01 492 #define JRSTA_CCBERR_ERRID_DATASIZ 0x02 493 #define JRSTA_CCBERR_ERRID_KEYSIZ 0x03 494 #define JRSTA_CCBERR_ERRID_PKAMEMSZ 0x04 495 #define JRSTA_CCBERR_ERRID_PKBMEMSZ 0x05 496 #define JRSTA_CCBERR_ERRID_SEQUENCE 0x06 497 #define JRSTA_CCBERR_ERRID_PKDIVZRO 0x07 498 #define JRSTA_CCBERR_ERRID_PKMODEVN 0x08 499 #define JRSTA_CCBERR_ERRID_KEYPARIT 0x09 500 #define JRSTA_CCBERR_ERRID_ICVCHK 0x0a 501 #define JRSTA_CCBERR_ERRID_HARDWARE 0x0b 502 #define JRSTA_CCBERR_ERRID_CCMAAD 0x0c 503 #define JRSTA_CCBERR_ERRID_INVCHA 0x0f 504 505 #define JRINT_ERR_INDEX_MASK 0x3fff0000 506 #define JRINT_ERR_INDEX_SHIFT 16 507 #define JRINT_ERR_TYPE_MASK 0xf00 508 #define JRINT_ERR_TYPE_SHIFT 8 509 #define JRINT_ERR_HALT_MASK 0xc 510 #define JRINT_ERR_HALT_SHIFT 2 511 #define JRINT_ERR_HALT_INPROGRESS 0x4 512 #define JRINT_ERR_HALT_COMPLETE 0x8 513 #define JRINT_JR_ERROR 0x02 514 #define JRINT_JR_INT 0x01 515 516 #define JRINT_ERR_TYPE_WRITE 1 517 #define JRINT_ERR_TYPE_BAD_INPADDR 3 518 #define JRINT_ERR_TYPE_BAD_OUTADDR 4 519 #define JRINT_ERR_TYPE_INV_INPWRT 5 520 #define JRINT_ERR_TYPE_INV_OUTWRT 6 521 #define JRINT_ERR_TYPE_RESET 7 522 #define JRINT_ERR_TYPE_REMOVE_OFL 8 523 #define JRINT_ERR_TYPE_ADD_OFL 9 524 525 #define JRCFG_SOE 0x04 526 #define JRCFG_ICEN 0x02 527 #define JRCFG_IMSK 0x01 528 #define JRCFG_ICDCT_SHIFT 8 529 #define JRCFG_ICTT_SHIFT 16 530 531 #define JRCR_RESET 0x01 532 533 /* 534 * caam_assurance - Assurance Controller View 535 * base + 0x6000 padded out to 0x1000 536 */ 537 538 struct rtic_element { 539 u64 address; 540 u32 rsvd; 541 u32 length; 542 }; 543 544 struct rtic_block { 545 struct rtic_element element[2]; 546 }; 547 548 struct rtic_memhash { 549 u32 memhash_be[32]; 550 u32 memhash_le[32]; 551 }; 552 553 struct caam_assurance { 554 /* Status/Command/Watchdog */ 555 u32 rsvd1; 556 u32 status; /* RSTA - Status */ 557 u32 rsvd2; 558 u32 cmd; /* RCMD - Command */ 559 u32 rsvd3; 560 u32 ctrl; /* RCTL - Control */ 561 u32 rsvd4; 562 u32 throttle; /* RTHR - Throttle */ 563 u32 rsvd5[2]; 564 u64 watchdog; /* RWDOG - Watchdog Timer */ 565 u32 rsvd6; 566 u32 rend; /* REND - Endian corrections */ 567 u32 rsvd7[50]; 568 569 /* Block access/configuration @ 100/110/120/130 */ 570 struct rtic_block memblk[4]; /* Memory Blocks A-D */ 571 u32 rsvd8[32]; 572 573 /* Block hashes @ 200/300/400/500 */ 574 struct rtic_memhash hash[4]; /* Block hash values A-D */ 575 u32 rsvd_3[640]; 576 }; 577 578 /* 579 * caam_queue_if - QI configuration and control 580 * starts base + 0x7000, padded out to 0x1000 long 581 */ 582 583 struct caam_queue_if { 584 u32 qi_control_hi; /* QICTL - QI Control */ 585 u32 qi_control_lo; 586 u32 rsvd1; 587 u32 qi_status; /* QISTA - QI Status */ 588 u32 qi_deq_cfg_hi; /* QIDQC - QI Dequeue Configuration */ 589 u32 qi_deq_cfg_lo; 590 u32 qi_enq_cfg_hi; /* QISEQC - QI Enqueue Command */ 591 u32 qi_enq_cfg_lo; 592 u32 rsvd2[1016]; 593 }; 594 595 /* QI control bits - low word */ 596 #define QICTL_DQEN 0x01 /* Enable frame pop */ 597 #define QICTL_STOP 0x02 /* Stop dequeue/enqueue */ 598 #define QICTL_SOE 0x04 /* Stop on error */ 599 600 /* QI control bits - high word */ 601 #define QICTL_MBSI 0x01 602 #define QICTL_MHWSI 0x02 603 #define QICTL_MWSI 0x04 604 #define QICTL_MDWSI 0x08 605 #define QICTL_CBSI 0x10 /* CtrlDataByteSwapInput */ 606 #define QICTL_CHWSI 0x20 /* CtrlDataHalfSwapInput */ 607 #define QICTL_CWSI 0x40 /* CtrlDataWordSwapInput */ 608 #define QICTL_CDWSI 0x80 /* CtrlDataDWordSwapInput */ 609 #define QICTL_MBSO 0x0100 610 #define QICTL_MHWSO 0x0200 611 #define QICTL_MWSO 0x0400 612 #define QICTL_MDWSO 0x0800 613 #define QICTL_CBSO 0x1000 /* CtrlDataByteSwapOutput */ 614 #define QICTL_CHWSO 0x2000 /* CtrlDataHalfSwapOutput */ 615 #define QICTL_CWSO 0x4000 /* CtrlDataWordSwapOutput */ 616 #define QICTL_CDWSO 0x8000 /* CtrlDataDWordSwapOutput */ 617 #define QICTL_DMBS 0x010000 618 #define QICTL_EPO 0x020000 619 620 /* QI status bits */ 621 #define QISTA_PHRDERR 0x01 /* PreHeader Read Error */ 622 #define QISTA_CFRDERR 0x02 /* Compound Frame Read Error */ 623 #define QISTA_OFWRERR 0x04 /* Output Frame Read Error */ 624 #define QISTA_BPDERR 0x08 /* Buffer Pool Depleted */ 625 #define QISTA_BTSERR 0x10 /* Buffer Undersize */ 626 #define QISTA_CFWRERR 0x20 /* Compound Frame Write Err */ 627 #define QISTA_STOPD 0x80000000 /* QI Stopped (see QICTL) */ 628 629 /* deco_sg_table - DECO view of scatter/gather table */ 630 struct deco_sg_table { 631 u64 addr; /* Segment Address */ 632 u32 elen; /* E, F bits + 30-bit length */ 633 u32 bpid_offset; /* Buffer Pool ID + 16-bit length */ 634 }; 635 636 /* 637 * caam_deco - descriptor controller - CHA cluster block 638 * 639 * Only accessible when direct DECO access is turned on 640 * (done in DECORR, via MID programmed in DECOxMID 641 * 642 * 5 typical, base + 0x8000/9000/a000/b000 643 * Padded out to 0x1000 long 644 */ 645 struct caam_deco { 646 u32 rsvd1; 647 u32 cls1_mode; /* CxC1MR - Class 1 Mode */ 648 u32 rsvd2; 649 u32 cls1_keysize; /* CxC1KSR - Class 1 Key Size */ 650 u32 cls1_datasize_hi; /* CxC1DSR - Class 1 Data Size */ 651 u32 cls1_datasize_lo; 652 u32 rsvd3; 653 u32 cls1_icvsize; /* CxC1ICVSR - Class 1 ICV size */ 654 u32 rsvd4[5]; 655 u32 cha_ctrl; /* CCTLR - CHA control */ 656 u32 rsvd5; 657 u32 irq_crtl; /* CxCIRQ - CCB interrupt done/error/clear */ 658 u32 rsvd6; 659 u32 clr_written; /* CxCWR - Clear-Written */ 660 u32 ccb_status_hi; /* CxCSTA - CCB Status/Error */ 661 u32 ccb_status_lo; 662 u32 rsvd7[3]; 663 u32 aad_size; /* CxAADSZR - Current AAD Size */ 664 u32 rsvd8; 665 u32 cls1_iv_size; /* CxC1IVSZR - Current Class 1 IV Size */ 666 u32 rsvd9[7]; 667 u32 pkha_a_size; /* PKASZRx - Size of PKHA A */ 668 u32 rsvd10; 669 u32 pkha_b_size; /* PKBSZRx - Size of PKHA B */ 670 u32 rsvd11; 671 u32 pkha_n_size; /* PKNSZRx - Size of PKHA N */ 672 u32 rsvd12; 673 u32 pkha_e_size; /* PKESZRx - Size of PKHA E */ 674 u32 rsvd13[24]; 675 u32 cls1_ctx[16]; /* CxC1CTXR - Class 1 Context @100 */ 676 u32 rsvd14[48]; 677 u32 cls1_key[8]; /* CxC1KEYR - Class 1 Key @200 */ 678 u32 rsvd15[121]; 679 u32 cls2_mode; /* CxC2MR - Class 2 Mode */ 680 u32 rsvd16; 681 u32 cls2_keysize; /* CxX2KSR - Class 2 Key Size */ 682 u32 cls2_datasize_hi; /* CxC2DSR - Class 2 Data Size */ 683 u32 cls2_datasize_lo; 684 u32 rsvd17; 685 u32 cls2_icvsize; /* CxC2ICVSZR - Class 2 ICV Size */ 686 u32 rsvd18[56]; 687 u32 cls2_ctx[18]; /* CxC2CTXR - Class 2 Context @500 */ 688 u32 rsvd19[46]; 689 u32 cls2_key[32]; /* CxC2KEYR - Class2 Key @600 */ 690 u32 rsvd20[84]; 691 u32 inp_infofifo_hi; /* CxIFIFO - Input Info FIFO @7d0 */ 692 u32 inp_infofifo_lo; 693 u32 rsvd21[2]; 694 u64 inp_datafifo; /* CxDFIFO - Input Data FIFO */ 695 u32 rsvd22[2]; 696 u64 out_datafifo; /* CxOFIFO - Output Data FIFO */ 697 u32 rsvd23[2]; 698 u32 jr_ctl_hi; /* CxJRR - JobR Control Register @800 */ 699 u32 jr_ctl_lo; 700 u64 jr_descaddr; /* CxDADR - JobR Descriptor Address */ 701 #define DECO_OP_STATUS_HI_ERR_MASK 0xF00000FF 702 u32 op_status_hi; /* DxOPSTA - DECO Operation Status */ 703 u32 op_status_lo; 704 u32 rsvd24[2]; 705 u32 liodn; /* DxLSR - DECO LIODN Status - non-seq */ 706 u32 td_liodn; /* DxLSR - DECO LIODN Status - trustdesc */ 707 u32 rsvd26[6]; 708 u64 math[4]; /* DxMTH - Math register */ 709 u32 rsvd27[8]; 710 struct deco_sg_table gthr_tbl[4]; /* DxGTR - Gather Tables */ 711 u32 rsvd28[16]; 712 struct deco_sg_table sctr_tbl[4]; /* DxSTR - Scatter Tables */ 713 u32 rsvd29[48]; 714 u32 descbuf[64]; /* DxDESB - Descriptor buffer */ 715 u32 rscvd30[193]; 716 #define DESC_DBG_DECO_STAT_HOST_ERR 0x00D00000 717 #define DESC_DBG_DECO_STAT_VALID 0x80000000 718 #define DESC_DBG_DECO_STAT_MASK 0x00F00000 719 u32 desc_dbg; /* DxDDR - DECO Debug Register */ 720 u32 rsvd31[126]; 721 }; 722 723 #define DECO_JQCR_WHL 0x20000000 724 #define DECO_JQCR_FOUR 0x10000000 725 726 /* 727 * Current top-level view of memory map is: 728 * 729 * 0x0000 - 0x0fff - CAAM Top-Level Control 730 * 0x1000 - 0x1fff - Job Ring 0 731 * 0x2000 - 0x2fff - Job Ring 1 732 * 0x3000 - 0x3fff - Job Ring 2 733 * 0x4000 - 0x4fff - Job Ring 3 734 * 0x5000 - 0x5fff - (unused) 735 * 0x6000 - 0x6fff - Assurance Controller 736 * 0x7000 - 0x7fff - Queue Interface 737 * 0x8000 - 0x8fff - DECO-CCB 0 738 * 0x9000 - 0x9fff - DECO-CCB 1 739 * 0xa000 - 0xafff - DECO-CCB 2 740 * 0xb000 - 0xbfff - DECO-CCB 3 741 * 0xc000 - 0xcfff - DECO-CCB 4 742 * 743 * caam_full describes the full register view of CAAM if useful, 744 * although many configurations may choose to implement parts of 745 * the register map separately, in differing privilege regions 746 */ 747 struct caam_full { 748 struct caam_ctrl __iomem ctrl; 749 struct caam_job_ring jr[4]; 750 u64 rsvd[512]; 751 struct caam_assurance assure; 752 struct caam_queue_if qi; 753 struct caam_deco deco; 754 }; 755 756 #endif /* REGS_H */ 757