1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * CAAM hardware register-level view 4 * 5 * Copyright 2008-2011 Freescale Semiconductor, Inc. 6 * Copyright 2018, 2023 NXP 7 */ 8 9 #ifndef REGS_H 10 #define REGS_H 11 12 #include <linux/types.h> 13 #include <linux/bitops.h> 14 #include <linux/io.h> 15 #include <linux/io-64-nonatomic-hi-lo.h> 16 17 /* 18 * Architecture-specific register access methods 19 * 20 * CAAM's bus-addressable registers are 64 bits internally. 21 * They have been wired to be safely accessible on 32-bit 22 * architectures, however. Registers were organized such 23 * that (a) they can be contained in 32 bits, (b) if not, then they 24 * can be treated as two 32-bit entities, or finally (c) if they 25 * must be treated as a single 64-bit value, then this can safely 26 * be done with two 32-bit cycles. 27 * 28 * For 32-bit operations on 64-bit values, CAAM follows the same 29 * 64-bit register access conventions as it's predecessors, in that 30 * writes are "triggered" by a write to the register at the numerically 31 * higher address, thus, a full 64-bit write cycle requires a write 32 * to the lower address, followed by a write to the higher address, 33 * which will latch/execute the write cycle. 34 * 35 * For example, let's assume a SW reset of CAAM through the master 36 * configuration register. 37 * - SWRST is in bit 31 of MCFG. 38 * - MCFG begins at base+0x0000. 39 * - Bits 63-32 are a 32-bit word at base+0x0000 (numerically-lower) 40 * - Bits 31-0 are a 32-bit word at base+0x0004 (numerically-higher) 41 * 42 * (and on Power, the convention is 0-31, 32-63, I know...) 43 * 44 * Assuming a 64-bit write to this MCFG to perform a software reset 45 * would then require a write of 0 to base+0x0000, followed by a 46 * write of 0x80000000 to base+0x0004, which would "execute" the 47 * reset. 48 * 49 * Of course, since MCFG 63-32 is all zero, we could cheat and simply 50 * write 0x8000000 to base+0x0004, and the reset would work fine. 51 * However, since CAAM does contain some write-and-read-intended 52 * 64-bit registers, this code defines 64-bit access methods for 53 * the sake of internal consistency and simplicity, and so that a 54 * clean transition to 64-bit is possible when it becomes necessary. 55 * 56 * There are limitations to this that the developer must recognize. 57 * 32-bit architectures cannot enforce an atomic-64 operation, 58 * Therefore: 59 * 60 * - On writes, since the HW is assumed to latch the cycle on the 61 * write of the higher-numeric-address word, then ordered 62 * writes work OK. 63 * 64 * - For reads, where a register contains a relevant value of more 65 * that 32 bits, the hardware employs logic to latch the other 66 * "half" of the data until read, ensuring an accurate value. 67 * This is of particular relevance when dealing with CAAM's 68 * performance counters. 69 * 70 */ 71 72 extern bool caam_little_end; 73 extern bool caam_imx; 74 extern size_t caam_ptr_sz; 75 76 #define caam_to_cpu(len) \ 77 static inline u##len caam##len ## _to_cpu(u##len val) \ 78 { \ 79 if (caam_little_end) \ 80 return le##len ## _to_cpu((__force __le##len)val); \ 81 else \ 82 return be##len ## _to_cpu((__force __be##len)val); \ 83 } 84 85 #define cpu_to_caam(len) \ 86 static inline u##len cpu_to_caam##len(u##len val) \ 87 { \ 88 if (caam_little_end) \ 89 return (__force u##len)cpu_to_le##len(val); \ 90 else \ 91 return (__force u##len)cpu_to_be##len(val); \ 92 } 93 94 caam_to_cpu(16) 95 caam_to_cpu(32) 96 caam_to_cpu(64) 97 cpu_to_caam(16) 98 cpu_to_caam(32) 99 cpu_to_caam(64) 100 101 static inline void wr_reg32(void __iomem *reg, u32 data) 102 { 103 if (caam_little_end) 104 iowrite32(data, reg); 105 else 106 iowrite32be(data, reg); 107 } 108 109 static inline u32 rd_reg32(void __iomem *reg) 110 { 111 if (caam_little_end) 112 return ioread32(reg); 113 114 return ioread32be(reg); 115 } 116 117 static inline void clrsetbits_32(void __iomem *reg, u32 clear, u32 set) 118 { 119 if (caam_little_end) 120 iowrite32((ioread32(reg) & ~clear) | set, reg); 121 else 122 iowrite32be((ioread32be(reg) & ~clear) | set, reg); 123 } 124 125 /* 126 * The only users of these wr/rd_reg64 functions is the Job Ring (JR). 127 * The DMA address registers in the JR are handled differently depending on 128 * platform: 129 * 130 * 1. All BE CAAM platforms and i.MX platforms (LE CAAM): 131 * 132 * base + 0x0000 : most-significant 32 bits 133 * base + 0x0004 : least-significant 32 bits 134 * 135 * The 32-bit version of this core therefore has to write to base + 0x0004 136 * to set the 32-bit wide DMA address. 137 * 138 * 2. All other LE CAAM platforms (LS1021A etc.) 139 * base + 0x0000 : least-significant 32 bits 140 * base + 0x0004 : most-significant 32 bits 141 */ 142 static inline void wr_reg64(void __iomem *reg, u64 data) 143 { 144 if (caam_little_end) { 145 if (caam_imx) { 146 iowrite32(data >> 32, (u32 __iomem *)(reg)); 147 iowrite32(data, (u32 __iomem *)(reg) + 1); 148 } else { 149 iowrite64(data, reg); 150 } 151 } else { 152 iowrite64be(data, reg); 153 } 154 } 155 156 static inline u64 rd_reg64(void __iomem *reg) 157 { 158 if (caam_little_end) { 159 if (caam_imx) { 160 u32 low, high; 161 162 high = ioread32(reg); 163 low = ioread32(reg + sizeof(u32)); 164 165 return low + ((u64)high << 32); 166 } else { 167 return ioread64(reg); 168 } 169 } else { 170 return ioread64be(reg); 171 } 172 } 173 174 static inline u64 cpu_to_caam_dma64(dma_addr_t value) 175 { 176 if (caam_imx) { 177 u64 ret_val = (u64)cpu_to_caam32(lower_32_bits(value)) << 32; 178 179 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)) 180 ret_val |= (u64)cpu_to_caam32(upper_32_bits(value)); 181 182 return ret_val; 183 } 184 185 return cpu_to_caam64(value); 186 } 187 188 static inline u64 caam_dma64_to_cpu(u64 value) 189 { 190 if (caam_imx) 191 return (((u64)caam32_to_cpu(lower_32_bits(value)) << 32) | 192 (u64)caam32_to_cpu(upper_32_bits(value))); 193 194 return caam64_to_cpu(value); 195 } 196 197 static inline u64 cpu_to_caam_dma(u64 value) 198 { 199 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) && 200 caam_ptr_sz == sizeof(u64)) 201 return cpu_to_caam_dma64(value); 202 else 203 return cpu_to_caam32(value); 204 } 205 206 static inline u64 caam_dma_to_cpu(u64 value) 207 { 208 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) && 209 caam_ptr_sz == sizeof(u64)) 210 return caam_dma64_to_cpu(value); 211 else 212 return caam32_to_cpu(value); 213 } 214 215 /* 216 * jr_outentry 217 * Represents each entry in a JobR output ring 218 */ 219 220 static inline void jr_outentry_get(void *outring, int hw_idx, dma_addr_t *desc, 221 u32 *jrstatus) 222 { 223 224 if (caam_ptr_sz == sizeof(u32)) { 225 struct { 226 u32 desc; 227 u32 jrstatus; 228 } __packed *outentry = outring; 229 230 *desc = outentry[hw_idx].desc; 231 *jrstatus = outentry[hw_idx].jrstatus; 232 } else { 233 struct { 234 dma_addr_t desc;/* Pointer to completed descriptor */ 235 u32 jrstatus; /* Status for completed descriptor */ 236 } __packed *outentry = outring; 237 238 *desc = outentry[hw_idx].desc; 239 *jrstatus = outentry[hw_idx].jrstatus; 240 } 241 } 242 243 #define SIZEOF_JR_OUTENTRY (caam_ptr_sz + sizeof(u32)) 244 245 static inline dma_addr_t jr_outentry_desc(void *outring, int hw_idx) 246 { 247 dma_addr_t desc; 248 u32 unused; 249 250 jr_outentry_get(outring, hw_idx, &desc, &unused); 251 252 return desc; 253 } 254 255 static inline u32 jr_outentry_jrstatus(void *outring, int hw_idx) 256 { 257 dma_addr_t unused; 258 u32 jrstatus; 259 260 jr_outentry_get(outring, hw_idx, &unused, &jrstatus); 261 262 return jrstatus; 263 } 264 265 static inline void jr_inpentry_set(void *inpring, int hw_idx, dma_addr_t val) 266 { 267 if (caam_ptr_sz == sizeof(u32)) { 268 u32 *inpentry = inpring; 269 270 inpentry[hw_idx] = val; 271 } else { 272 dma_addr_t *inpentry = inpring; 273 274 inpentry[hw_idx] = val; 275 } 276 } 277 278 #define SIZEOF_JR_INPENTRY caam_ptr_sz 279 280 281 /* Version registers (Era 10+) e80-eff */ 282 struct version_regs { 283 u32 crca; /* CRCA_VERSION */ 284 u32 afha; /* AFHA_VERSION */ 285 u32 kfha; /* KFHA_VERSION */ 286 u32 pkha; /* PKHA_VERSION */ 287 u32 aesa; /* AESA_VERSION */ 288 u32 mdha; /* MDHA_VERSION */ 289 u32 desa; /* DESA_VERSION */ 290 u32 snw8a; /* SNW8A_VERSION */ 291 u32 snw9a; /* SNW9A_VERSION */ 292 u32 zuce; /* ZUCE_VERSION */ 293 u32 zuca; /* ZUCA_VERSION */ 294 u32 ccha; /* CCHA_VERSION */ 295 u32 ptha; /* PTHA_VERSION */ 296 u32 rng; /* RNG_VERSION */ 297 u32 trng; /* TRNG_VERSION */ 298 u32 aaha; /* AAHA_VERSION */ 299 u32 rsvd[10]; 300 u32 sr; /* SR_VERSION */ 301 u32 dma; /* DMA_VERSION */ 302 u32 ai; /* AI_VERSION */ 303 u32 qi; /* QI_VERSION */ 304 u32 jr; /* JR_VERSION */ 305 u32 deco; /* DECO_VERSION */ 306 }; 307 308 /* Version registers bitfields */ 309 310 /* Number of CHAs instantiated */ 311 #define CHA_VER_NUM_MASK 0xffull 312 /* CHA Miscellaneous Information */ 313 #define CHA_VER_MISC_SHIFT 8 314 #define CHA_VER_MISC_MASK (0xffull << CHA_VER_MISC_SHIFT) 315 /* CHA Revision Number */ 316 #define CHA_VER_REV_SHIFT 16 317 #define CHA_VER_REV_MASK (0xffull << CHA_VER_REV_SHIFT) 318 /* CHA Version ID */ 319 #define CHA_VER_VID_SHIFT 24 320 #define CHA_VER_VID_MASK (0xffull << CHA_VER_VID_SHIFT) 321 322 /* CHA Miscellaneous Information - AESA_MISC specific */ 323 #define CHA_VER_MISC_AES_NUM_MASK GENMASK(7, 0) 324 #define CHA_VER_MISC_AES_GCM BIT(1 + CHA_VER_MISC_SHIFT) 325 326 /* CHA Miscellaneous Information - PKHA_MISC specific */ 327 #define CHA_VER_MISC_PKHA_NO_CRYPT BIT(7 + CHA_VER_MISC_SHIFT) 328 329 /* 330 * caam_perfmon - Performance Monitor/Secure Memory Status/ 331 * CAAM Global Status/Component Version IDs 332 * 333 * Spans f00-fff wherever instantiated 334 */ 335 336 /* Number of DECOs */ 337 #define CHA_NUM_MS_DECONUM_SHIFT 24 338 #define CHA_NUM_MS_DECONUM_MASK (0xfull << CHA_NUM_MS_DECONUM_SHIFT) 339 340 /* 341 * CHA version IDs / instantiation bitfields (< Era 10) 342 * Defined for use with the cha_id fields in perfmon, but the same shift/mask 343 * selectors can be used to pull out the number of instantiated blocks within 344 * cha_num fields in perfmon because the locations are the same. 345 */ 346 #define CHA_ID_LS_AES_SHIFT 0 347 #define CHA_ID_LS_AES_MASK (0xfull << CHA_ID_LS_AES_SHIFT) 348 349 #define CHA_ID_LS_DES_SHIFT 4 350 #define CHA_ID_LS_DES_MASK (0xfull << CHA_ID_LS_DES_SHIFT) 351 352 #define CHA_ID_LS_ARC4_SHIFT 8 353 #define CHA_ID_LS_ARC4_MASK (0xfull << CHA_ID_LS_ARC4_SHIFT) 354 355 #define CHA_ID_LS_MD_SHIFT 12 356 #define CHA_ID_LS_MD_MASK (0xfull << CHA_ID_LS_MD_SHIFT) 357 358 #define CHA_ID_LS_RNG_SHIFT 16 359 #define CHA_ID_LS_RNG_MASK (0xfull << CHA_ID_LS_RNG_SHIFT) 360 361 #define CHA_ID_LS_SNW8_SHIFT 20 362 #define CHA_ID_LS_SNW8_MASK (0xfull << CHA_ID_LS_SNW8_SHIFT) 363 364 #define CHA_ID_LS_KAS_SHIFT 24 365 #define CHA_ID_LS_KAS_MASK (0xfull << CHA_ID_LS_KAS_SHIFT) 366 367 #define CHA_ID_LS_PK_SHIFT 28 368 #define CHA_ID_LS_PK_MASK (0xfull << CHA_ID_LS_PK_SHIFT) 369 370 #define CHA_ID_MS_CRC_SHIFT 0 371 #define CHA_ID_MS_CRC_MASK (0xfull << CHA_ID_MS_CRC_SHIFT) 372 373 #define CHA_ID_MS_SNW9_SHIFT 4 374 #define CHA_ID_MS_SNW9_MASK (0xfull << CHA_ID_MS_SNW9_SHIFT) 375 376 #define CHA_ID_MS_DECO_SHIFT 24 377 #define CHA_ID_MS_DECO_MASK (0xfull << CHA_ID_MS_DECO_SHIFT) 378 379 #define CHA_ID_MS_JR_SHIFT 28 380 #define CHA_ID_MS_JR_MASK (0xfull << CHA_ID_MS_JR_SHIFT) 381 382 /* Specific CHA version IDs */ 383 #define CHA_VER_VID_AES_LP 0x3ull 384 #define CHA_VER_VID_AES_HP 0x4ull 385 #define CHA_VER_VID_MD_LP256 0x0ull 386 #define CHA_VER_VID_MD_LP512 0x1ull 387 #define CHA_VER_VID_MD_HP 0x2ull 388 389 struct sec_vid { 390 u16 ip_id; 391 u8 maj_rev; 392 u8 min_rev; 393 }; 394 395 struct caam_perfmon { 396 /* Performance Monitor Registers f00-f9f */ 397 u64 req_dequeued; /* PC_REQ_DEQ - Dequeued Requests */ 398 u64 ob_enc_req; /* PC_OB_ENC_REQ - Outbound Encrypt Requests */ 399 u64 ib_dec_req; /* PC_IB_DEC_REQ - Inbound Decrypt Requests */ 400 u64 ob_enc_bytes; /* PC_OB_ENCRYPT - Outbound Bytes Encrypted */ 401 u64 ob_prot_bytes; /* PC_OB_PROTECT - Outbound Bytes Protected */ 402 u64 ib_dec_bytes; /* PC_IB_DECRYPT - Inbound Bytes Decrypted */ 403 u64 ib_valid_bytes; /* PC_IB_VALIDATED Inbound Bytes Validated */ 404 u64 rsvd[13]; 405 406 /* CAAM Hardware Instantiation Parameters fa0-fbf */ 407 u32 cha_rev_ms; /* CRNR - CHA Rev No. Most significant half*/ 408 u32 cha_rev_ls; /* CRNR - CHA Rev No. Least significant half*/ 409 #define CTPR_MS_QI_SHIFT 25 410 #define CTPR_MS_QI_MASK (0x1ull << CTPR_MS_QI_SHIFT) 411 #define CTPR_MS_PS BIT(17) 412 #define CTPR_MS_DPAA2 BIT(13) 413 #define CTPR_MS_VIRT_EN_INCL 0x00000001 414 #define CTPR_MS_VIRT_EN_POR 0x00000002 415 #define CTPR_MS_PG_SZ_MASK 0x10 416 #define CTPR_MS_PG_SZ_SHIFT 4 417 u32 comp_parms_ms; /* CTPR - Compile Parameters Register */ 418 #define CTPR_LS_BLOB BIT(1) 419 u32 comp_parms_ls; /* CTPR - Compile Parameters Register */ 420 u64 rsvd1[2]; 421 422 /* CAAM Global Status fc0-fdf */ 423 u64 faultaddr; /* FAR - Fault Address */ 424 u32 faultliodn; /* FALR - Fault Address LIODN */ 425 u32 faultdetail; /* FADR - Fault Addr Detail */ 426 u32 rsvd2; 427 #define CSTA_PLEND BIT(10) 428 #define CSTA_ALT_PLEND BIT(18) 429 #define CSTA_MOO GENMASK(9, 8) 430 #define CSTA_MOO_SECURE 1 431 #define CSTA_MOO_TRUSTED 2 432 u32 status; /* CSTA - CAAM Status */ 433 u64 rsvd3; 434 435 /* Component Instantiation Parameters fe0-fff */ 436 u32 rtic_id; /* RVID - RTIC Version ID */ 437 #define CCBVID_ERA_MASK 0xff000000 438 #define CCBVID_ERA_SHIFT 24 439 u32 ccb_id; /* CCBVID - CCB Version ID */ 440 u32 cha_id_ms; /* CHAVID - CHA Version ID Most Significant*/ 441 u32 cha_id_ls; /* CHAVID - CHA Version ID Least Significant*/ 442 u32 cha_num_ms; /* CHANUM - CHA Number Most Significant */ 443 u32 cha_num_ls; /* CHANUM - CHA Number Least Significant*/ 444 #define SECVID_MS_IPID_MASK 0xffff0000 445 #define SECVID_MS_IPID_SHIFT 16 446 #define SECVID_MS_MAJ_REV_MASK 0x0000ff00 447 #define SECVID_MS_MAJ_REV_SHIFT 8 448 u32 caam_id_ms; /* CAAMVID - CAAM Version ID MS */ 449 u32 caam_id_ls; /* CAAMVID - CAAM Version ID LS */ 450 }; 451 452 /* LIODN programming for DMA configuration */ 453 #define MSTRID_LOCK_LIODN 0x80000000 454 #define MSTRID_LOCK_MAKETRUSTED 0x00010000 /* only for JR masterid */ 455 456 #define MSTRID_LIODN_MASK 0x0fff 457 struct masterid { 458 u32 liodn_ms; /* lock and make-trusted control bits */ 459 u32 liodn_ls; /* LIODN for non-sequence and seq access */ 460 }; 461 462 /* Partition ID for DMA configuration */ 463 struct partid { 464 u32 rsvd1; 465 u32 pidr; /* partition ID, DECO */ 466 }; 467 468 /* RNGB test mode (replicated twice in some configurations) */ 469 /* Padded out to 0x100 */ 470 struct rngtst { 471 u32 mode; /* RTSTMODEx - Test mode */ 472 u32 rsvd1[3]; 473 u32 reset; /* RTSTRESETx - Test reset control */ 474 u32 rsvd2[3]; 475 u32 status; /* RTSTSSTATUSx - Test status */ 476 u32 rsvd3; 477 u32 errstat; /* RTSTERRSTATx - Test error status */ 478 u32 rsvd4; 479 u32 errctl; /* RTSTERRCTLx - Test error control */ 480 u32 rsvd5; 481 u32 entropy; /* RTSTENTROPYx - Test entropy */ 482 u32 rsvd6[15]; 483 u32 verifctl; /* RTSTVERIFCTLx - Test verification control */ 484 u32 rsvd7; 485 u32 verifstat; /* RTSTVERIFSTATx - Test verification status */ 486 u32 rsvd8; 487 u32 verifdata; /* RTSTVERIFDx - Test verification data */ 488 u32 rsvd9; 489 u32 xkey; /* RTSTXKEYx - Test XKEY */ 490 u32 rsvd10; 491 u32 oscctctl; /* RTSTOSCCTCTLx - Test osc. counter control */ 492 u32 rsvd11; 493 u32 oscct; /* RTSTOSCCTx - Test oscillator counter */ 494 u32 rsvd12; 495 u32 oscctstat; /* RTSTODCCTSTATx - Test osc counter status */ 496 u32 rsvd13[2]; 497 u32 ofifo[4]; /* RTSTOFIFOx - Test output FIFO */ 498 u32 rsvd14[15]; 499 }; 500 501 /* RNG4 TRNG test registers */ 502 struct rng4tst { 503 #define RTMCTL_ACC BIT(5) /* TRNG access mode */ 504 #define RTMCTL_PRGM BIT(16) /* 1 -> program mode, 0 -> run mode */ 505 #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC 0 /* use von Neumann data in 506 both entropy shifter and 507 statistical checker */ 508 #define RTMCTL_SAMP_MODE_RAW_ES_SC 1 /* use raw data in both 509 entropy shifter and 510 statistical checker */ 511 #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC 2 /* use von Neumann data in 512 entropy shifter, raw data 513 in statistical checker */ 514 #define RTMCTL_SAMP_MODE_INVALID 3 /* invalid combination */ 515 u32 rtmctl; /* misc. control register */ 516 u32 rtscmisc; /* statistical check misc. register */ 517 u32 rtpkrrng; /* poker range register */ 518 union { 519 u32 rtpkrmax; /* PRGM=1: poker max. limit register */ 520 u32 rtpkrsq; /* PRGM=0: poker square calc. result register */ 521 }; 522 #define RTSDCTL_ENT_DLY_SHIFT 16 523 #define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT) 524 #define RTSDCTL_ENT_DLY_MIN 3200 525 #define RTSDCTL_ENT_DLY_MAX 12800 526 #define RTSDCTL_SAMP_SIZE_MASK 0xffff 527 #define RTSDCTL_SAMP_SIZE_VAL 512 528 u32 rtsdctl; /* seed control register */ 529 union { 530 u32 rtsblim; /* PRGM=1: sparse bit limit register */ 531 u32 rttotsam; /* PRGM=0: total samples register */ 532 }; 533 u32 rtfrqmin; /* frequency count min. limit register */ 534 #define RTFRQMAX_DISABLE (1 << 20) 535 union { 536 u32 rtfrqmax; /* PRGM=1: freq. count max. limit register */ 537 u32 rtfrqcnt; /* PRGM=0: freq. count register */ 538 }; 539 union { 540 u32 rtscmc; /* statistical check run monobit count */ 541 u32 rtscml; /* statistical check run monobit limit */ 542 }; 543 union { 544 u32 rtscrc[6]; /* statistical check run length count */ 545 u32 rtscrl[6]; /* statistical check run length limit */ 546 }; 547 u32 rsvd1[33]; 548 #define RDSTA_SKVT 0x80000000 549 #define RDSTA_SKVN 0x40000000 550 #define RDSTA_PR0 BIT(4) 551 #define RDSTA_PR1 BIT(5) 552 #define RDSTA_IF0 0x00000001 553 #define RDSTA_IF1 0x00000002 554 #define RDSTA_MASK (RDSTA_PR1 | RDSTA_PR0 | RDSTA_IF1 | RDSTA_IF0) 555 u32 rdsta; 556 u32 rsvd2[15]; 557 }; 558 559 /* 560 * caam_ctrl - basic core configuration 561 * starts base + 0x0000 padded out to 0x1000 562 */ 563 564 #define KEK_KEY_SIZE 8 565 #define TKEK_KEY_SIZE 8 566 #define TDSK_KEY_SIZE 8 567 568 #define DECO_RESET 1 /* Use with DECO reset/availability regs */ 569 #define DECO_RESET_0 (DECO_RESET << 0) 570 #define DECO_RESET_1 (DECO_RESET << 1) 571 #define DECO_RESET_2 (DECO_RESET << 2) 572 #define DECO_RESET_3 (DECO_RESET << 3) 573 #define DECO_RESET_4 (DECO_RESET << 4) 574 575 struct caam_ctrl { 576 /* Basic Configuration Section 000-01f */ 577 /* Read/Writable */ 578 u32 rsvd1; 579 u32 mcr; /* MCFG Master Config Register */ 580 u32 rsvd2; 581 u32 scfgr; /* SCFGR, Security Config Register */ 582 583 /* Bus Access Configuration Section 010-11f */ 584 /* Read/Writable */ 585 struct masterid jr_mid[4]; /* JRxLIODNR - JobR LIODN setup */ 586 u32 rsvd3[11]; 587 u32 jrstart; /* JRSTART - Job Ring Start Register */ 588 struct masterid rtic_mid[4]; /* RTICxLIODNR - RTIC LIODN setup */ 589 u32 rsvd4[5]; 590 u32 deco_rsr; /* DECORSR - Deco Request Source */ 591 u32 rsvd11; 592 u32 deco_rq; /* DECORR - DECO Request */ 593 struct partid deco_mid[5]; /* DECOxLIODNR - 1 per DECO */ 594 u32 rsvd5[22]; 595 596 /* DECO Availability/Reset Section 120-3ff */ 597 u32 deco_avail; /* DAR - DECO availability */ 598 u32 deco_reset; /* DRR - DECO reset */ 599 u32 rsvd6[182]; 600 601 /* Key Encryption/Decryption Configuration 400-5ff */ 602 /* Read/Writable only while in Non-secure mode */ 603 u32 kek[KEK_KEY_SIZE]; /* JDKEKR - Key Encryption Key */ 604 u32 tkek[TKEK_KEY_SIZE]; /* TDKEKR - Trusted Desc KEK */ 605 u32 tdsk[TDSK_KEY_SIZE]; /* TDSKR - Trusted Desc Signing Key */ 606 u32 rsvd7[32]; 607 u64 sknonce; /* SKNR - Secure Key Nonce */ 608 u32 rsvd8[70]; 609 610 /* RNG Test/Verification/Debug Access 600-7ff */ 611 /* (Useful in Test/Debug modes only...) */ 612 union { 613 struct rngtst rtst[2]; 614 struct rng4tst r4tst[2]; 615 }; 616 617 u32 rsvd9[416]; 618 619 /* Version registers - introduced with era 10 e80-eff */ 620 struct version_regs vreg; 621 /* Performance Monitor f00-fff */ 622 struct caam_perfmon perfmon; 623 }; 624 625 /* 626 * Controller master config register defs 627 */ 628 #define MCFGR_SWRESET 0x80000000 /* software reset */ 629 #define MCFGR_WDENABLE 0x40000000 /* DECO watchdog enable */ 630 #define MCFGR_WDFAIL 0x20000000 /* DECO watchdog force-fail */ 631 #define MCFGR_DMA_RESET 0x10000000 632 #define MCFGR_LONG_PTR 0x00010000 /* Use >32-bit desc addressing */ 633 #define SCFGR_RDBENABLE 0x00000400 634 #define SCFGR_VIRT_EN 0x00008000 635 #define DECORR_RQD0ENABLE 0x00000001 /* Enable DECO0 for direct access */ 636 #define DECORSR_JR0 0x00000001 /* JR to supply TZ, SDID, ICID */ 637 #define DECORSR_VALID 0x80000000 638 #define DECORR_DEN0 0x00010000 /* DECO0 available for access*/ 639 640 /* AXI read cache control */ 641 #define MCFGR_ARCACHE_SHIFT 12 642 #define MCFGR_ARCACHE_MASK (0xf << MCFGR_ARCACHE_SHIFT) 643 #define MCFGR_ARCACHE_BUFF (0x1 << MCFGR_ARCACHE_SHIFT) 644 #define MCFGR_ARCACHE_CACH (0x2 << MCFGR_ARCACHE_SHIFT) 645 #define MCFGR_ARCACHE_RALL (0x4 << MCFGR_ARCACHE_SHIFT) 646 647 /* AXI write cache control */ 648 #define MCFGR_AWCACHE_SHIFT 8 649 #define MCFGR_AWCACHE_MASK (0xf << MCFGR_AWCACHE_SHIFT) 650 #define MCFGR_AWCACHE_BUFF (0x1 << MCFGR_AWCACHE_SHIFT) 651 #define MCFGR_AWCACHE_CACH (0x2 << MCFGR_AWCACHE_SHIFT) 652 #define MCFGR_AWCACHE_WALL (0x8 << MCFGR_AWCACHE_SHIFT) 653 654 /* AXI pipeline depth */ 655 #define MCFGR_AXIPIPE_SHIFT 4 656 #define MCFGR_AXIPIPE_MASK (0xf << MCFGR_AXIPIPE_SHIFT) 657 658 #define MCFGR_AXIPRI 0x00000008 /* Assert AXI priority sideband */ 659 #define MCFGR_LARGE_BURST 0x00000004 /* 128/256-byte burst size */ 660 #define MCFGR_BURST_64 0x00000001 /* 64-byte burst size */ 661 662 /* JRSTART register offsets */ 663 #define JRSTART_JR0_START 0x00000001 /* Start Job ring 0 */ 664 #define JRSTART_JR1_START 0x00000002 /* Start Job ring 1 */ 665 #define JRSTART_JR2_START 0x00000004 /* Start Job ring 2 */ 666 #define JRSTART_JR3_START 0x00000008 /* Start Job ring 3 */ 667 668 /* 669 * caam_job_ring - direct job ring setup 670 * 1-4 possible per instantiation, base + 1000/2000/3000/4000 671 * Padded out to 0x1000 672 */ 673 struct caam_job_ring { 674 /* Input ring */ 675 u64 inpring_base; /* IRBAx - Input desc ring baseaddr */ 676 u32 rsvd1; 677 u32 inpring_size; /* IRSx - Input ring size */ 678 u32 rsvd2; 679 u32 inpring_avail; /* IRSAx - Input ring room remaining */ 680 u32 rsvd3; 681 u32 inpring_jobadd; /* IRJAx - Input ring jobs added */ 682 683 /* Output Ring */ 684 u64 outring_base; /* ORBAx - Output status ring base addr */ 685 u32 rsvd4; 686 u32 outring_size; /* ORSx - Output ring size */ 687 u32 rsvd5; 688 u32 outring_rmvd; /* ORJRx - Output ring jobs removed */ 689 u32 rsvd6; 690 u32 outring_used; /* ORSFx - Output ring slots full */ 691 692 /* Status/Configuration */ 693 u32 rsvd7; 694 u32 jroutstatus; /* JRSTAx - JobR output status */ 695 u32 rsvd8; 696 u32 jrintstatus; /* JRINTx - JobR interrupt status */ 697 u32 rconfig_hi; /* JRxCFG - Ring configuration */ 698 u32 rconfig_lo; 699 700 /* Indices. CAAM maintains as "heads" of each queue */ 701 u32 rsvd9; 702 u32 inp_rdidx; /* IRRIx - Input ring read index */ 703 u32 rsvd10; 704 u32 out_wtidx; /* ORWIx - Output ring write index */ 705 706 /* Command/control */ 707 u32 rsvd11; 708 u32 jrcommand; /* JRCRx - JobR command */ 709 710 u32 rsvd12[900]; 711 712 /* Version registers - introduced with era 10 e80-eff */ 713 struct version_regs vreg; 714 /* Performance Monitor f00-fff */ 715 struct caam_perfmon perfmon; 716 }; 717 718 #define JR_RINGSIZE_MASK 0x03ff 719 /* 720 * jrstatus - Job Ring Output Status 721 * All values in lo word 722 * Also note, same values written out as status through QI 723 * in the command/status field of a frame descriptor 724 */ 725 #define JRSTA_SSRC_SHIFT 28 726 #define JRSTA_SSRC_MASK 0xf0000000 727 728 #define JRSTA_SSRC_NONE 0x00000000 729 #define JRSTA_SSRC_CCB_ERROR 0x20000000 730 #define JRSTA_SSRC_JUMP_HALT_USER 0x30000000 731 #define JRSTA_SSRC_DECO 0x40000000 732 #define JRSTA_SSRC_QI 0x50000000 733 #define JRSTA_SSRC_JRERROR 0x60000000 734 #define JRSTA_SSRC_JUMP_HALT_CC 0x70000000 735 736 #define JRSTA_DECOERR_JUMP 0x08000000 737 #define JRSTA_DECOERR_INDEX_SHIFT 8 738 #define JRSTA_DECOERR_INDEX_MASK 0xff00 739 #define JRSTA_DECOERR_ERROR_MASK 0x00ff 740 741 #define JRSTA_DECOERR_NONE 0x00 742 #define JRSTA_DECOERR_LINKLEN 0x01 743 #define JRSTA_DECOERR_LINKPTR 0x02 744 #define JRSTA_DECOERR_JRCTRL 0x03 745 #define JRSTA_DECOERR_DESCCMD 0x04 746 #define JRSTA_DECOERR_ORDER 0x05 747 #define JRSTA_DECOERR_KEYCMD 0x06 748 #define JRSTA_DECOERR_LOADCMD 0x07 749 #define JRSTA_DECOERR_STORECMD 0x08 750 #define JRSTA_DECOERR_OPCMD 0x09 751 #define JRSTA_DECOERR_FIFOLDCMD 0x0a 752 #define JRSTA_DECOERR_FIFOSTCMD 0x0b 753 #define JRSTA_DECOERR_MOVECMD 0x0c 754 #define JRSTA_DECOERR_JUMPCMD 0x0d 755 #define JRSTA_DECOERR_MATHCMD 0x0e 756 #define JRSTA_DECOERR_SHASHCMD 0x0f 757 #define JRSTA_DECOERR_SEQCMD 0x10 758 #define JRSTA_DECOERR_DECOINTERNAL 0x11 759 #define JRSTA_DECOERR_SHDESCHDR 0x12 760 #define JRSTA_DECOERR_HDRLEN 0x13 761 #define JRSTA_DECOERR_BURSTER 0x14 762 #define JRSTA_DECOERR_DESCSIGNATURE 0x15 763 #define JRSTA_DECOERR_DMA 0x16 764 #define JRSTA_DECOERR_BURSTFIFO 0x17 765 #define JRSTA_DECOERR_JRRESET 0x1a 766 #define JRSTA_DECOERR_JOBFAIL 0x1b 767 #define JRSTA_DECOERR_DNRERR 0x80 768 #define JRSTA_DECOERR_UNDEFPCL 0x81 769 #define JRSTA_DECOERR_PDBERR 0x82 770 #define JRSTA_DECOERR_ANRPLY_LATE 0x83 771 #define JRSTA_DECOERR_ANRPLY_REPLAY 0x84 772 #define JRSTA_DECOERR_SEQOVF 0x85 773 #define JRSTA_DECOERR_INVSIGN 0x86 774 #define JRSTA_DECOERR_DSASIGN 0x87 775 776 #define JRSTA_QIERR_ERROR_MASK 0x00ff 777 778 #define JRSTA_CCBERR_JUMP 0x08000000 779 #define JRSTA_CCBERR_INDEX_MASK 0xff00 780 #define JRSTA_CCBERR_INDEX_SHIFT 8 781 #define JRSTA_CCBERR_CHAID_MASK 0x00f0 782 #define JRSTA_CCBERR_CHAID_SHIFT 4 783 #define JRSTA_CCBERR_ERRID_MASK 0x000f 784 785 #define JRSTA_CCBERR_CHAID_AES (0x01 << JRSTA_CCBERR_CHAID_SHIFT) 786 #define JRSTA_CCBERR_CHAID_DES (0x02 << JRSTA_CCBERR_CHAID_SHIFT) 787 #define JRSTA_CCBERR_CHAID_ARC4 (0x03 << JRSTA_CCBERR_CHAID_SHIFT) 788 #define JRSTA_CCBERR_CHAID_MD (0x04 << JRSTA_CCBERR_CHAID_SHIFT) 789 #define JRSTA_CCBERR_CHAID_RNG (0x05 << JRSTA_CCBERR_CHAID_SHIFT) 790 #define JRSTA_CCBERR_CHAID_SNOW (0x06 << JRSTA_CCBERR_CHAID_SHIFT) 791 #define JRSTA_CCBERR_CHAID_KASUMI (0x07 << JRSTA_CCBERR_CHAID_SHIFT) 792 #define JRSTA_CCBERR_CHAID_PK (0x08 << JRSTA_CCBERR_CHAID_SHIFT) 793 #define JRSTA_CCBERR_CHAID_CRC (0x09 << JRSTA_CCBERR_CHAID_SHIFT) 794 795 #define JRSTA_CCBERR_ERRID_NONE 0x00 796 #define JRSTA_CCBERR_ERRID_MODE 0x01 797 #define JRSTA_CCBERR_ERRID_DATASIZ 0x02 798 #define JRSTA_CCBERR_ERRID_KEYSIZ 0x03 799 #define JRSTA_CCBERR_ERRID_PKAMEMSZ 0x04 800 #define JRSTA_CCBERR_ERRID_PKBMEMSZ 0x05 801 #define JRSTA_CCBERR_ERRID_SEQUENCE 0x06 802 #define JRSTA_CCBERR_ERRID_PKDIVZRO 0x07 803 #define JRSTA_CCBERR_ERRID_PKMODEVN 0x08 804 #define JRSTA_CCBERR_ERRID_KEYPARIT 0x09 805 #define JRSTA_CCBERR_ERRID_ICVCHK 0x0a 806 #define JRSTA_CCBERR_ERRID_HARDWARE 0x0b 807 #define JRSTA_CCBERR_ERRID_CCMAAD 0x0c 808 #define JRSTA_CCBERR_ERRID_INVCHA 0x0f 809 810 #define JRINT_ERR_INDEX_MASK 0x3fff0000 811 #define JRINT_ERR_INDEX_SHIFT 16 812 #define JRINT_ERR_TYPE_MASK 0xf00 813 #define JRINT_ERR_TYPE_SHIFT 8 814 #define JRINT_ERR_HALT_MASK 0xc 815 #define JRINT_ERR_HALT_SHIFT 2 816 #define JRINT_ERR_HALT_INPROGRESS 0x4 817 #define JRINT_ERR_HALT_COMPLETE 0x8 818 #define JRINT_JR_ERROR 0x02 819 #define JRINT_JR_INT 0x01 820 821 #define JRINT_ERR_TYPE_WRITE 1 822 #define JRINT_ERR_TYPE_BAD_INPADDR 3 823 #define JRINT_ERR_TYPE_BAD_OUTADDR 4 824 #define JRINT_ERR_TYPE_INV_INPWRT 5 825 #define JRINT_ERR_TYPE_INV_OUTWRT 6 826 #define JRINT_ERR_TYPE_RESET 7 827 #define JRINT_ERR_TYPE_REMOVE_OFL 8 828 #define JRINT_ERR_TYPE_ADD_OFL 9 829 830 #define JRCFG_SOE 0x04 831 #define JRCFG_ICEN 0x02 832 #define JRCFG_IMSK 0x01 833 #define JRCFG_ICDCT_SHIFT 8 834 #define JRCFG_ICTT_SHIFT 16 835 836 #define JRCR_RESET 0x01 837 838 /* 839 * caam_assurance - Assurance Controller View 840 * base + 0x6000 padded out to 0x1000 841 */ 842 843 struct rtic_element { 844 u64 address; 845 u32 rsvd; 846 u32 length; 847 }; 848 849 struct rtic_block { 850 struct rtic_element element[2]; 851 }; 852 853 struct rtic_memhash { 854 u32 memhash_be[32]; 855 u32 memhash_le[32]; 856 }; 857 858 struct caam_assurance { 859 /* Status/Command/Watchdog */ 860 u32 rsvd1; 861 u32 status; /* RSTA - Status */ 862 u32 rsvd2; 863 u32 cmd; /* RCMD - Command */ 864 u32 rsvd3; 865 u32 ctrl; /* RCTL - Control */ 866 u32 rsvd4; 867 u32 throttle; /* RTHR - Throttle */ 868 u32 rsvd5[2]; 869 u64 watchdog; /* RWDOG - Watchdog Timer */ 870 u32 rsvd6; 871 u32 rend; /* REND - Endian corrections */ 872 u32 rsvd7[50]; 873 874 /* Block access/configuration @ 100/110/120/130 */ 875 struct rtic_block memblk[4]; /* Memory Blocks A-D */ 876 u32 rsvd8[32]; 877 878 /* Block hashes @ 200/300/400/500 */ 879 struct rtic_memhash hash[4]; /* Block hash values A-D */ 880 u32 rsvd_3[640]; 881 }; 882 883 /* 884 * caam_queue_if - QI configuration and control 885 * starts base + 0x7000, padded out to 0x1000 long 886 */ 887 888 struct caam_queue_if { 889 u32 qi_control_hi; /* QICTL - QI Control */ 890 u32 qi_control_lo; 891 u32 rsvd1; 892 u32 qi_status; /* QISTA - QI Status */ 893 u32 qi_deq_cfg_hi; /* QIDQC - QI Dequeue Configuration */ 894 u32 qi_deq_cfg_lo; 895 u32 qi_enq_cfg_hi; /* QISEQC - QI Enqueue Command */ 896 u32 qi_enq_cfg_lo; 897 u32 rsvd2[1016]; 898 }; 899 900 /* QI control bits - low word */ 901 #define QICTL_DQEN 0x01 /* Enable frame pop */ 902 #define QICTL_STOP 0x02 /* Stop dequeue/enqueue */ 903 #define QICTL_SOE 0x04 /* Stop on error */ 904 905 /* QI control bits - high word */ 906 #define QICTL_MBSI 0x01 907 #define QICTL_MHWSI 0x02 908 #define QICTL_MWSI 0x04 909 #define QICTL_MDWSI 0x08 910 #define QICTL_CBSI 0x10 /* CtrlDataByteSwapInput */ 911 #define QICTL_CHWSI 0x20 /* CtrlDataHalfSwapInput */ 912 #define QICTL_CWSI 0x40 /* CtrlDataWordSwapInput */ 913 #define QICTL_CDWSI 0x80 /* CtrlDataDWordSwapInput */ 914 #define QICTL_MBSO 0x0100 915 #define QICTL_MHWSO 0x0200 916 #define QICTL_MWSO 0x0400 917 #define QICTL_MDWSO 0x0800 918 #define QICTL_CBSO 0x1000 /* CtrlDataByteSwapOutput */ 919 #define QICTL_CHWSO 0x2000 /* CtrlDataHalfSwapOutput */ 920 #define QICTL_CWSO 0x4000 /* CtrlDataWordSwapOutput */ 921 #define QICTL_CDWSO 0x8000 /* CtrlDataDWordSwapOutput */ 922 #define QICTL_DMBS 0x010000 923 #define QICTL_EPO 0x020000 924 925 /* QI status bits */ 926 #define QISTA_PHRDERR 0x01 /* PreHeader Read Error */ 927 #define QISTA_CFRDERR 0x02 /* Compound Frame Read Error */ 928 #define QISTA_OFWRERR 0x04 /* Output Frame Read Error */ 929 #define QISTA_BPDERR 0x08 /* Buffer Pool Depleted */ 930 #define QISTA_BTSERR 0x10 /* Buffer Undersize */ 931 #define QISTA_CFWRERR 0x20 /* Compound Frame Write Err */ 932 #define QISTA_STOPD 0x80000000 /* QI Stopped (see QICTL) */ 933 934 /* deco_sg_table - DECO view of scatter/gather table */ 935 struct deco_sg_table { 936 u64 addr; /* Segment Address */ 937 u32 elen; /* E, F bits + 30-bit length */ 938 u32 bpid_offset; /* Buffer Pool ID + 16-bit length */ 939 }; 940 941 /* 942 * caam_deco - descriptor controller - CHA cluster block 943 * 944 * Only accessible when direct DECO access is turned on 945 * (done in DECORR, via MID programmed in DECOxMID 946 * 947 * 5 typical, base + 0x8000/9000/a000/b000 948 * Padded out to 0x1000 long 949 */ 950 struct caam_deco { 951 u32 rsvd1; 952 u32 cls1_mode; /* CxC1MR - Class 1 Mode */ 953 u32 rsvd2; 954 u32 cls1_keysize; /* CxC1KSR - Class 1 Key Size */ 955 u32 cls1_datasize_hi; /* CxC1DSR - Class 1 Data Size */ 956 u32 cls1_datasize_lo; 957 u32 rsvd3; 958 u32 cls1_icvsize; /* CxC1ICVSR - Class 1 ICV size */ 959 u32 rsvd4[5]; 960 u32 cha_ctrl; /* CCTLR - CHA control */ 961 u32 rsvd5; 962 u32 irq_crtl; /* CxCIRQ - CCB interrupt done/error/clear */ 963 u32 rsvd6; 964 u32 clr_written; /* CxCWR - Clear-Written */ 965 u32 ccb_status_hi; /* CxCSTA - CCB Status/Error */ 966 u32 ccb_status_lo; 967 u32 rsvd7[3]; 968 u32 aad_size; /* CxAADSZR - Current AAD Size */ 969 u32 rsvd8; 970 u32 cls1_iv_size; /* CxC1IVSZR - Current Class 1 IV Size */ 971 u32 rsvd9[7]; 972 u32 pkha_a_size; /* PKASZRx - Size of PKHA A */ 973 u32 rsvd10; 974 u32 pkha_b_size; /* PKBSZRx - Size of PKHA B */ 975 u32 rsvd11; 976 u32 pkha_n_size; /* PKNSZRx - Size of PKHA N */ 977 u32 rsvd12; 978 u32 pkha_e_size; /* PKESZRx - Size of PKHA E */ 979 u32 rsvd13[24]; 980 u32 cls1_ctx[16]; /* CxC1CTXR - Class 1 Context @100 */ 981 u32 rsvd14[48]; 982 u32 cls1_key[8]; /* CxC1KEYR - Class 1 Key @200 */ 983 u32 rsvd15[121]; 984 u32 cls2_mode; /* CxC2MR - Class 2 Mode */ 985 u32 rsvd16; 986 u32 cls2_keysize; /* CxX2KSR - Class 2 Key Size */ 987 u32 cls2_datasize_hi; /* CxC2DSR - Class 2 Data Size */ 988 u32 cls2_datasize_lo; 989 u32 rsvd17; 990 u32 cls2_icvsize; /* CxC2ICVSZR - Class 2 ICV Size */ 991 u32 rsvd18[56]; 992 u32 cls2_ctx[18]; /* CxC2CTXR - Class 2 Context @500 */ 993 u32 rsvd19[46]; 994 u32 cls2_key[32]; /* CxC2KEYR - Class2 Key @600 */ 995 u32 rsvd20[84]; 996 u32 inp_infofifo_hi; /* CxIFIFO - Input Info FIFO @7d0 */ 997 u32 inp_infofifo_lo; 998 u32 rsvd21[2]; 999 u64 inp_datafifo; /* CxDFIFO - Input Data FIFO */ 1000 u32 rsvd22[2]; 1001 u64 out_datafifo; /* CxOFIFO - Output Data FIFO */ 1002 u32 rsvd23[2]; 1003 u32 jr_ctl_hi; /* CxJRR - JobR Control Register @800 */ 1004 u32 jr_ctl_lo; 1005 u64 jr_descaddr; /* CxDADR - JobR Descriptor Address */ 1006 #define DECO_OP_STATUS_HI_ERR_MASK 0xF00000FF 1007 u32 op_status_hi; /* DxOPSTA - DECO Operation Status */ 1008 u32 op_status_lo; 1009 u32 rsvd24[2]; 1010 u32 liodn; /* DxLSR - DECO LIODN Status - non-seq */ 1011 u32 td_liodn; /* DxLSR - DECO LIODN Status - trustdesc */ 1012 u32 rsvd26[6]; 1013 u64 math[4]; /* DxMTH - Math register */ 1014 u32 rsvd27[8]; 1015 struct deco_sg_table gthr_tbl[4]; /* DxGTR - Gather Tables */ 1016 u32 rsvd28[16]; 1017 struct deco_sg_table sctr_tbl[4]; /* DxSTR - Scatter Tables */ 1018 u32 rsvd29[48]; 1019 u32 descbuf[64]; /* DxDESB - Descriptor buffer */ 1020 u32 rscvd30[193]; 1021 #define DESC_DBG_DECO_STAT_VALID 0x80000000 1022 #define DESC_DBG_DECO_STAT_MASK 0x00F00000 1023 #define DESC_DBG_DECO_STAT_SHIFT 20 1024 u32 desc_dbg; /* DxDDR - DECO Debug Register */ 1025 u32 rsvd31[13]; 1026 #define DESC_DER_DECO_STAT_MASK 0x000F0000 1027 #define DESC_DER_DECO_STAT_SHIFT 16 1028 u32 dbg_exec; /* DxDER - DECO Debug Exec Register */ 1029 u32 rsvd32[112]; 1030 }; 1031 1032 #define DECO_STAT_HOST_ERR 0xD 1033 1034 #define DECO_JQCR_WHL 0x20000000 1035 #define DECO_JQCR_FOUR 0x10000000 1036 1037 #define JR_BLOCK_NUMBER 1 1038 #define ASSURE_BLOCK_NUMBER 6 1039 #define QI_BLOCK_NUMBER 7 1040 #define DECO_BLOCK_NUMBER 8 1041 #define PG_SIZE_4K 0x1000 1042 #define PG_SIZE_64K 0x10000 1043 #endif /* REGS_H */ 1044